RT9244
Multi-Phase PWM Controller for CPU Core Power Supply
General Description
Features
The RT9244 is a multi-phase buck DC/DC controller
integrated with all control functions for GHz CPU VRM.
The RT9244 controls 2, 3 or 4 buck switching stages
operating in interleaved phase set automatically. The multiphase architecture provides high output current while
maintaining low power dissipation on power devices and
low stress on input and output capacitors. The high
equivalent operating frequency also reduces the component
dimension and the output voltage ripple in load transient.
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Multi-Phase Power Conversion with Automatic
Phase Selection
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K8 DAC Output with Active Droop Compens-ation
for Fast Load Transient
Smooth VCORE Transition at VID Jump
Power Stage Thermal Balance by RDS(ON) Current
Sense
Hiccup Mode Over-Current Protection
Programmable Switching Frequency (50kHz to
400kHz per Phase), Under-Voltage Lockout and
Soft-Start
High Ripple Frequency Times Channel Number
RoHS Compliant and 100% Lead (Pb)-Free
RT9244 controls both voltage and current loops to achieve
good regulation, response & power stage thermal balance.
Precise current loop using RDS(ON) as sense component
builds precise load line for strict VRM DC & transient
specification and also ensures thermal balance of different
power stages. The settings of current sense, droop tuning,
V CORE initial offset and over current protection are
independent to compensation circuit of voltage loop. The
feature greatly facilitates the flexibility of CPU power supply
design and tuning.
The DAC output of RT9244 supports K8 CPU by 5-bit VID
input, precise initial value & smooth VCORE transient at VID
jump. The IC monitors the VCORE voltage for PGOOD and
over-voltage protection. Soft-start, over-current protection
and programmable under-voltage lockout are also provided
to assure the safety of microprocessor and power system.
Ordering Information
RT9244
Package Type
S : SOP-32
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commercial Standard)
Note :
RichTek Pb-free and Green products are :
`RoHS compliant and compatible with the current require-
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z
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Applications
AMD® AthlonTM 64 and OpteronTM Processors Voltage
Regulator
z Low Output Voltage, High Current DC-DC Converters
z Voltage Regulator Modules
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Pin Configurations
(TOP VIEW)
SS
OVP
VID4
VID3
VID2
VID1
VID0
VOSS
COMP
FB
ADJ
VDIF
VSEN
SGND
ISN4
ISN3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DVD
RT
PGOOD
PWM4
ISP4
ISP1
PWM1
PWM2
GND
ISP2
ISP3
PWM3
VCC
SS2
ISN1
ISN2
SOP-32
ments of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
`100%matte tin (Sn) plating.
DS9244-06 March 2007
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1
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2
OVP
<
33pF
C4
22nF
C2
0.1uF
C3
R3
2.4k
2
19
7
6
5
4
3
30
16
15
12
9
10
1
11
R1 100k 8
C1
0.1uF
R2
15K
VID0 >
VID1 >
VID2 >
VID3 >
VID4 >
PG_VCORE <
R4
2k
ISN3
ISN4
VIDF
COMP
FB
SS
ADJ
VOSS
SS2
VID0
VID1
VID2
VID3
VID4
PGOOD
OVP
RT
ISN2
ISN1
VSEN
SGND
GND
PWM3
ISP3
ISP1
PWM1
PWM2
ISP2
ISP4
PWM4
VCC
DVD
RT9244
C5
1uF
17
18
13
14
24
21
22
27
26
25
23
28
29
20
32
31
+5V
R12 2k
R11 2k
R10 2k
R9 2k
R8
2k
R6
12k
R7
1k
R5
4.7k
+12V
C16
1uF
R17
10
+12V
C11
1uF
R15
10
+12V
C6
1uF
R13
10
+12V
3
6
7
2
3
6
7
2
3
6
7
2
C12
1uF
GND
4
LGATE
PHASE
UGATE
C17
1uF
GND
4
LGATE
PHASE
UGATE
PWM
VCC
PVCC
BOOT
GND
4
LGATE
PHASE
UGATE
RT9600
PWM
VCC
PVCC
BOOT
RT9600
PWM
VCC
PVCC
BOOT
RT9600
C7
1uF
5
8
1
5
8
1
5
8
1
IPD06N03LA
Q6
IPD09N03LA
Q5
+12V
IPD06N03LA
Q4
IPD09N03LA
Q3
+12V
IPD06N03LA
Q2
IPD09N03LA
Q1
+12V
C8
4.7uF
C18
4.7uF
C13
4.7uF
C20
0.01uF
R18
4.7
1uH
C19
2200uF
C15
0.01uF
R16
4.7
1uH
C14
2200uF
C10
0.01uF
R14
4.7
1uH
C9
2200uF
C26 to C29
2200uF x 4
C21 to C25
2200uF x 5
VCORE
RT9244
Typical Application Circuit
DS9244-06 March 2007
RT9244
Functional Pin Description
SS (Pin 1)
Connect this SS pin to GND with a capacitor to set the
start time interval. Pull this pin below 1V (ramp valley of
sawtooth wave in pulse width modulator) to shutdown the
converter output.
to GND with a capacitor to set the rising/falling time at VID
jump.
VCC (Pin 20)
IC power supply. Connect this pin to a 5V supply.
OVP (Pin 2)
GND (Pin 21)
Over voltage trip output.
Ground for the IC.
VID4 (Pin 3), VID3 (Pin 4), VID2 (Pin 5), VID1 (Pin 6),
VID0 (Pin 7)
PWM1 (Pin 26), PWM2 (Pin 25), PWM3 (Pin 21) &
PWM4 (Pin 29)
DAC voltage identification inputs for K8. These pins are
internally pulled to 2.4V if left open.
PWM outputs for each driven channel. Connect these pins
to the PWM input of the MOSFET driver. For systems
which use 3 channels, connect PWM4 high. Two channel
systems connect PWM3 and PWM4 high.
VOSS (Pin 8)
VCORE initial value offset. Connect this pin to GND with a
resistor to set the offset value.
COMP (Pin 9)
Output of the error amplifier and input of the PWM
comparator.
FB (Pin 10)
Inverting input of the internal error amplifier.
ADJ (Pin 11)
Current sense output for active droop adjust. Connect a
resistor from this pin to GND to set the load droop.
ISP1 (Pin 27), ISP2 (Pin 23), ISP3 (Pin 22) & ISP4
(Pin 28)
RDS(ON) current sense inputs for each individual converter
channel. Tie this pin to the component's sense node.
PGOOD (Pin 30)
Power good open-drain output.
RT (Pin 31)
Switching frequency setting. Connect this pin to GND with
a resistor to set the frequency.
Frequency vs. RRT
450
VDIF (Pin 12)
400
VCORE differential sense output.
350
VCORE differential sense positive input.
300
f OSC(kHz)
VSEN (Pin 13)
250
200
SGND (Pin 14)
150
VCORE differential sense negative input.
100
50
ISN1 (Pin 18), ISN2 (Pin 17), ISN3 (Pin 16) & ISN4
(Pin 15)
RDS(ON) current sense inputs from each individual converter
channel sense component's GND node.
SS2 (Pin 19)
DAC O/P ramping speed control for K8. Connect this pin
DS9244-06 March 2007
0
0
10
20
30
40
50
60
70
RRT (kΩ)
DVD (Pin 32)
Programmable power UVLO detection input. Trip threshold
= 2.0V at VDVD rising.
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3
VSEN
SGND
VOSS
Buffer
Amplifier
+
-
Offset Currrent
Source/Sink
VDIF
FB
Error
Amplifier
COMP
PG Trip
Point
+
-
DAC + Droop
SS
SS
Control
GAP
Amplifier
-
+
+
-
OVP Trip
Point
ADJ
OCP
Setting
INH
GND
-
+
-
+
-
+
-
+
+
-
DAC
Oscillator
&
Sawtooth
SUM/M
Current
Correction
+ +
+ +
+ +
+ +
INH
PWMCP
INH
PWMCP
INH
PWMCP
INH
PWMCP
-
+
Power On Reset
+
-
VID0
VID1
VID2
VID3
VID4
SS2
+
-
RT
ISN4
ISP4
ISP3
ISP2
ISN3
ISN2
ISP1
PWM4
PWM3
PWM2
PWM1
ISN1
PWM Logic
& Driver
PWM Logic
& Driver
PWM Logic
& Driver
PWM Logic
& Driver
-
+
+
-
+
+
+
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4
-
OVP PGOOD VCC DVD
RT9244
Function Block Diagram
DS9244-06 March 2007
RT9244
Table 1. Output Voltage Program
VID4
VID3
VID2
VID1
VID0
Nominal Output Voltage DACOUT
0
0
0
0
0
1.550
0
0
0
0
1
1.525
0
0
0
1
0
1.500
0
0
0
1
1
1.475
0
0
1
0
0
1.450
0
0
1
0
1
1.425
0
0
1
1
0
1.400
0
0
1
1
1
1.375
0
1
0
0
0
1.350
0
1
0
0
1
1.325
0
1
0
1
0
1.200
0
1
0
1
1
1.275
0
1
1
0
0
1.250
0
1
1
0
1
1.225
0
1
1
1
0
1.200
0
1
1
1
1
1.175
1
0
0
0
0
1.150
1
0
0
0
1
1.125
1
0
0
1
0
1.100
1
0
0
1
1
1.075
1
0
1
0
0
1.050
1
0
1
0
1
1.025
1
0
1
1
0
1.000
1
0
1
1
1
0.975
1
1
0
0
0
0.950
1
1
0
0
1
0.925
1
1
0
1
0
0.900
1
1
0
1
1
0.875
1
1
1
0
0
0.850
1
1
1
0
1
0.825
1
1
1
1
0
0.800
1
1
1
1
1
Shutdown
Note: (1) 0 : Connected to GND
(2) 1 : Open
DS9244-06 March 2007
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5
RT9244
Absolute Maximum Ratings
z
z
z
z
z
z
z
(Note 1)
Supply Voltage, VCC ------------------------------------------------------------------------------------------Input, Output or I/O Voltage ---------------------------------------------------------------------------------Package Thermal Resistance
SOP-32, θJA ----------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------ESD Susceptibility (Note 2)
HBM (Human Body Mode) ----------------------------------------------------------------------------------MM (Machine Mode) -------------------------------------------------------------------------------------------
Recommended Operating Conditions
z
z
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7V
GND-0.3V to VCC+0.3V
50°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
(Note 3)
Supply Voltage, VCC ------------------------------------------------------------------------------------------- 5V ± 10%
Ambient Temperature Range --------------------------------------------------------------------------------- 0°C to 70°C
Junction Temperature Range --------------------------------------------------------------------------------- 0°C to 125°C
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
--
12
--
mA
4.0
4.2
4.5
V
0.2
0.5
--
V
--
2.0
--
V
--
50
--
mV
170
200
230
kHz
50
--
400
kHz
--
1.9
--
V
--
1.0
--
V
62
66
75
%
0.55
0.60
0.65
V
VDAC ≥ 1V
−1
--
+1
%
VDAC < 1V
−10
--
+10
mV
VCC Supply Current
ICC
PWM 1,2,3,4 Open
POR Threshold
VCCRTH
VCC Rising
Hysteresis
VCCHYS
Nominal Supply Current
Power-On Reset
VDVD Threshold
Trip (Low to High)
VDVDTP
Hysteresis
VDVDHYS
Enable
Oscillator
Free Running Frequency
fOSC
Frequency Adjustable Range
fOSC_ADJ
Ramp Amplitude
ΔVOSC
Ramp Valley
VRV
RRT = 12kΩ
RRT = 12kΩ
Maximum On-Time of Each Channel
RT Pin Voltage
VRT
R RT = 12kΩ
Reference and DAC
DACOUT Voltage Accuracy
ΔVDAC
DAC (VID0-VID4) Input Low
VILDAC
--
--
0.8
V
DAC (VID0-VID4) Input High
VIHDAC
2.0
--
--
V
To be continued
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6
DS9244-06 March 2007
RT9244
Parameter
Symbol
DAC (VID0-VID4) Bias Current
IBIAS_DAC
VOSS Pin Voltage
VVOSS
Test Conditions
RVOSS = 100kΩ
Min
Typ
Max
Units
30
60
90
μA
0.95
1.0
1.05
V
--
85
--
dB
--
10
--
MHz
--
3
--
V/μs
Error Amplifier
DC Gain
Gain-Bandwidth Product
GBW
Slew Rate
SR
COMP = 10pF
Differential Sense Amplifier
Input Impedance
ZIMP
--
16
--
kΩ
Gain-Bandwidth Product
GBW
--
10
--
MHz
Slew Rate
SR
--
3
--
V/μs
ISP 1,2,3,4 Full Scale Source Current
IISPFSS
60
--
--
μA
ISP 1,2,3,4 Current for OCP
IISPOCP
--
80
--
μA
--
13
--
μA
--
140
--
%
Current Sense GM Amplifier
Protection
SS Current
ISS
Over-Voltage Trip (VSEN/DACOUT)
ΔOVT
OVP Voltage
VOVP
IOVP = 4mA
--
--
0.2
V
Lower Threshold (VSEN/DACOUT)
VPGOOD−
VSEN Rising
--
92
--
%
Output Low Voltage
IPGOODL
IPGOOD = 4mA
--
--
0.2
V
VSS = 1V
Power Good
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
DS9244-06 March 2007
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7
RT9244
Typical Operating Characteristics
Adjustable Frequency
GM
250
500
400
GM1
GM3
GM4
GM2
150
F OSC (kHz)
VADJ (mV)
200
R1 = 3kΩ
100
50
300
200
100
0
0
0
20
40
60
80
100
120
0
10
20
30
40
50
VDS (mV)
RRT (kΩ)
(kohm)
Offset Voltage
Current Sharing at IOUT = 60A
60
35
Dropout Voltage (mV)
30
25
Inductor
Current
20
(5A/Div)
15
10
PWM
(1V/Div)
5
0
0
20
40
60
80
100
120
Time (2.5μs/Div)
Ross (kohm)
Start-up @IOUT = 60A
VSS
Power Off @IOUT = 60A
VSS
(5V/Div)
VOUT
VOUT
PGOOD
PWM
(1V/Div)
PGOOD
(5V/Div)
(5V/Div)
PWM
Time (10ms/Div)
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8
(5V/Div)
(1V/Div)
(5V/Div)
(5V/Div)
Time (100μs/Div)
DS9244-06 March 2007
RT9244
Application Information
RT9244 is a multi-phase DC/DC controller that precisely
regulates CPU core voltage and balances the current of
different power channels. The converter consisting of
RT9244 and its companion MOSFET driver provides high
quality CPU power and all protection functions to meet
the requirement of modern VRM.
Voltage Control
RT9244 senses the CPU VCORE by an precise instrumental
amplifier to minimize the voltage drop on PCB trace at
heavy load. VSEN & SGND are the differential inputs. VDIF
is the output node of the differential voltage & the input for
PGOOD & OVP sense. The internal high accuracy VID
DAC provides the reference voltage for K8 compliance.
Control loop consists of error amplifier, multi-phase pulse
width modulator, driver and power components. Like
conventional voltage mode PWM controller, the output
voltage is locked at the VREF of error amplifier and the error
signal is used as the control signal VC of pulse width
modulator. The PWM signals of different channels are
generated by comparison of EA output and split-phase sawtooth wave. Power stage transforms VIN to output by PWM
signal on-time ratio.
Current Balance
RT9244 senses the current of low side MOSFET in each
synchronous rectifier when it is conducting for channel
current balance and droop tuning. The differential sensing
GM amplifier converts the voltage on the sense component
(can be a sense resistor or the RDS(ON) of the low side
MOSFET) to current signal into internal balance circuit.
The current balance circuit sums and averages the current
signals and then produces the balancing signals injected
to pulse width modulator. If the current of some power
channel is greater than average, the balancing signal
reduces the output pulse width to keep the balance.
Fault Detection
The chip detects VCORE for over voltage and power good
detection. The “hiccup mode” operation of over-current
protection is adopted to reduce the short circuit current.
The inrush current at the start up is suppressed by the
soft start circuit through clamping the pulse width and output
voltage.
Phase Setting and Converter Start Up
RT9244 interfaces with companion MOSFET drivers (like
RT9600, RT9602 series) for correct converter initialization.
The tri-state PWM output (high, low and high impedance)
pins sense the interface voltage at IC POR period (both
VCC and DVD trip). The channel is enabled if the pin voltage
is 1.2V less than VCC. Please tie the PWM output to VCC
and the current sense pins to GND or left floating if the
channel is unused. For 3-Channel application, connect
PWM4 high.
Current Sensing Setting
RT9244 senses the current of low side MOSFET in each
synchronous rectifier when it is conducting for channel
current balance and droop tuning. The differential sensing
GM amplifier converts the voltage on the sense component
(can be a sense resistor or the RDS(ON) of the low side
MOSFET) to current signal into internal circuit (see
Figure 1).
IX
IBP
Sample & Hold
<
<
Load Droop
The sensed power channel current signals regulate the
reference of DAC to form a output voltage droop proportional
to the load current. The droop or so-called “active voltage
positioning” can reduce the output voltage ripple at load
transient and the LC filter size.
DS9244-06 March 2007
<
Current
Balance
GM
+
ISPx
RSP1
RS
ISNx
IBN
IL
RSN1
Droop Tune
Over-Current
Detection
Figure 1. Current Sense Circuit
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9
RT9244
I L × RS
by local feedback.
RSP
RSP = RSN to cancel the voltage drop caused by GM amplifier
input bias current. IX is sampled and held just before low
side MOSFET turns off (See Figure 2). Therefore,
The sensing circuit gets IX =
I L (S/H) × R S
V O T OFF
×
, I L (S/H) = I L (AVG) −
,
R SP
L
2
⎡ V IN − V O ⎤
= ⎢
⎥ × 5uS for fosc = 200kHz
V IN
⎣
⎦
I X (S/H) =
T OFF
I X (S/H)
⎡
⎤
⎡ V IN − V O ⎤
VO − ⎢
⎢
⎥ × 5uS ⎥
RS
IN
V
⎣
⎦
⎥×
= ⎢I L(AVG) −
2L
⎢
⎥ R SP
⎢
⎥
⎣
⎦
Falling Slope = Vo/L
IL
IL(AVG)
IL(S/H)
Inductor Current
PWM Signal & High Side MOSFET Gate Signal
⎛ 0 .6 V ⎞
⎟ × 1 .5 . Controller forces
⎝ 9K ⎠
DAC Offset Voltage & Droop Tuning
The DAC offset voltage is set by compensation network
⎛ 1V ⎞ R f 1
& VOSS pin external resistors by ⎜ R VOSS ⎟ × 4
.
⎝
⎠
The S/H current signals from power channels are injected
to ADJ pin to create droop voltage. VADJ = RADJ× 2 IX
∑
The DAC output voltage decreases by VADJ to form the
VCORE load droop (see Figure 3).
+
Current
Source
∑
2IX1
2IX2
>
1 IVOSS
4
-
RVOSS
FB
ADJ
RF1
RADJ
>
VCORE
Figure 3. DAC Offset Voltage & Droop Tune Circuit
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10
S.S
Count ==22 COUNT
Count ==33
COUNT
Count ==11 COUNT
VCORE
0V
Overload
Applied
ILOAD
+
VOSS
PWM output latched at high impedance to turn off both
high and low side MOSFETs in the power stage and initial
the hiccup mode protection. The SS pin voltage is pulled
low with a 13μA current after it is less than 90% VCC. The
converter restarts after SS pin voltage < 0.2V. Three times
of OCP disable the converter and only release the latch by
POR acts (see Figure 4).
2IX3
2IX4
>
IVOSS
1V
=
RVOSS
+
EA
-
-
COMP
Soft-start circuit generates a ramp voltage by charging
external capacitor with 13μA current after IC POR acts.
The PWM pulse width and VCORE are clamped by the rising
ramp to reduce the inrush current and protect the power
devices.
S/H current signal IX > ⎜
Figure 2. Inductor Current and PWM Signal
VDAC
For OVP, the RT9244 detects the VCORE by VDIF pin voltage
of the differential amplifier output. Eliminate the delay due
to compensation network (compared to sensing FB voltage)
for fast and accurate detection. The trip point of OVP is
140% of normal output level. The PWM outputs are pulled
low to turn on the low side MOSFET and turn off the high
side MOSFET of the synchronous rectifier at OVP. The
OVP latch can only be reset by VCC or DVD restart power
on reset sequence. The PGOOD detection trip point of
VCORE is 92% lower than the normal level. The PGOOD
open drain output pulls low when VCORE is lower than the
trip point. For VID jumping issue, only power fail conditions
(VCC & DVD are lower than trip point or OVP) reset the
output low.
Over-current protection trip point is internally set at around
100μA for each channel. OCP is triggered if one channel
Low Side MOSFET Gate Signal
VADJ
Protection and SS Function
0A
T0,T1
T3,T4
T2
TIME
Figure 4.
DS9244-06 March 2007
RT9244
3-Phase Converter and Components Function Grouping
12V
VCC
PVCC
BOOT
UGATE
PHASE
RT9600
PWM
LGATE
GND
SGND
VSEN
VDIF
PWM1
VID
12V
ISP1
ISN1
OVP
PGOOD
VCC
RT9244
Compensation
& Offset
BOOT
UGATE
VCORE
PHASE
COMP
RT9600
PWM2
FB
PVCC
PWM
LGATE
GND
ADJ
Droop Setting
Driver Power
UVLO
ISP2
ISN2
12V
DVD
12V
VOSS
ISP3
ISN3
VCC
PWM3
PVCC
SS,SS2
DAC Offset
Voltage Setting
RT
GND
Frequency
Setting
BOOT
UGATE
PHASE
RT9600
PWM
LGATE
GND
Current Sense
Components
Design Procedure Suggestion
Voltage Loop Setting
a. Output filter pole and zero (Inductor, output capacitor
value & ESR).
b. Error amplifier compensation & sawtooth wave amplitude (compensation network).
c. Kelvin sense for VCORE.
VRM Load Line Setting
a. Droop amplitude (ADJ pin resistor).
b. No load offset (additional resistor in compensation
Current Loop Setting
a. GM amplifier S/H current (current sense component
Ron, ISPx & ISNx pin external resistor value, keep
ISPx current < 60μA at full load condition for better
load line linearity).
b. Over-current protection trip point (Internal setting,
keep ISPx current < 100μA at OCP condition for
precision issue).
Power Sequence & SS
DVD pin external resistor and SS pin capacitor.
DS9244-06 March 2007
network).
c. DAC offset voltage setting (VOSS pin & compensation network resistor).
PCB Layout
a. Kelvin sense for current sense GM amplifier input.
b. Refer to layout guide for other item.
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RT9244
Design Example
Asymptotic Bode Plot of PWM Loop Gain
100
Given:
80
Apply for three phase converter
60
VCORE = 1.5V
40
Gain (dB)
VIN = 12V
ILOAD (MAX) = 60A
VDROOP = 120mV at full load
OCP trip point set at 33A for each channel (S/H)
RDS(ON) = 6mΩ of low side MOSFET at 27°C
2
1
LC Filter Pole = 2π x LC = 1.2kHz and
1
ESR Zero = 2π x ESR x COUT = 8.8kHz
b. EA Compensation Network :
Select R1 = 2.4kΩ, R2 = 24kΩ, C1 = 6.6nF,
C2 = 33pF and use the type 2 compensation
scheme shown in Figure 5.
R3
C3
R1
COMP
> VDIF
FB
R3,C3 are used in type
3 compensation scheme
(left NC in type 2)
DACOUT
Modulator Gain
10
10
100
100
1K
1000
10K
10000
100K
100000
1M
10M
1000000
10000000
2. Droop & DAC Offset Setting
where VRAMP : ramp amplitude of sawtooth wave
+
PWM Loop Gain
Figure 6.
From the following formula :
V IN
12V
Modulator Gain =
=
= 4.2 (12.46dB)
V RAMP 1.9V × 3
-
Compensated EA Gain
-20
Frequency (Hz)
1. Compensation Setting
a. Modulator Gain, Pole and Zero :
C2
0
-60
COUT = 9,000μF with 2mΩ ESR.
C1
20
-40
L = 2μH
R2
Uncompensated EA Gain
Figure 5.
From the following formulas :
1
1
FZ =
, FP =
2π x R 2 x C 1
⎛ C1 × C 2 ⎞
2π x R 2 x ⎜
⎟
R2
⎝ C1 + C 2 ⎠
Middle Band Gain =
R1
By calculation, the FZ = 1kHz, FP = 200kHz and
Middle Band Gain is 10 (i.e 20dB).
The asymptotic bode plot of EA compensation and
For each channel the load current is 60A / 3 = 20A
and the ripple current, ΔIL, is given as :
5μ s x 1.5V x ⎛⎜ 1− 1.5V ⎞⎟ = 3.28A
2uH ⎝
12V ⎠
ΔIL
= 18.36 A .
The load current, IL, at S/H is 20 A −
2
Using the following formula to select the appropriate
IX (MAX) for the S/H of GM amplifier :
R DS(ON) × 18.36A
I X (MAX) =
R SP
The suggested IX is in the order of 50 to 60μA, select
RSP = RSN = 2kΩ, then IX (MAX) will be 55μA.
VDROOP = 120mV = 55μA × 2 × 3 (phase no.) × RADJ,
therefore RADJ will be 360Ω.
The RDS(ON) of MOSFET varies with temperature rise.
When the low side MOSFET working at 70°C and
5000ppm/°C temperature coefficient of RDS(ON), the
RDS(ON) at 70°C is given as :
6mΩ × {1+ (70°C − 27°C) × 5000ppm/°C} = 7.3mΩ.
RADJ at 70°C is given as :
RADJ_27°C × (RDS(ON)_27°C / RDS(ON)_70°C) = 296Ω
3. Over-Current Protection Setting
OCP trip point is internally set at around 100μA of IX
for each channel. As above-selected RSP = RSN = 2kΩ,
the OCP trip point is found using :
IX (OCP) =
RDS(ON) × IL (TRIP) 6mΩ × 33A
=
= 100μ A
RSP
2kΩ
4. Soft-Start Capacitor Selection
CSS = 0.1μF is the suitable value for most application.
PWM loop gain is shown as Figure 6.
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12
DS9244-06 March 2007
RT9244
Layout Guide
Place the high-power switching components first, and separate them from sensitive nodes.
1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense
resistors tied to ISP1,2,3,4 and ISN1,2,3,4 should be located not more than 0.5 inch from the IC and away
from the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible.
Kelvin connection of the sense component (additional sense resistor or MOSFET RDS(ON)) ensures the accurate
stable current sensing.
Keep well Kelvin sense to ensure the stable operation!
2. Switching ripple current path:
a. Input capacitor to high side MOSFET.
b. Low side MOSFET to output capacitor.
c. The return path of input and output capacitor.
d. Separate the power and signal GND.
e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points.
Keep them away from sensitive small-signal node.
f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via.
3. MOSFET driver should be closed to MOSFET.
4. The compensation, bypass and other function setting components should be near the IC and away from the noisy
power path.
SW1
L1
VOUT
VIN
RIN
COUT
CIN
RL
V
SW2
L2
Figure 7. Power Stage Ripple Current Path
DS9244-06 March 2007
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RT9244
Next to IC
+12V
+12V or +5V
CBP
VCC
PVCC
PWM
BOOT
+5VIN
VCC
CBP
RT
CBOOT
VOSS
UGATE
LO1
PHASE
RT9600
PWM
VCORE
CC
COUT
CIN
LGATE
Kelvin
Sense
GND
Next to IC
COMP
RT9244
RSIP
RSIN
Locate near MOSFETs
Locate next
to FB Pin
FB
ISPx
ISNx
ADJ
RC
RFB
VSEN
GND
For Thermal Couple
Figure 8. Layout Consideration
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DS9244-06 March 2007
RT9244
Outline Dimension
H
A
M
J
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
20.320
20.726
0.800
0.816
B
7.391
7.595
0.291
0.299
C
2.362
2.642
0.093
0.104
D
0.330
0.508
0.013
0.020
F
1.27
0.050
H
0.229
0.330
0.009
0.013
I
0.102
0.305
0.004
0.012
J
10.008
10.643
0.394
0.419
M
0.381
1.270
0.015
0.050
32-Lead SOP Plastic Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: [email protected]
DS9244-06 March 2007
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15