Revised March 2001 74ACTQ153 Quiet Series Dual 4-Input Multiplexer General Description Features The ACTQ153 is a high-speed dual 4-input multiplexer with common select inputs and individual enable inputs for each section. It can select two lines of data from four sources. The two buffered outputs present data in the true (noninverted) form. In addition to multiplexer operation, the ACTQ153 can act as a function generator and generate any two functions of three variables. ■ Outputs source/sink 24 mA ■ ACTQ153 has TTL-compatible inputs ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Improved latch-up immunity Ordering Code: Order Number Package Number Package Description 74ACTQ153SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74ACTQ153PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description I0a - 13a Side A Data Inputs I0b - 13b Side B Data Inputs S0, S1 Common Select Inputs Ea Side A Enable Input Eb Side B Enable Input Za Side A Output Zb Side B Output FACT, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation. © 2001 Fairchild Semiconductor Corporation DS010244 www.fairchildsemi.com 74ACTQ153 Quiet Series Dual 4-Input Multiplexer July 1990 74ACTQ153 Functional Description Truth Table The ACTQ153 is a dual 4-input multiplexer. It can select two bits of data from up to four sources under the control of the common Select inputs (S0, S1). The two 4-input multiplexer circuits have individual active-LOW Enables (Ea, Eb) which can be used to strobe the outputs independently. When the Enables (Ea, Eb) are HIGH, the corresponding outputs (Az, Zb) are forced LOW. The ACTQ153 is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the Select inputs. The logic equations for the outputs are shown below. Select Inputs Za = Ea • (I0a • S1 • S0 + I1a • S1 • S0 + I2a • S1 •S0 + I3a • S1 • S0) Zb = Eb • (I0b • S1 • S0 • I1b • S1 • S0 + I2b • S1 • S0 +I3b • S1 • S0) Inputs (a or b) Outputs S0 S1 E I0 I1 I2 I3 X X H X X X X L L L L L X X X L L L L H X X X H H L L X L X X L H L L X H X X H L H L X X L X L L H L X X H X H H H L X X X L L H H L X X X H H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Z Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA Supply Voltage (VCC) 0V to VCC −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate ∆V/∆t DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) 0V to VCC Output Voltage (VO) −0.5V to VCC + 0.5V DC Input Voltage (VI) 4.5V to 5.5V Input Voltage (VI) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −0.5V to VCC + 0.5V 125 mV/ns DC Output Source ±50 mA or Sink Current (IO) DC VCC or Ground Current Storage Temperature (TSTG) Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. ±50 mA per Output Pin (ICC or IGND ) −65°C to +150°C DC Latch-Up Source or Sink Current ±300 mA Junction Temperature (TJ) 140°C PDIP DC Electrical Characteristics Symbol VIH VIL VOH Parameter VCC TA = +25°C (V) Typ TA = −40°C to +85°C Guaranteed Limits Minimum HIGH Level 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Units V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 5.5 VOL 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 IOH = −24 mA (Note 2) V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IOL = 24 mA (Note 2) 5.5 0.36 0.44 IIN Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µA VI = VCC, GND ICCT Maximum ICC/Input 5.5 1.5 µA VI = VCC − 2.1V IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent Supply Current 5.5 80.0 µA VOLP Maximum HIGH Level Output Noise 0.6 8.0 5.0 1.1 1.5 V VIN = VCC or GND Figures 1, 2 (Note 4)(Note 5) VOLV Maximum LOW Level Output Noise 5.0 −0.6 −1.2 V Figures 1, 2 VIHD Minimum HIGH Level Dynamic Input Voltage 5.0 1.9 2.2 V (Note 4)(Note 6) VILD Maximum LOW Level Dynamic Input Voltage 5.0 1.2 0.8 V (Note 4)(Note 6) Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: Worst case package. Note 5: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One Data Input @ VIN = GND. Note 6: Max number of Data Inputs (n) switching. (n−1) inputs switching 0V to 5V. Input-under-test switching: 5V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. 3 www.fairchildsemi.com 74ACTQ153 Absolute Maximum Ratings(Note 1) 74ACTQ153 AC Electrical Characteristics Symbol tPLH Parameter Propagation Delay Sn to Zn tPHL Propagation Delay Sn to Zn tPLH Propagation Delay En to Zn tPHL Propagation Delay En to Zn tPLH Propagation Delay In to Zn tPHL Propagation Delay In to Zn VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max 5.0 3.0 7.0 11.5 2.0 13.5 ns 5.0 3.0 7.0 11.5 2.5 13.5 ns 5.0 2.0 6.5 10.5 2.0 12.5 ns 5.0 3.0 6.0 9.5 2.5 11.0 ns 5.0 2.5 5.5 9.5 2.0 11.0 ns 5.0 2.0 5.5 9.5 2.0 11.0 ns Note 7: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol Parameter Typ Units CIN Input Capacitance 4.5 pF VCC = 5.0V CPD Power Dissipation Capacitance 65.0 pF VCC = 5.0V www.fairchildsemi.com Units (Note 7) 4 Conditions The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. VOLP/VOLV and VOHP/VOHV: • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture • Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. VILD and VIHD: • Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. • First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. • Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. Note 8: VOHV and VOLP are measured with respect to ground reference. Note 9: Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps. FIGURE 1. Quiet Output Noise Voltage Waveforms FIGURE 2. Simultaneous Switching Test Circuit 5 www.fairchildsemi.com 74ACTQ153 FACT Noise Characteristics 74ACTQ153 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A www.fairchildsemi.com 6 74ACTQ153 Quiet Series Dual 4-Input Multiplexer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com