FAIRCHILD KM4212IC8

www.fairchildsemi.com
KM4212
Dual, 70µA, Low Cost, +2.7V & +5V, 7.3MHz Rail-to-Rail Amp
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General Description
70µA supply current
7.3MHz bandwidth
Fully specified at +2.7V and +5V supplies
Output voltage range: 0.04V to 4.96V; Vs = +5
Input voltage range: -0.3V to +3.8V; Vs = +5
9V/µs slew rate
±4mA linear output current
±9mA short circuit output current
29nV/√Hz input voltage noise
Competes with low power CMOS amps
Small package options (SOIC-8 and MSOP-8)
Applications
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Portable/battery-powered applications
A/D buffer
Active filters
Signal conditioning
Portable test instruments
KM4212 Packages
SOIC-8
Out1
1
-In1
2
+In1
3
-Vs
4
+
+
8
+Vs
7
Out2
6
-In2
5
+In2
The KM4212 is an ultra-low power, low cost, voltage
feedback amplifier. The KM4212 uses only 70µA of
supply current and is designed to operate on +2.7V,
+5V, or ±2.5V supplies. The input voltage range
extends 300mV below the negative rail and 1.2V
below the positive rail.
The KM4212 offers high bipolar performance at a low
CMOS price. The KM4212 offers superior dynamic
performance with a 7.3MHz small signal bandwidth
and 9V/µs slew rate. The combination of low power,
high bandwidth, and rail-to-rail performance make
the KM4212 well suited for battery-powered communication/computing systems.
The KM4112 single amplifier is also available.
Non-Inverting Freq. Response Vs = +5V
Normalized Magnitude (2dB/div)
Features
G=2
Rf = 10kΩ
0.01
MSOP-8
Out1
1
-In1
2
+In1
3
-Vs
4
+
+
0.1
1
10
Frequency (MHz)
8
+Vs
7
Out2
6
-In2
5
+In2
REV. 1 August 2001
DATA SHEET
KM4212
KM4212 Electrical Characteristics
PARAMETERS
(Vs = +2.7V, G = 2, RL = 10kΩ to Vs/2, Rf = 10kΩ; unless noted)
CONDITIONS
Case Temperature
Frequency Domain Response
-3dB bandwidth
TYP
MIN & MAX
+25°C
+25°C
UNITS
NOTES
1
G = +1, Vo = 0.05Vpp
G = +2, Vo < 0.2Vpp
G = -1, Vo = 2Vpp
6.5
3
2
3.5
MHz
MHz
MHz
MHz
Time Domain Response
rise and fall time
settling time to 0.1%
overshoot
slew rate
0.2V step
1V step
1V step,
2V step, G = -1
55
700
7
7
ns
ns
%
V/µs
Distortion and Noise Response
2nd harmonic distortion
3rd harmonic distortion
THD
input voltage noise
crosstalk
1Vpp, 100kHz
1Vpp, 100kHz
1Vpp, 100kHz
>10kHz
0.01MHz
68
65
63
30
89
dBc
dBc
dB
nV/√Hz
dB
full power bandwidth
gain bandwidth product
DC Performance
input offset voltage
average drift
input bias current
average drift
input offset current
power supply rejection ratio
open loop gain
quiescent current
Input Characteristics
input resistance
input capacitance
input common mode voltage range
common mode rejection ratio
Output Characteristics
output voltage swing
linear output current
short circuit output current
power supply operating range
DC
DC, Vcm = 0V to Vs - 1.5
RL = 10kΩ to Vs/2
RL = 2kΩ to Vs/2
1
3
90
100
2.1
63
82
62
>10
1.4
-0.3 to 1.5
95
±5
100
58
65
95
mV
µV/°C
nA
pA/°C
nA
dB
dB
µA
2
2
2
2
68
MΩ
pF
V
dB
2
250
0.035 to 2.665 0.15 to 2.55
0.07 to 2.6
±4
±9
2.7
2.5 to 5.5
V
V
mA
mA
V
2
2
2
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels
are determined from tested parameters.
NOTES:
1) For G = +1, Rf = 0.
2) 100% tested at +25°C.
Absolute Maximum Ratings
supply voltage
0 to +6V
maximum junction temperature
+175°C
storage temperature range
-65°C to +150°C
lead temperature (10 sec)
+260°C
operating temperature range (recommended) -40°C to +85°C
input voltage range
+Vs +0.5V; -Vs -0.5V
internal power dissipation
see power derating curves
2
Package Thermal Resistance
Package
θJA
8 lead SOIC
8 lead MSOP
152°C/W
206°C/W
REV. 1 August 2001
KM4212
DATA SHEET
KM4212 Electrical Characteristics
PARAMETERS
(Vs = +5V, G = 2, RL = 10kΩ to Vs/2, Rf = 10kΩ; unless noted)
CONDITIONS
Case Temperature
Frequency Domain Response
-3dB bandwidth
TYP
MIN & MAX
+25°C
+25°C
UNITS
NOTES
1
G = +1, Vo = 0.05Vpp
G = +2, Vo < 0.2Vpp
G = -1, Vo = 2Vpp
7.3
3.4
2.5
4
MHz
MHz
MHz
MHz
Time Domain Response
rise and fall time
settling time to 0.1%
overshoot
slew rate
0.2V step
2V step
2V step,
2V step, G = -1
50
600
4
9
ns
ns
%
V/µs
Distortion and Noise Response
2nd harmonic distortion
3rd harmonic distortion
THD
input voltage noise
crosstalk
2Vpp, 100kHz
2Vpp, 100kHz
2Vpp, 100kHz
>10kHz
0.01MHz
67
60
59
29
89
dBc
dBc
dB
nV/√Hz
dB
1
8
90
100
1.3
63
76
70
mV
µV/°C
nA
pA/°C
nA
dB
dB
µA
>10
1.25
-0.3 to 3.8
97
MΩ
pF
V
dB
0.04 to 4.96
0.09 to 4.9
±4
±9
5
V
V
mA
mA
V
full power bandwidth
gain bandwidth product
DC Performance
input offset voltage
average drift
input bias current
average drift
input offset current
power supply rejection ratio
open loop gain
quiescent current
Input Characteristics
input resistance
input capacitance
input common mode voltage range
common mode rejection ratio
Output Characteristics
output voltage swing
linear output current
short circuit output current
power supply operating range
DC
DC, Vcm = 0V to Vs - 1.5
RL = 10kΩ to Vs/2
RL = 2kΩ to Vs/2
2.5 to 5.5
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels
are determined from tested parameters.
NOTES:
1) For G = +1, Rf = 0.
REV. 1 August 2001
3
DATA SHEET
KM4212
KM4212 Performance Characteristics
(Vs = +5V, G = 2, RL = 10kΩ to Vs/2, Rf = 10kΩ; unless noted)
Inverting Frequency Response Vs = +5V
Normalized Magnitude (1dB/div)
Normalized Magnitude (2dB/div)
Non-Inverting Frequency Response Vs = +5V
G=1
G=2
G = 10
G=5
0.01
0.1
1
G = -2
G = -10
G = -5
G = -1
0.01
10
0.1
1
10
Non-Inverting Freq. Response Vs = +2.7V
Inverting Frequency Response Vs = +2.7V
Normalized Magnitude (1dB/div)
Frequency (MHz)
Normalized Magnitude (2dB/div)
Frequency (MHz)
G=1
G=2
G = 10
G=5
0.01
0.1
1
G = -1
G = -2
G = -10
G = -5
0.01
10
0.1
Frequency (MHz)
1
10
Frequency (MHz)
Large Signal Frequency Response
Open Loop Gain & Phase vs. Frequency
0
80
|Gain|
Open Loop Gain (dB)
70
Vo = 2Vpp
-20
60
-40
50
-60
40
-80
30
-100
20
-120
10
-140
-160
0
Open Loop Phase (deg)
Magnitude (1dB/div)
Vo = 1Vpp
Phase
-180
-10
0.01
0.1
1
1
10
10
Frequency (MHz)
100
1k
10k
100k
1M
Frequency (Hz)
Input Voltage Noise
2nd & 3rd Harmonic Distortion; Vs = +5V
140
-20
120
-30
100
-40
Distortion (dBc)
Voltage Noise (nV/√Hz)
Vo = 2Vpp
80
60
40
20
0
0.0001
-50
-60
-70
2nd
-80
-90
0.001
0.01
0.1
Frequency (MHz)
4
3rd
1.0
10
10
100
1000
Frequency (kHz)
REV. 1 August 2001
KM4212
DATA SHEET
KM4212 Performance Characteristics
(Vs = +5V, G = 2, RL = 10kΩ to Vs/2, Rf = 10kΩ; unless noted)
2nd & 3rd Harmonic Distortion; Vs = +2.7V
PSRR
0
-20
Vo = 1Vpp
-10
-20
-40
3rd
PSRR (dB)
Distortion (dBc)
-30
-50
-60
2nd
-30
-40
-50
-70
-60
-80
-70
-90
-80
10
100
1
1000
Frequency (kHz)
10
100
1k
10k
100k
1M
Frequency (Hz)
Output Swing vs. RL
CMRR
4.95
0
-10
4.90
Output Swing (Vpp)
CMRR (dB)
-20
-30
4.85
-40
-50
4.80
-60
-70
4.75
-80
-90
4.70
-100
1
10
100
1k
10k
100k
1
1M
10
100
RL (kΩ)
Frequency (Hz)
Large Signal Pulse Response Vs = +5V
Crosstalk vs. Frequency
Output Voltage (0.5V/div)
-60
-65
Crosstalk (dB)
SOIC
-70
-75
-80
-85
MSOP
-90
-95
Time (1µs/div)
0.01
0.1
1.0
10
Frequency (MHz)
REV. 1 August 2001
5
KM4212
General Description
The KM4212 is a single supply, general purpose, voltagefeedback amplifier fabricated on a complementary
bipolar process. The KM4212 offers 7.3MHz unity gain
bandwidth, 9V/µs slew rate, and only 70µA supply
current. It features a rail-to-rail output stage and is
unity gain stable.
The design utilizes a patent pending topology that
provides increased slew rate performance. The common
mode input range extends to 300mV below ground
and to 1.2V below Vs. Exceeding these values will not
cause phase reversal. However, if the input voltage
exceeds the rails by more than 0.5V, the input ESD
devices will begin to conduct. The output will stay at
the rail during this overdrive condition.
The design uses a Darlington output stage. The output stage is short circuit protected and offers “soft”
saturation protection that improves recovery time.
The typical circuit schematic is shown in Figure 1.
Maximum Power Dissipation (W)
DATA SHEET
2.0
1.5
SOIC-8 lead
1.0
MSOP-8 lead
0.5
0
-50
-30
-10
10
30
50
70
90
Ambient Temperature ( C)
Figure 2: Power Derating Curves
Overdrive Recovery
For an amplifier, an overdrive condition occurs when
the output and/or input ranges are exceeded. The
recovery time varies based on whether the input or
output is overdriven and by how much the ranges are
exceeded. The KM4212 will typically recover in less
than 60ns from an overdrive condition. Figure 3
shows the KM4212 in an overdriven condition.
+Vs
6.8µF
+
0.01µF
Out1
1/2
KM4212
-
Rf
Input
Input Voltage (0.2V/div)
+In1
Output Voltage (1V/div)
G=5
+
Output
Time (2µs/div)
Rg
Figure 3: Overdrive Recovery
Figure 1: Typical Configuration
Power Dissipation
The maximum internal power dissipation allowed is
directly related to the maximum junction temperature.
If the maximum junction temperature exceeds 150°C,
some reliability degradation will occur. If the maximum
junction temperature exceeds 175°C for an extended
time, device failure may occur.
Driving Capacitive Loads
A small series resistance (Rs) at the output of the
amplifier, illustrated in Figure 4, will improve stability
and settling performance.
+
Rs
Rf
The KM4212 is short circuit protected. However, this
may not guarantee that the maximum junction
temperature (+150°C) is not exceeded under all
conditions. Follow the maximum power derating
curves shown in Figure 2 to ensure proper operation.
6
CL
RL
Rg
Figure 4: Typical Topology for driving
a capacitive load
REV. 1 August 2001
KM4212
Layout Considerations
General layout and supply bypassing play major roles
in high frequency performance. Fairchild has evaluation
boards to use as a guide for high frequency layout
and to aid in device testing and characterization.
Follow the steps below as a basis for high frequency
layout:
Include 6.8µF and 0.01µF ceramic capacitors
■ Place the 6.8µF capacitor within 0.75 inches
of the power pin
■ Place the 0.01µF capacitor within 0.1 inches
of the power pin
■ Remove the ground plane under and around the
part, especially near the input and output pins to
reduce parasitic capacitance
■ Minimize all trace lengths to reduce
series inductances
■
DATA SHEET
Evaluation Board Information
The following evaluation boards are available to aid
in the testing and layout of this device:
Eval Board
Description
Products
KEB006
Dual Channel,
Dual Supply 8 lead SOIC
KM4212IC8
KEB010
Dual Channel,
Dual Supply 8 lead MSOP
KM4212IM8
Evaluation board schematics and layouts are shown in
Figure 5 and Figure 6.
The KEB002 evaluation board is built for dual supply
operation. Follow these steps to use the board in a
single supply application:
1. Short -Vs to ground
2. Use C3 and C4, if the -Vs pin of the KM4212 is not
directly connected to the ground plane.
Refer to the evaluation board layouts shown in Figure
6 for more information.
When evaluating only one channel, complete the
following on the unused channel
1. Ground the non-inverting input
2. Short the output to the inverting input
Figure 5: Evaluation Board Schematic
REV. 1 August 2001
7
DATA SHEET
KM4212
KM4212 Evaluation Board Layout
8
Figure 6a: KEB006 (top side)
Figure 6b: KEB006 (bottom side)
Figure 6c: KEB010 (top side)
Figure 6d: KEB010 (bottom side)
REV. 1 August 2001
KM4212
DATA SHEET
KM4212 Package Dimensions
SOIC-8
D
SYMBOL
A1
B
C
D
E
e
H
h
L
A
7¡
e
ZD
CL
SOIC
CL
Pin No. 1
E
H
B
ZD
A2
DETAIL-A
L
NOTE:
h x 45¡
A
A1
DETAIL-A
1. All dimensions are in millimeters.
2. Lead coplanarity should be 0 to 0.10mm (.004") max.
3. Package surface finishing:
(2.1) Top: matte (charmilles #18~30).
(2.2) All sides: matte (charmilles #18~30).
(2.3) Bottom: smooth or matte (charmilles #18~30).
4. All dimensions excluding mold flashes and end flash
from the package body shall not exceed o.152mm (.006)
per side(d).
α
A2
C
e
02
S
MSOP-8
t1
MSOP
R1
t2
E/2 2X
–H–
3
7
–B–
2
E1
R
Gauge
Plane
0.25mm
L1
b
ccc A B C
2
01
L
03
E3
E4
1
c
Detail A
Scale 40:1
c1
2
4
6
–C–
D2
A2
A1
Section A - A
A
Detail A
E1
E
D
3
E2
A
–A–
b
bbb M A B C
b1
5
A
aaa A
4
NOTE:
1 All dimensions are in millimeters (angle in degrees), unless otherwise specified.
REV. 1 August 2001
MIN
MAX
0.10
0.25
0.36
0.46
0.19
0.25
4.80
4.98
3.81
3.99
1.27 BSC
5.80
6.20
0.25
0.50
0.41
1.27
1.52
1.72
8
0
0.53 ref
1.37
1.57
2
Datums – B – and – C – to be determined at datum plane – H – .
3
Dimensions "D" and "E1" are to be determined at datum – H – .
4
Dimensions "D2" and "E2" are for top package and dimensions "D" and "E1" are for bottom package.
5
Cross sections A – A to be determined at 0.13 to 0.25mm from the leadtip.
6
Dimension "D" and "D2" does not include mold flash, protrusion or gate burrs.
7
Dimension "E1" and "E2" does not include interlead flash or protrusion.
SYMBOL
MIN
A
1.10
A1
0.10
A2
0.86
D
3.00
D2
2.95
E
4.90
E1
3.00
E2
2.95
E3
0.51
E4
0.51
R
0.15
R1
0.15
t1
0.31
t2
0.41
b
0.33
b1
0.30
c
0.18
c1
0.15
01
3.0°
02
12.0°
03
12.0°
L
0.55
L1
0.95 BSC
aaa
0.10
bbb
0.08
ccc
0.25
e
0.65 BSC
S
0.525 BSC
MAX
–
±0.05
±0.08
±0.10
±0.10
±0.15
±0.10
±0.10
±0.13
±0.13
+0.15/-0.06
+0.15/-0.06
±0.08
±0.08
+0.07/-0.08
±0.05
±0.05
+0.03/-0.02
±3.0°
±3.0°
±3.0°
±0.15
–
–
–
–
–
–
9
KM4212
DATA SHEET
Ordering Information
Model
Part Number
Package
Container
Pack Qty
KM4212
KM4212IC8
SOIC-8
Rail
95
KM4212
KM4212IC8TR3
SOIC-8
Reel
2500
KM4212
KM4212IM8
MSOP-8
Rail
50
KM4212
KM4212IM8TR3
MSOP-8
Reel
4000
Temperature range for all parts: -40°C to +85°C
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICES TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT
OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1.
Life support devices or systems are devices or systems which, (a) are intended for
surgical implant into the body, or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant injury of the user.
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2.
A critical component in any component of a life support device or system whose
failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
© 2001 Fairchild Semiconductor Corporation