PHILIPS SAA5284GP

INTEGRATED CIRCUITS
DATA SHEET
SAA5284
Multimedia video data acquisition
circuit
Objective specification
Supersedes data of 1997 Mar 03
File under Integrated Circuits, IC22
1998 Feb 05
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
CONTENTS
1
FEATURES
2
GENERAL DESCRIPTION
3
QUICK REFERENCE DATA
4
ORDERING INFORMATION
5
MAIN FUNCTIONAL BLOCKS
6
BLOCK DIAGRAM
7
PINNING INFORMATION
7.1
7.2
Pinning
Pin description
8
FUNCTIONAL DESCRIPTION
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
Power supply strategy
Clocking strategy
Power-on reset
Analog switch
Analog video-to-data byte converter
Packet filtering
Packet buffer
FIFO
Host interface
Interrupt support
DMA support
I2C-bus interface
9
LIMITING VALUES
10
QUALITY & RELIABILITY
11
CHARACTERISTICS
12
TIMING
13
APPLICATION INFORMATION
13.1
13.2
13.3
Hardware application circuit for ISA card
Hardware application circuit for PCI application
Software application information
14
PACKAGE OUTLINE
15
SOLDERING
15.1
15.2
15.3
15.4
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
16
DEFINITIONS
17
LIFE SUPPORT APPLICATIONS
18
PURCHASE OF PHILIPS I2C COMPONENTS
1998 Feb 05
2
SAA5284
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
1
SAA5284
FEATURES
• High performance multi-standard data slicer
• Intercast (Intel Corporation) compatible
• Teletext (WST, Chinese teletext) (625 lines)
• Teletext (US teletext, NABTS and MOJI) (525 lines)
• Wide Screen Signalling (WSS), Video Programming
Signal (VPS)
• Single IC with few external components and small
footprint QFP44 package
• Closed Caption (Europe, US)
• Optimized for EMC.
• Data broadcast, PDC (packet 30 and 31)
• User programmable data format (programmable framing
code)
2
The SAA5284 is a Vertical Blanking Interval (VBI) and Full
Field (FF) video data acquisition device tailored for
application on PC add-in cards, PC mother-boards, set-top
boxes and as a SAA5250 replacement. The IC in
combination with a range of software modules will acquire
most existing formats of broadcast VBI and FF data.
• 2 kbytes data cache on-chip to avoid data loss and
reduce host CPU overhead
• Filtering of packets 30 and 31 WST/NABTS
• Choice of clock frequencies, direct-in clock or crystal
oscillator
These associated software modules are available under
licence. Scope is provided for acquiring some as yet
unspecified formats. The SAA5284 incorporates all the
data slicing, parallel interface, data filtering and control
logic. It is controlled either by a parallel interface or
I2C-bus. It can output ASCII VBI data as pixels on the
digital video bus where no parallel port is available. It is
available in a QFP44 package.
• Parallel interface, Motorola, Intel and digital video bus
• I2C-bus control
• Data transport by digital video bus
• Choice of programmable interrupt, DMA or polling
driven
• Data type selectable video line by video line, with
Vertical Blanking Interval and Full Field mode
3
GENERAL DESCRIPTION
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX. UNIT
VDD
supply voltage
4.5
5.0
5.5
V
IDD
supply current
−
72
95
mA
Vsync(p-p)
sync voltage (peak-to-peak value)
0.1
0.3
0.6
V
Vi(CVBS)(p-p)
input voltage on pin CVBS0 and CVBS1
(peak-to-peak value)
0.7
1.0
1.4
V
fxtal
crystal frequency; see note 1
−
12.0
−
MHz
Tamb
operating ambient temperature
−20
−
+70
°C
Note
1. Selectable: 12, 13.5, 15 or 16 MHz.
4
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA5284GP
1998 Feb 05
QFP44
DESCRIPTION
plastic quad flat package; 44 leads (lead length 2.35 mm);
body 14 × 14 × 2.2 mm
3
VERSION
SOT205-1
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
5
SAA5284
7. 12, 13.5, 15 and 16 MHz clock or oscillator options
MAIN FUNCTIONAL BLOCKS
1. Input clamp and sync separator
8. FIFO access to data
2. Analog-to-digital converter
9. Interrupt and DMA support
3. Multi-standard data slicer and clock regenerator
10. Multi-standard parallel interface
4. Packet filtering; (8 and 4) Hamming correction
11. I2C-bus interface
5. On-chip data cache
12. Power-on reset.
6. Line selectable data type
Figure 1 shows a block diagram of the SAA5284.
6
BLOCK DIAGRAM
handbook, full pagewidth
VDDA VSSA VDDX VDDD VSSD3
17
16
6
41
40
RESET
VPOIN0
HREF
VPOIN1
38
1
39
2
RD(1)
LLC
WR(1)
LLC2
43
42
33
DMACK(1)
DMARQ
34
36
37
35
CS0
44
SAA5284
CS1
31
INT
32
CVBS0
CVBS1
MULTI-STANDARD
HOST INTERFACE
15
ANALOG
SWITCH
14
PACKET BUFFER AND
FRONT END CONTROL
REGISTERS
RDY(1)
10
SEL0
11
SEL1
5
30 to 28
3
20 to 27 8
IREF
BLACK
13
12
ANALOG
VIDEO TO
DATA BYTE
CONVERTER
(DATA
DEMODULATOR)
8
FIFO
9
OSCOUT
OSCGND
OSCIN
18
19
4
D7 to D0(1)
SDA
SCL
VSSD1
VSSD2
MGG740
(1) Multi-functional pins, see Chapter 7.
Fig.1 Block diagram.
1998 Feb 05
3
I2C-BUS
INTERFACE
400 kHz
SLAVE
A2 to A0(1)
PACKET BUFFER RAM
2 kbyte
(45 packets)
OSCILLATOR
AND TIMING
7
PACKET
FILTERING (e.g.
WST packets
30/31)
DENB
4
data path
control
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
34 RD(1)
35 CS0
36 DMARQ
37 DMACK(1)
39 VPOIN1
40 VSSD3
41 VDDD
42 LLC
43 LLC2
44 CS1
handbook, full pagewidth
38 VPOIN0
Pinning
RESET 1
33 WR(1)
HREF 2
32 RDY(1)
SDA 3
31 INT
SCL 4
30 A2(1)
DENB 5
29 A1(1)
VDDX 6
28 A0(1)
SAA5284
23 D4(1)
D5(1) 22
SEL1 11
D6(1) 21
24 D3(1)
D7(1) 20
SEL0 10
VSSD2 19
25 D2(1)
VDDA 16
OSCGND 9
CVBS0 15
26 D1(1)
CVBS1 14
OSCIN 8
IREF 13
27 D0(1)
BLACK 12
OSCOUT 7
VSSA 17
7.1
PINNING INFORMATION
VSSD1 18
7
SAA5284
MGG739
(1) Multi-functional pin.
Fig.2 Pin configuration.
7.2
Pin description
Table 1 QFP44 package
The IC has a total of 44 pins; many of these are multi-functional due to the multiple host block modes of operation.
SYMBOL
PIN
I/O
RESET
HREF
1
2
I
I
SDA
SCL
DENB
VDDX
OSCOUT
3
4
5
6
7
I/O
I
O
−
O
OSCIN
8
I
1998 Feb 05
DESCRIPTION
reset IC
video horizontal reference signal (digital video mode only)
serial data port for I2C-bus, open-drain
serial clock input for I2C-bus
data enable bar (for external buffers)
+5 V supply
oscillator output
oscillator input
5
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SYMBOL
SAA5284
PIN
I/O
OSCGND
SEL0
9
10
−
I
SEL1
BLACK
IREF
11
12
I
I/O
13
14
I
I
reference current input; connected to VSSA via 27 kΩ resistor
analog composite video input 1
CVBS0
VDDA
VSSA
VSSD1
15
16
17
I
−
−
analog composite video input 0
analog +5 V supply
analog ground supply
18
I
digital ground supply 1
VSSD2
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
O
O
I
digital ground supply 2
data bus 7/video data output 7
data bus 6/video data output 6
data bus 5/video data output 5
data bus 4/video data output 4
data bus 3/video data output 3
data bus 2/video data output 2
data bus 1/video data output 1
data bus 0/video data output 0
address input 0/video data input 7
address input 1/video data input 6
address input 2/video data input 5
interrupt request
ready/DTACK (data acknowledge)/VBI, open-drain
Intel bus Write/Motorola bus R/W/video data input 4
34
35
I
I
Intel bus Read/Motorola bus LDS/video data input 3
chip select 0; active LOW
36
O
DMA request
VPOIN0
VPOIN1
VSSD3
VDDD
LLC
LLC2
37
38
39
40
41
42
43
I
I
I
−
−
I
I
DMA acknowledge/video data input 2
video data input 0
video data input 1
digital ground supply 3
digital +5 V supply
full rate digital video clock input
half rate digital video clock input
CS1
44
I
chip select 1; active LOW
CVBS1
D7(1)
D6(1)
D5(1)
D4(1)
D3(1)
D2(1)
D1(1)
D0(1)
A0(1)
A1(1)
A2(1)
INT
RDY(1)
WR(1)
RD(1)
CS0
DMARQ
DMACK(1)
DESCRIPTION
oscillator ground
parallel interface format select 0
parallel interface format select 1
video black level storage; connected to VSSA via 100 nF capacitor
Note
1. These pins have two functions, depending on the interface mode.
1998 Feb 05
6
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
8
The analog video-to-data byte converter is specifically
designed to overcome the most commonly found types of
distortion of a broadcast video signal. It is also fully
multi-standard. The data type to be demodulated is
programmable on a line-by-line basis using 4 register bits
per line for lines 2 to 23 (PAL numbering),
fields 1 and 2, and 4 further bits for all lines combined.
FUNCTIONAL DESCRIPTION
8.1
Power supply strategy
There are three separate +5 V (VDD) connections to the IC:
1. VDDA supplies the critical noise-sensitive analog
front-end sections: ADC and sync separator, to reduce
interference from the rest of the front-end
2. VDDX supplies all sections which take standing DC
current
8.6
Packet filtering
If using a slow (e.g. 80C51) microcontroller, it is necessary
to reduce the amount of data acquired by SAA5284 before
downloading to the microcontroller to avoid it being
swamped by unwanted data. Packet filtering is available
for this purpose. A common use of this would be to acquire
only packet 8/30 in 625-line WST. The packet filter
includes optional (8, 4) Hamming correction.
3. VDDD supplies the rest of the logic.
8.2
SAA5284
Clocking strategy
The master frequency reference for the IC is a
12, 13.5, 15 or 16 MHz crystal oscillator. The tolerance on
the clock frequency is 500 × 10−6 (1.5 kHz). Further
specifications of the crystal are given in Table 2.
8.7
If preferred, an external 12, 13.5, 15 or 16 MHz (±1.5 kHz)
frequency source may be connected to OSCIN instead of
the crystal.
Packet buffer
Direct addressed registers (i.e. those addressed using the
A0 to A2 pins) are set to 00H after power-up. All other
register bits are assumed to be in random states after
power-up.
This is a 2 kbyte RAM which acts as a buffer for storing
received packets. The first 44 bytes are reserved for
control information. The rest of the RAM is divided into
44-byte rows (or packets), each holding the data received
on one incoming CVBS line. In the case of a WST packet
received, the data stored consists of a Magazine and
Row-Address Group (2 bytes), followed by the 40 bytes of
packet data. When data in other formats than WST is
received, this is stored in the packet buffer in the same
way. In each case, the data is preceded by two information
bytes which record on which line and field the packet was
received, and what the data type is.
8.4
8.8
8.3
Power-on reset
The RESET pin should be held HIGH for a minimum of two
clock cycles. The reset signal is passed through a Schmitt
trigger internally.
Analog switch
Register bit selection between two video sources.
8.5
FIFO hardware is provided to manage the ‘read’ address
for the host processor, i.e. data is read repeatedly from the
same 8-bit port, and appears byte-serially in the order of
reception. The read address can be reset to the start of the
packet buffer (the first 44-byte packet), back to the start of
the current packet, or incremented to the start of the next
packet.
Analog video-to-data byte converter
This section comprises a line and field sync separator, a
video clamp, an ADC and a custom adaptive digital filter
with DPLL based timing circuit.
Table 2
FIFO
Crystal characteristics
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
C1
series capacitance
−
18.5
−
fF
C2
parallel capacitance
−
4.9
−
pF
Rr
resonant resistance
−
−
50
Ω
Xa
ageing
−
−
5 × 10−6
Xj
Xd
1998 Feb 05
−
adjustment tolerance
−
drift
7
−
−
per year
25 ×
10−6
−
25 ×
10−6
−
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
8.9
Host interface
8.10
The SAA5284 has a multi-standard 8-bit I/O interface.
To reduce the amount of host I/O space used, the parallel
interface has only 3 address inputs (A0, A1 and A2).
An extended addressing (pointer) scheme and the data
FIFO are used to allow access to the full set of SAA5284
registers and the full span of the packet buffer.
SAA5284
Interrupt support
The host interface provides comprehensive support for
interrupt generation. The interrupt may be programmed to
occur when a particular number of packets of VBI data are
available in the cache RAM. The interrupts can be further
controlled to occur on a specific line in the TV frame.
The interrupts can also be self masking if required.
As well as the 8 data I/O lines and 3 address lines, there
are the following control signals: RD (read LOW), WR
(write LOW), CS0 (chip select LOW), CS1(second chip
select LOW), INT (interrupt request), DMARQ (DMA
request), DMACK (DMA acknowledge) and RDY (ready).
8.11
DMA support
Burst and demand mode DMA are supported. In burst
mode, the number of packets to transfer can be defined.
An interrupt can be generated when DMA is finished. This
can be self masking.
In order to maintain compatibility with Motorola and Intel
type buses, two control signals SEL0 and SEL1 are
provided to configure the host interface. These signals
allow configuration of the host interface to work with the
Motorola or Intel style interfaces.
8.12
I2C-bus interface
The I2C-bus interface functions as a slave receiver or
transmitter at up to 400 kHz. The I2C-bus address is
selectable as 20H or 22H. All functionality is available
using the I2C-bus although with a slower data transfer
speed. It is possible to use the I2C-bus in all modes.
The host interface has a digital video mode. Digital video
mode may be used to allow the SAA5284 to pass decoded
VBI data into a system using the digital video bus.
9 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage (all supplies)
−0.3
+6.5
V
VI(max)
input voltage (any input)
−0.3
VDD + 0.5
V
VO(max)
output voltage (any output)
−0.3
VDD + 0.5
V
∆VDDD−DDA−DDX supply voltage difference between VDDD, VDDA and VDDX
−
0.25
V
IIOK
DC input or output diode current
−
20
mA
IO(max)
output current (any output)
−
10
mA
Tstg
storage temperature
−55
+125
°C
Tamb
operating ambient temperature
−20
+70
°C
10 QUALITY & RELIABILITY
In accordance with “SNW-FQ-611-E”.
1998 Feb 05
8
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
11 CHARACTERISTICS
Tamb = −20 to +70 °C; VDD = 4.5 to 5.5 V; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Power supply
VDDn
supply voltage
4.5
5.0
5.5
V
IDD(tot)
total supply current
−
72
95
mA
IDDD
digital supply current
−
32
42
mA
IDDA
analog supply current
−
40
53
mA
Inputs CVBS0 and CVBS1
Vsync(p-p)
sync voltage
(peak-to-peak value)
0.1
0.3
0.6
V
Vburst(p-p)
colour burst voltage
(peak-to-peak value)
0
0.3
0.4
V
Vi(vid)(p-p)
video input voltage
(peak-to-peak value)
0.7
1.0
1.4
V
Vi(data)(p-p) teletext data input voltage
(peak-to-peak value)
0.29
0.46
0.71
V
Zsource
source impedance
−
−
250
Ω
Vi(sw)
input switching level of sync
separator
1.5
1.8
2.1
V
Zi
input impedance
2.5
5.0
−
kΩ
Ci
input capacitance
−
−
10
pF
external resistor to VSSA
−
27
−
kΩ
Input IREF
RIREF
Inputs RESET, HREF, SEL0, SEL1, A0, A1, A2, WR, RD, CS0, CS1, DMACK, VPOIN1, VPOIN0, LLC and LLC2
VIL
LOW-level input voltage
−0.3
−
+0.8
VIH
HIGH-level input voltage
2.0
−
VDD + 0.5 V
ILI
input leakage current
−10
−
+10
µA
Ci
input capacitance
−
−
10
pF
VIL
LOW-level input voltage
−0.5
−
+1.5
V
VIH
HIGH-level input voltage
3.0
−
VDD + 0.5 V
ILI
input leakage current
Vi = 0 to VDD
−10
−
+10
Ci
input capacitance
−
10
pF
ti(r)
input rise time
VIL(min) to VIH(max); fi(SCL) = 100 kHz
50
−
1000
ns
VIL(min) to VIH(max); fi(SCL) = 400 kHz
50
−
300
ns
VIL(max) to VIH(min); fi(SCL) = 100 kHz
50
−
300
ns
VIL(max) to VIH(min); fi(SCL) = 400 kHz
Vi = 0 to VDD
V
Input SCL
µA
ti(f)
input fall time
50
−
300
ns
fi(SCL)
input clock frequency
0
−
400
kHz
CL
load capacitance
−
−
400
pF
1998 Feb 05
9
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SYMBOL
PARAMETER
SAA5284
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input/output SDA (open-drain)
VIL
LOW-level input voltage
−0.5
−
+1.5
VIH
HIGH-level input voltage
3.0
−
VDD + 0.5 V
ILI
input leakage current
VI = 0 to VDD
−10
−
+10
Ci
input capacitance
−
10
pF
ti(r)
input rise time
VIL(min) to VIH(max); fi(SCL) = 100 kHz
50
−
1000
ns
VIL(min) to VIH(max); fi(SCL) = 400 kHz
50
−
300
ns
ti(f)
VOL
input fall time
LOW-level output voltage
to(f)
output fall time
CL
load capacitance
V
µA
VIL(max) to VIH(min); fi(SCL) = 100 kHz 50
−
300
ns
VIL(max) to VIH(min); fi(SCL) = 400 kHz
50
−
300
ns
IOL = 3 mA
0
−
0.4
V
IOL = 6 mA
0
−
0.6
V
between 3 and 1.5 V; IOL = 3 mA
50
−
250
ns
−
−
400
pF
−
100
−
nF
−0.3
−
+0.8
V
Input/output BLACK
CBLACK
storage capacitance to VSSA
Inputs/outputs D7 to D0
VIL
LOW-level input voltage
2.0
−
VDD + 0.5 V
−10
−
+10
µA
−
−
10
pF
VIH
HIGH-level input voltage
ILI
input leakage current
Ci
input capacitance
VOL
LOW-level output voltage
IOL = +1.6 mA
0
−
0.4
V
VOH
HIGH-level output voltage
IOH = −0.2 mA
2.4
−
VDD
V
CL
load capacitance
−
−
tbf
pF
to(r)
output rise time into CL
0.6 to 2.2 V
−
−
tbf
ns
to(f)
output fall time into CL
2.2 to 0.6 V
−
−
tbf
ns
VIN = 0 to VDD
Outputs INT, DENB and DMARQ
VOL
LOW-level output voltage
IOL = +1.6 mA
0
−
0.4
V
VOH
HIGH-level output voltage
IOH = −0.2 mA
2.4
−
VDD
V
CL
load capacitance
−
−
tbf
pF
to(r)
output rise time into CL
0.6 to 2.2 V
−
−
tbf
ns
to(f)
output fall time into CL
2.2 to 0.6 V
−
−
tbf
ns
RDY (open-drain); note 1
VOL
LOW-level output voltage
CL
load capacitance
to(r)
output rise time into CL
to(f)
output fall time into CL
1998 Feb 05
0
−
0.4
V
−
−
tbf
pF
0.6 to 2.2 V
−
−
tbf
ns
2.2 to 0.6 V
−
−
tbf
ns
IOL = +1.6 mA
10
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SYMBOL
PARAMETER
SAA5284
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I2C-bus timings (see note 2 and Fig.8)
fi(SCL)
SCL input clock frequency
tLOW
SCL LOW time
tHIGH
SCL HIGH time
tSU;DAT
data set-up time
tHD;DAT
data hold time
tSU;STO
set-up time STOP condition
tBUF
bus free time
fi(SCL) = 100 kHz
0
−
100
kHz
fi(SCL) = 400 kHz
0
−
400
kHz
fi(SCL) = 100 kHz
4.7
−
−
µs
fi(SCL) = 400 kHz
1.3
−
−
µs
fi(SCL) = 100 kHz
4.0
−
−
µs
fi(SCL) = 400 kHz
0.6
−
−
µs
fi(SCL) = 100 kHz
250
−
−
ns
fi(SCL) = 400 kHz
100
−
−
ns
fi(SCL) = 100 kHz
0
−
−
µs
fi(SCL) = 400 kHz
0
−
−
µs
fi(SCL) = 100 kHz
4.7
−
−
µs
fi(SCL) = 400 kHz
0.6
−
−
µs
fi(SCL) = 100 kHz
4.7
−
−
µs
fi(SCL) = 400 kHz
1.3
−
−
µs
fi(SCL) = 100 kHz
4.0
−
−
µs
fi(SCL) = 400 kHz
0.6
−
−
µs
tSU;STA
set-up time repeated START fi(SCL) = 100 kHz
4.7
−
−
µs
fi(SCL) = 400 kHz
0.6
−
−
µs
tr
rise time (SDA and SCL)
fi(SCL) = 100 kHz
−
−
1000
ns
fi(SCL) = 400 kHz
−
−
300
ns
fi(SCL) = 100 kHz
−
−
300
ns
fi(SCL) = 400 kHz
−
−
300
ns
tHD;STA
tf
hold time START condition
fall time (SDA and SCL)
Notes
1. ESD protection of this pin falls below the Philips General Quality Specification (GQS). Therefore it is recommended
that a diode is connected from pin RDY to VDDD.
2. The I2C-bus interface pins SDA and SCL may pull the data and clock lines below 3 V while the digital power supply
VDDD is in the range 0.4 to 0.8 V.
1998 Feb 05
11
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
12 TIMING
handbook, full pagewidth
t0
A2 to A0
valid address
t1
D7 to D0
t2
valid data
3-state
3-state
t4
t3
CS0 or CS1
t7
RD
t5
t6
RDY
MGK145
A(1)
B(2)
(1) Event A occurs when RD + CS0 + CS1 = 0 (boolean).
(2) Event B occurs when RD + CS0 + CS1 = 1 (boolean).
Fig.3 Intel mode interface read cycle timing.
Table 3
Intel-mode interface read cycle timing (12 MHz clock)
SYMBOL
DESCRIPTION
MIN.
MAX.
UNIT
t0
minimum cycle time
333
833
ns
t1
address set-up time before event A
0
−
ns
t2
address hold time after event B
0
−
ns
t3
data settling time
88
712
ns
t4
data hold time after event B
0
−
ns
t5
time from event A until RDY goes LOW
83
170
ns
t6
RDY LOW time
83
530
ns
t7
event B to next event A time
83
−
ns
1998 Feb 05
12
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
handbook, full pagewidth
t0
A2 to A0
valid address
t1
t2
D7 to D0
valid data
t4
t3
CS0 or CS1
t7
WR
t5
t6
RDY
MGK146
A(1)
B(2)
(1) Event A occurs when WR + CS0 + CS1 = 0 (boolean).
(2) Event B occurs when WR + CS0 + CS1 = 1 (boolean).
Fig.4 Intel mode interface write cycle timing.
Table 4
Intel-mode interface write cycle timing (12 MHz clock)
SYMBOL
DESCRIPTION
MIN.
MAX.
UNIT
t0
minimum cycle time
333
833
ns
t1
address set-up time
0
−
ns
t2
address hold time
0
−
ns
t3
data set-up time, note 1
0
−
ns
t4
data hold time
0
−
ns
t5
RDY set-up time
83
170
ns
t6
RDY LOW time
83
530
ns
t7
event B to next event A time
83
−
ns
Note
1. Legacy AT bus PCs may not satisfy this requirement as they are not ISA compatible. An application fix is available
in the “SAA5284 Users Guide”.
1998 Feb 05
13
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
handbook, full pagewidth
DMARQ
t2
t1
DMACK
t3
CS
(same signal
as DMACK)
t4
t5
t6
RD(1)
t7
valid data
D7 to D0
valid data
MGK147
(1) Read data pipelined, so no RD LOW to data valid set-up time.
Fig.5 Intel mode interface DMA cycle timing.
Table 5
Intel-mode interface DMA cycle timing (12 MHz clock)
SYMBOL
DESCRIPTION
MIN.
0
MAX.
−
UNIT
t1
DMARQ to DMACK
ns
t2
RD LOW to DMARQ LOW
0
212
ns
t3
cycle time
252
−
ns
t4
DMACK to RD active
−
0
ns
ns
t5
data set-up time
0
90(1)
t6
data hold time
83
−
ns
t7
data hold from DMACK HIGH
0
83
ns
Note
1. This timing will be up to 3 clock cycles for the first read in DMA transfer.
1998 Feb 05
14
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
handbook, full pagewidth
t0
valid address
A2 to A0
t1
D7 to D0
t2
3-state
valid data
3-state
t3
CS1 or CS0
t7
R/W
LDS
t4
t6
t5
DTACK
MGK148
A
(1)
B
(2)
(1) Event A occurs when LDS + CS0 + CS1 = 0 (boolean).
(2) Event B occurs when LDS + CS0 + CS1 = 1 (boolean).
Fig.6 Motorola mode interface read cycle timing.
Table 6
Motorola-mode interface read cycle timing (12 MHz clock)
SYMBOL
DESCRIPTION
MIN.
MAX.
UNIT
t0
minimum cycle time
333
833
ns
t1
address set-up time before event A
0
−
ns
t2
address hold time after event B
0
−
ns
t3
data hold time from event B
0
−
ns
t4
data settling time
88
712
ns
t5
data valid to DTACK LOW
83
170
ns
t6
LDS HIGH to DTACK HIGH
83
212
ns
t7
delay between cycles
83
−
ns
1998 Feb 05
15
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
handbook, full pagewidth
t0
valid address
A2 to A0
t1
D7 to D0
t2
3-state
valid data
3-state
t3
CS1 or CS0
t7
R/W
t4
LDS
t6
t5
DTACK
(1)
MGK149
B(2)
A
(1) Event A occurs when LDS + CS0 + CS1 = 0 (boolean).
(2) Event B occurs when LDS + CS0 + CS1 = 1 (boolean).
Fig.7 Motorola mode interface write cycle timing.
Table 7
Motorola-mode interface write cycle timing (12 MHz clock)
SYMBOL
DESCRIPTION
MIN.
MAX.
UNIT
t0
minimum cycle time
333
417
ns
t1
address set-up time before event A
0
−
ns
t2
address hold time after event B
0
−
ns
t3
data hold time from event B
0
−
ns
t4
data set-up time
0
−
ns
t5
DTACK set-up time
−
212
ns
t6
LDS HIGH to DTACK HIGH
83
212
ns
t7
delay between cycles
83
−
ns
1998 Feb 05
16
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
tr
handbook, full pagewidth
tHIGH
tf
tLOW
SCL
tHD;STA
tSU;DAT
tSU;STA
tHD;DAT
tSU;STO
SDA
MGG741
tBUF
Fig.8 I2C-bus timing diagram.
handbook, full pagewidth
VPOIN
t0
VPOOUT
t1
t2
t3
CS0 or CS1
t4
LLC
LLC2
MGK150
Fig.9 Digital video mode interface timing.
Table 8
Digital video mode interface timing with 13.5 MHz clock and 27 MHz LLC
SYMBOL
DESCRIPTION
MIN.
TYP.
MAX.
UNIT
t0
VPOIN set-up time
4
5
6
ns
t1
VPOOUT set-up time
8
10
22
ns
t2
CS HIGH to VPOOUT 3-state
6
10
25
ns
t3
CS LOW to VPOOUT enabled
9
11
16
ns
t4
clock qualifier set-up time
−
1.1
−
ns
1998 Feb 05
17
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
13 APPLICATION INFORMATION
13.3
13.1
PC application software is available providing two levels of
interface. At a low level a VxD based driver offers generic
packet gathering and buffering. Full support is provided for
ISA based applications with facility for PCI based
applications. Higher level support is provided by a series
of DLLs. These perform normal teletext display generation
and page management.
Hardware application circuit for ISA card
A typical application circuit diagram (for the ISA card
application) is shown in Fig.10.
13.2
Hardware application circuit for PCI application
This PCI application is based around the Philips SAA7146
video to PCI bridge IC. SAA7146 has a ‘Data Expansion
Bus Interface’ (DEBI) which is an Intel/Motorola style
16-bit parallel interface. This is used to facilitate
communications to SAA5284.
The application circuit diagram is shown in Fig.11.
1998 Feb 05
18
Software application information
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
handbook, full pagewidth
VDDD = +5 V
VDDA = +5 V
VDDA
100 nF
BLACK
VSSA = 0 V
27 kΩ
75 Ω
IREF
VDDD
16
41
VDDX
6
12
D7
20
21
13
CVBS0
CVBS0
100 nF
CVBS1
OSCIN
8
22
pF
SAA5284
OSCGND
SCL
9
HREF
LLC
LLC2
VPOIN1
VPOIN0
RDY(2)
WR
33
RESET
1
DENB
5
38
40
18
19
11
VSSA VSSD3 VSSD1 VSSD2 SEL1
10
44
SEL0 CS1
VSSA = 0 V
VSSD = 0 V
B1
B8
B7
B6
supply decoupling
VDDA
n.c.
VDDD
+5 V
B5
B4
B3
100
nF
B2
10
µF
VSSD
B0
11
B9
VSSA
n.c.
CS0
35
17
10
µF
RESET
39
VSSD = 0 V
100
nF
IOR
DACKx
DMACK(3)
37
43
I/O RDY
DMARQ
36
42
IRQx
IOW
RD
34
2
A2
INT
32
4
A1
A2
30
3
A0
A1
31
SDA
D0
A0
29
7
D1
D0
28
OSCOUT
D2
D1
26
12 MHz(1)
22
pF
D3
D2
27
75 Ω
D4
D3
24
14
D5
D4
25
CVBS1
D6
D5
22
15
D7
D6
23
100 nF
VSSA = 0 V
SAA5284
9
1
19
18
17
16
15
14
13
2
ADDRESS
DECODER
e.g.
PLUS153
or
74 SERIES
LOGIC
3
4
5
6
7
12
8
10
0V
GND
VSSD = 0 V
I0
I1
I2
I3
I4
I5
I6
I7
AEN
A3
A4
A5
A6
A7
A8
A9
20
VCC
VDDD = 5 V
MGG742
(1) Option of 13.5, 15 and 16 MHz or direct feed from external clock.
(2) A diode to VDDD is recommended for ESD protection.
(3) Pin DMACK must be connected to VDDD if DMA is not used.
Fig.10 Application circuit diagram for ISA card.
1998 Feb 05
19
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VDDA
100 nF
VSSA = 0 V
27 kΩ
75 Ω
IREF
100 nF
CVBS0
100 nF
CVBS1
CVBS0
CVBS1
12 MHz(1)
22
pF
OSCOUT
20
22
pF
OSCGND
+5 V
HREF
LLC
100
nF
10
µF
LLC2
VPOIN1
VSSA
VSSD
20
21
13
22
15
24
14
26
0V
8
28
29
VPOIN0
XAD7
D6
XAD6
D5
XAD5
D4
XAD4
D3
XAD3
D2
XAD2
D1
XAD1
D0
XAD0
A0
1Q
A1
2Q
A2
3Q
3
35
4
31
32
2
33
42
34
43
36
37
39
1
38
40
18
19
16
2
15
3
132
131
130
129
126
125
124
123
1D
2D
74HCT75
30
9
17
VSSD = 0 V
D7
7
SAA5284
SCL
VDDD
10
µF
DEBI PORT
6
25
SDA
100
nF
41
12
23
OSCIN
supply decoupling
VDDA
16
SAA7145
SAA7146
VDDX
27
75 Ω
VSSA = 0 V
BLACK
VDDD
11
VSSA VSSD3 VSSD1 VSSD2 SEL1
10
44
5
CS0
10
13
LE
6
3D
4D
4 7
LE
INT
ALE
XIRQ
RDY
RDY
WR
WRN
RD
RDN
DMARQ
DMACK
RESET
DENB
SEL0 CS1
n.c.
VDDD
114
118
117
116
115
5 kΩ
VDDD
RESET
23
n.c.
MGG744
Fig.11 Application circuit diagram for PCI application.
SAA5284
(1) Option of 13.5, 15 and 16 MHz or LLC2 from the SAA7111 if in 13.5 MHz mode.
Objective specification
VSSA = 0 V
VSSD = 0 V
Philips Semiconductors
VDDD = +5 V
Multimedia video data acquisition circuit
handbook, full pagewidth
1998 Feb 05
VDDA = +5 V
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
14 PACKAGE OUTLINE
QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm
SOT205-1
c
y
X
33
A
23
34
22
ZE
e
E HE
A
A2
(A 3)
A1
wM
θ
bp
Lp
pin 1 index
44
L
12
detail X
1
11
ZD
e
v M A
wM
bp
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
2.60
0.25
0.05
2.3
2.1
0.25
0.50
0.35
0.25
0.14
14.1
13.9
14.1
13.9
1
19.2
18.2
19.2
18.2
2.35
2.0
1.2
0.3
0.15
0.1
Z D (1) Z E (1)
2.4
1.8
2.4
1.8
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
SOT205-1
133E01A
1998 Feb 05
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
97-08-01
21
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
15 SOLDERING
15.1
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
15.2
Reflow soldering
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering techniques are suitable for all QFP
packages.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
15.4
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
Wave soldering
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
CAUTION
Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.
1998 Feb 05
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
15.3
SAA5284
22
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
16 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
17 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 Feb 05
23
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Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1997
SCA53
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Printed in The Netherlands
655102/00/02/pp24
Date of release: 1998 Feb 05
Document order number:
9397 750 02768