MOTOROLA SEMICONDUCTOR TECHNICAL DATA 68030/040 PECL-TTL Clock Driver MC10H644 MC100H644 The MC10H/100H644 generates the necessary clocks for the 68030, 68040 and similar microprocessors. The device is functionally equivalent to the H640, but with fewer outputs in a smaller outline 20–lead PLCC package. It is guaranteed to meet the clock specifications required by the 68030 and 68040 in terms of part–to–part skew, within–part skew and also duty cycle skew. • • • • • • • 68030/040 PECL–TTL CLOCK DRIVER Generates Clocks for 68030/040 Meets 68030/040 Skew Requirements TTL or PECL Input Clock Extra TTL and ECL Power/Ground Pins Within Device Skew on Similar Paths is 0.5 ns Asynchronous Reset Single +5.0V Supply The user has a choice of using either TTL or PECL (ECL referenced to FN SUFFIX +5.0V) for the input clock. TTL clocks are typically used in present MPU PLASTIC PACKAGE systems. However, as clock speeds increase to 50MHz and beyond, the CASE 775–02 inherent superiority of ECL (particularly differential ECL) as a means of clock signal distribution becomes increasingly evident. The H644 also uses differential ECL internally to achieve its superior skew characteristic. The H644 includes divide–by–two and divide–by–four stages, both to achieve the necessary duty cycle and skew to generate MPU clocks as required. A typical 50MHz processor application would use an input clock running at 100MHz, thus obtaining output clocks at 50MHz and 25MHz (see Logic Symbol). The 10H version is compatible with MECL 10H ECL logic levels, while the 100H version is compatible with 100K levels (referenced to +5.0V). Function Reset (R): LOW on RESET forces all Q outputs LOW and all Q outputs HIGH. Synchronized Outputs: The device is designed to have the POS edges of the ÷2 and ÷4 outputs synchronized. Select (SEL): LOW selects the ECL input source (DE/DE). HIGH selects the TTL input source (DT). The H644 also contains circuitry to force a stable state of the ECL input differential pair, should both sides be left open. In this case, the DE side of the input is pulled LOW, and DE goes HIGH. Pinout: 20–Lead PLCC (Top View) Q4 VT Q5 GT R 18 17 16 15 14 GT 19 13 VE Q3 20 12 DE GT 1 11 VBB Q2 2 10 DE GT 3 9 GE 4 5 6 7 8 Q1 VT Q0 SEL DT MECL 10H is a trademark of Motorola, Inc. 11/93 Motorola, Inc. 1995 2–1 REV 3 MC10H644 MC100H644 LOGIC DIAGRAM TTL OUTPUTS VBB Q0 DE (ECL) DE (ECL) PIN NAMES PIN FUNCTION GT VT VE GE DE, DE VBB DT Qn, Qn SEL R ÷2 2:1 MUX Q1 DT (TTL) TTL Ground (0V) TTL VCC (+5.0V) ECL VCC (+5.0V) ECL Ground (0V) ECL Signal Input (positive ECL) VBB Reference Output TTL Signal Input Signal Outputs (TTL) Input Select (TTL) Reset (TTL) Q2 Q3 SEL (TTL) ÷4 Q4 R (TTL) Q5 AC CHARACTERISTICS (VT = VE = 5.0 V ±5%) 0°C Symbol Characteristic 25°C 85°C Min Max Min Max Min Max Unit 5.8 6.8 5.7 6.7 6.1 7.1 ns CL = 50pF 5.7 6.7 5.7 6.7 6.0 7.0 ns CL = 50pF Q0, 1, 4, 5 – 0.5 – 0.5 – 0.5 ns CL = 50pF Within–Device Skew Q2, Q3 – 0.5 – 0.5 – 0.5 ns CL = 50pF tskwd* Within–Device Skew All Outputs – 1.5 – 1.5 – 1.5 ns CL = 50pF tskp–p* Part–to–Part Skew Q0, 1, 4, 5 – 1.0 – 1.0 – 1.0 ns CL = 50pF tPD Propagation Delay R to Output All Outputs 4.3 7.3 4.3 7.3 4.5 7.5 ns CL = 50pF tR tF Output Rise/Fall Time 0.8V – 2.0V All Outputs – 1.6 – 1.6 – 1.6 ns CL = 50pF fmax Maximum Input Frequency 135 – 135 – 135 – MHz CL = 50pF TW Minimum Pulse Width Reset 1.5 – 1.5 – 1.5 – ns trr Reset Recovery Time 1.25 – 1.25 – 1.25 – ns TPW Pulse Width Out High or Low @ fin = 100 MHz and CL = 50 pf 9.5 10.5 9.5 10.5 9.5 10.5 ns TS Setup Time SEL to DE, DT 2.0 – 2.0 – 2.0 – Hold Time SEL to DE, DT 2.0 – 2.0 – 2.0 – tPLH Propagation Delay ECL D to Output tPLH Propagation Delay TTL D to Output tskwd* Within–Device Skew tskwd* TH All Outputs Q0, 1 Condition CL = 50pf Relative 1.5V ns ns * Skews are specified for Identical Edges MOTOROLA 2–2 MECL Data DL122 — Rev 6 MC10H644 MC100H644 DC CHARACTERISTICS (VT = VE = 5.0 V ±5%) 0°C Symbol IEE Characteristic Power Supply Current ICC Min 25°C Max Min 85°C Max Min Max Unit Condition ECL 65 65 65 mA VE Pin TTL 85 85 85 mA Total all VT pins Max Unit TTL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%) 0°C Symbol Characteristic VIH VIL Input HIGH Voltage Input LOW Voltage IIH Min 25°C Max Min 2.0 85°C Max 2.0 Min 2.0 Condition V 0.8 0.8 0.8 Input HIGH Current 20 100 20 100 20 100 µA VIN = 2.7 V VIN = 7.0 V IIL Input LOW Current –0.6 –0.6 –0.6 mA VIN = 0.5 V VOH Output HIGH Voltage VOL Output LOW Voltage VIK Input Clamp Voltage IOS Output Short Circuit Current 2.5 2.0 2.5 2.0 2.5 2.0 0.5 IOH = –3.0 mA IOH = –24 mA V IOL = 24 mA –1.2 V IIN = –18 mA –225 mA VOUT = 0 V 0.5 –1.2 –100 V 0.5 –1.2 –225 –100 –225 –100 10H PECL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%) 0°C Symbol Characteristic Min 25°C Max Min 85°C Max 225 Min 175 Max Unit 175 µA Condition IIH IIL Input HIGH Current Input LOW Current 0.5 VIH* VIL* Input HIGH Voltage Input LOW Voltage 3.83 3.05 4.16 3.52 3.87 3.05 4.19 3.52 3.94 3.05 4.28 3.55 V VE = 5.0 V VBB* Output Reference Voltage 3.62 3.73 3.65 3.75 3.69 3.81 V VE = 5.0 V Max Unit 175 µA 4.12 3.525 V 0.5 0.5 100H PECL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%) 0°C Symbol Characteristic Min IIH IIL Input HIGH Current Input LOW Current 0.5 VIH* VIL* Input HIGH Voltage Input LOW Voltage 3.835 3.19 25°C Max Min 225 85°C Max Min 175 0.5 4.12 3.525 3.835 3.19 Condition 0.5 4.12 3.525 3.835 3.19 VE = 5.0 V VBB* Output Reference Voltage 3.62 3.74 3.62 3.74 3.62 3.74 V VE = 5.0 V * NOTE: PECL levels are referenced to VCC and will vary 1:1 with the power supply. The values shown are for VCC = 5.0 V. Only corresponds to ECL Clock Inputs. MECL Data DL122 — Rev 6 2–3 MOTOROLA MC10H644 MC100H644 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 776–02 ISSUE D 0.007 (0.180) B T L–M M N S T L–M S S Y BRK –N– 0.007 (0.180) U M N S D Z –M– –L– W 28 D X G1 0.010 (0.250) T L–M S N S S V 1 VIEW D–D A 0.007 (0.180) R 0.007 (0.180) M T L–M S N S C M T L–M S N 0.007 (0.180) H Z M T L–M N S S S K1 E 0.004 (0.100) G J S K SEATING PLANE F VIEW S G1 0.010 (0.250) –T– T L–M S N S M T L–M S N S VIEW S NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). MOTOROLA 0.007 (0.180) 2–4 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10_ 0.410 0.430 0.040 ––– MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10_ 10.42 10.92 1.02 ––– MECL Data DL122 — Rev 6 MC10H644 MC100H644 Motorola reserves the right to make changes without further notice to any products herein. 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