ONSEMI NTHD4508NT1

NTHD4508N
Power MOSFET
20 V, 4.1 A, Dual N−Channel ChipFET
Features
•
•
•
•
Low RDS(on) and Fast Switching Speed
Leadless ChipFET Package has 40% Smaller Footprint than TSOP−6
Excellent Thermal Capabilities Where Heat Transfer is Required
Pb−Free Package is Available
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V(BR)DSS
RDS(on) TYP
Applications
• DC−DC Buck/Boost Converters
• Battery and Low Side Switching in Portable Equipment Such as MP3
ID MAX
60 m @ 4.5 V
20 V
4.1 A
80 m @ 2.5 V
Players, Cell Phones, DSCs and PDAs
• Level Shifting
D1, D2
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
20
V
Gate−to−Source Voltage
VGS
±12
V
ID
3.0
A
Continuous Drain
Current
Steady
State
t5s
Power Dissipation
Steady
State
t5s
Pulsed Drain Current
TJ = 25 °C
TJ = 85 °C
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
2.1
IDM
12
A
TJ,
TSTG
−55 to
150
°C
TL
260
°C
Parameter
Symbol
Max
Unit
RθJA
110
°C/W
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq
[1 oz] including traces).
PIN
CONNECTIONS
MARKING
DIAGRAM
D1 8
1 S1
1
8
D1 7
2 G1
2
7
D2 6
3 S2
3
D2 5
4 G2
4
C8 M
THERMAL RESISTANCE RATINGS
Junction−to−Ambient – Steady State
(Note 1)
ChipFET
CASE 1206A
STYLE 2
W
1.13
0.59
TJ = 25 °C
Operating Junction and Storage Temperature
N−Channel MOSFET
4.1
PD
TJ = 85 °C
tp = 10 µs
S1, S2
2.2
TJ = 25 °C
TJ = 25 °C
G 1 , G2
6
5
C8 = Specific Device Code
M = Month Code
ORDERING INFORMATION
Package
Shipping†
NTHD4508NT1
ChipFET
3000/Tape & Reel
NTHD4508NT1G
ChipFET
(Pb−Free)
3000/Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
 Semiconductor Components Industries, LLC, 2004
October, 2004 − Rev. 3
1
Publication Order Number:
NTHD4508N/D
NTHD4508N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Conditions
Min
V(BR)DSS
VGS = 0 V
20
IDSS
Typ
Max
Units
VGS = 0 V, VDS = 16 V
1.0
A
VGS = 0 V, VDS = 16 V, TJ = 125°C
10
IGSS
VDS = 0 V, VGS = 12 V
100
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250 A
Drain−to−Source On−Resistance
RDS(on)
( )
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
V
nA
ON CHARACTERISTICS (Note 2)
Forward Transconductance
gFS
0.6
1.2
V
m
VGS = 4.5, ID = 3.1 A
60
75
VGS = 2.5, ID = 2.3 A
80
115
VDS = 10 V, ID = 3.1 A
6.0
S
180
pF
CHARGES AND CAPACITANCES
Input Capacitance
CISS
V f = 1.0
1 0 MHz,
MH
VGS = 0 V,
VDS = 10 V
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
25
Total Gate Charge
QG(TOT)
2.6
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
0.7
td(ON)
VGS = 4.5 V, VDS = 10 V,
ID = 3.1 A
80
4.0
nC
5.0
10
ns
15
30
10
20
3.0
6.0
0.75
1.15
0.5
0.6
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
tr
td(OFF)
Fall Time
VGS = 4.5 V, VDS = 16 V,
ID = 3.1 A, RG = 2.5 tf
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V, IS = 3.1 A
12.5
VGS = 0 V, IS = 1.5 A,
dIS/dt = 100 A/s
QRR
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2
ns
9.0
3.5
6.0
2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
3. Switching characteristics are independent of operating junction temperatures.
V
nC
NTHD4508N
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
8
VGS = 5 V to 3 V
VGS = 2.4 V
2V
2.2 V
6
4
1.8 V
2
1.6 V
1.4 V
4
2
TC = −55°C
100°C
0
1
2
3
4
5
6
7
8
9
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0
0.5
1
1.5
2
2.5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
6
25°C
0
0.15
ID = 3.1 A
TJ = 25°C
0.10
0.05
0
0
3
5
2
4
1
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
6
3
0.1
TJ = 25°C
VGS = 2.5 V
0.07
VGS = 4.5 V
0.04
1
3
7
5
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.7
100
ID = 3.1 A
VGS = 4.5 V
VGS = 0 V
1.5
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
VDS ≥ 10 V
TJ = 25°C
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
8
1.3
1.1
TJ = 100°C
10
0.9
0.7
−50
1
−25
0
25
50
75
100
125
150
2
4
6
8
10
12
14
16
18
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
20
NTHD4508N
C, CAPACITANCE (pF)
CISS
VDS = 0 V
VGS = 0 V
TJ = 25°C
300
CRSS
200
100
COSS
0
10
5
VGS
0
VDS
5
10
15
20
5
QG
7.5
3
QGS
2
5.0
QGD
2.5
1
ID = 3.1 A
TJ = 25°C
0
0
0.5
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1
1.5
2
2.5
QG, TOTAL GATE CHARGE (nC)
0
3
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Figure 7. Capacitance Variation
7
100
10
IS, SOURCE CURRENT (AMPS)
VDD = 16 V
ID = 2.3 A
VGS = 4.5 V
t, TIME (ns)
10
4
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
400
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
td(off)
tr
td(on)
tf
1
1
10
VGS = 0 V
TJ = 25°C
6
5
4
3
2
1
0
0.3
100
0.45
0.6
0.75
0.9
1.05
RG, GATE RESISTANCE (OHMS)
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
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4
1.2
NTHD4508N
SOLDERING FOOTPRINTS*
2.032
0.08
2.032
0.08
0.457
0.018
0.635
0.025
1.032
0.043
0.635
0.025
0.178
0.007
0.457
0.018
0.711
0.028
0.66
0.026
0.66
0.026
Figure 11. Basic
0.254
0.010
SCALE 20:1
mm inches
Figure 12. Style 2
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BASIC PAD PATTERNS
footprint. The drain copper area is 0.0019 sq. in. (or 1.22 sq.
mm). This will assist the power dissipation path away from
the device (through the copper lead−frame) and into the
board and exterior chassis (if applicable) for the single
device. The addition of a further copper area and/or the
addition of vias to other board layers will enhance the
performance still further.
The basic pad layout with dimensions is shown in
Figure 11. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area, particularly
for the drain leads.
The minimum recommended pad pattern shown in Figure
12 improves the thermal area of the drain connections (pins
5, 6, 7, 8) while remaining within the confines of the basic
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5
NTHD4508N
PACKAGE DIMENSIONS
ChipFET
CASE 1206A−03
ISSUE E
A
8
7
M
6
K
5
S
5
6
7
8
4
3
2
1
B
1
2
3
L
4
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM
PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN
HORIZONTAL AND VERTICAL SHALL NOT EXCEED
0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE
BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND
BOTTOM LEAD SURFACE.
7. 1206A−01 AND 1206A−02 OBSOLETE. NEW
STANDARD IS 1206A−03.
J
G
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
C
0.05 (0.002)
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
DIM
A
B
C
D
G
J
K
L
M
S
MILLIMETERS
MIN
MAX
2.95
3.10
1.55
1.70
1.00
1.10
0.25
0.35
0.65 BSC
0.10
0.20
0.28
0.42
0.55 BSC
5 ° NOM
2.00
1.80
INCHES
MIN
MAX
0.116
0.122
0.061
0.067
0.039
0.043
0.010
0.014
0.025 BSC
0.004
0.008
0.011
0.017
0.022 BSC
5 ° NOM
0.072
0.080
ChipFET is a trademark of Vishay Siliconix.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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For additional information, please contact your
local Sales Representative.
NTHD4508N/D