ONSEMI NTHS4101P

NTHS4101P
Power MOSFET
−20 V, 6.7 A, P−Channel ChipFETt
Features
• Offers an Ultra Low RDS(on) Solution in the ChipFET Package
• Miniature ChipFET Package 40% Smaller Footprint than TSOP−6
•
•
•
•
•
making it an Ideal Device for Applications where Board Space is at a
Premium
Low Profile (<1.1 mm) Allows it to Fit Easily into Extremely Thin
Environments such as Portable Electronics
Designed to Provide Low RDS(on) at Gate Voltage as Low as 1.8 V, the
Operating Voltage used in many Logic ICs in Portable Electronics
Simplifies Circuit Design since Additional Boost Circuits for Gate
Voltages are not Required
Operated at Standard Logic Level Gate Drive, Facilitating Future
Migration to Lower Levels using the same Basic Topology
Pb−Free Package is Available
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RDS(on) TYP
V(BR)DSS
ID MAX
21 mW @ −4.5 V
−20 V
−6.7 A
30 mW @ −2.5 V
42 mW @ −1.8 V
S
G
Applications
• Optimized for Battery and Load Management Applications in
•
•
D
Portable Equipment such as MP3 Players, Cell Phones, Digital
Cameras, Personal Digital Assistant and other Portable Applications
Charge Control in Battery Chargers
Buck and Boost Converters
P−Channel MOSFET
1
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Value
Unit
Drain−to−Source Voltage
VDSS
−20
Vdc
Gate−to−Source Voltage − Continuous
VGS
"8.0
Vdc
Drain Current − Continuous
− 5 seconds
ID
ID
−4.8
−6.7
A
Total Power Dissipation
Continuous @ TA = 25°C
(5 sec) @ TA = 25°C
Continuous @ 85°C
(5 sec) @ 85°C
PD
Pulsed Drain Current − tp = 10 ms
IDM
−190
A
Is
−4.8
A
RqJA
RqJA
50
95
TL
260
Thermal Resistance (Note 1)
Junction−to−Ambient, 5 sec
Junction−to−Ambient, Continuous
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
W
1.3
2.5
0.7
1.3
°C/W
°C
February, 2007 − Rev. 3
1
MARKING
DIAGRAM
D
8
1
D
1
D
7
2
D
2
D
6
3
D
3
S
5
4
G
4
8
7
6
5
C6 = Specific Device Code
M = Month Code
G = Pb−Free Package
ORDERING INFORMATION
Package
Shipping †
NTHS4101PT1
ChipFET
3000 Tape / Reel
NTHS4101PT1G
ChipFET
(Pb−free)
3000 Tape / Reel
Device
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq
[1 oz] including traces).
© Semiconductor Components Industries, LLC, 2007
PIN
CONNECTIONS
C6 M
G
Symbol
Continuous Source Current
ChipFET
CASE 1206A
STYLE 1
8
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NTHS4101P/D
NTHS4101P
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Test Condition
Min
V(Br)DSS
VGS = 0 Vdc, ID = −250 mAdc
−20
Gate−Body Leakage Current Zero
IGSS
VDS = 0 Vdc, VGS = "8.0 Vdc
"100
nAdc
Zero Gate Voltage Drain Current
IDSS
VDS = −16 Vdc, VGS = 0 Vdc
VDS = −16 Vdc, VGS = 0 Vdc,
TJ = 85°C
−1.0
−5.0
mAdc
Gate Threshold Voltage
VGS(th)
VDS = VGS, ID = −250 mAdc
−1.5
Vdc
Static Drain−to−Source On−Resistance
RDS(on)
VGS = −4.5 Vdc, ID = −4.8 Adc
VGS = −2.5 Vdc, ID = −4.2 Adc
VGS = −1.8 Vdc, ID = −1.0 Adc
21
30
42
34
40
52
mW
Forward Transconductance
gFS
VDS = −5.0 Vdc, ID = −4.8 Adc
15
Diode Forward Voltage
VSD
IS = −4.8 Adc, VGS = 0 Vdc
−0.8
Input Capacitance
Ciss
2100
Output Capacitance
Coss
VDS = −16 Vdc
VGS = 0 V
f = 1.0 MHz
Transfer Capacitance
Crss
Characteristic
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 2)
Temperature Coefficient (Positive)
Vdc
ON CHARACTERISTICS (Note 2)
−0.45
S
−1.2
V
DYNAMIC CHARACTERISTICS
pF
290
200
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
td(on)
VDD = −16 Vdc
8.0
tr
VGS = −4.5 Vdc
28
td(off)
ID = −4.5 Adc
75
tf
RG = 2.5 W
60
Qg
VGS = −4.5 Vdc
25
Qgs
ID = −4.5 Adc
4.0
Qgd
VDS = −16 Vdc (Note 3)
7.0
2. Pulse Test: Pulse Width = 250 ms, Duty Cycle = 2%.
3. Switching characteristics are independent of operating junction temperatures.
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2
ns
35
nC
NTHS4101P
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
−1.8 V
8
7
6
5
−1.6 V
4
3
2
−1.4 V
1
−1.2 V
0
0
1
2
3
4
5
9
8
7
6
5
4
125°C
3
25°C
2
TJ = −55°C
1
0
6
7
8
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.5
1
1.5
2
2.5
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0
3
1.5
0.1
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
VGS = −1.8 V
0.08
0.06
0.04
VGS = −2.5 V
0.02
VGS = −4.5 V
2
4
8
10
12
−ID, DRAIN CURRENT (AMPS)
6
14
VGS = −4.5 V
1.3
1.1
0.9
0.7
0.5
−50
0
16
−25
0
25
75
100
125
Figure 4. On−Resistance Variation with
Temperature
10000
VGS = 0 V
TJ = 125°C
1000
TJ = 100°C
100
10
TJ = 25°C
1
0.1
0
50
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. On−Resistance vs. Drain Current and
Gate Voltage
−IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
10
TJ = 25°C
VGS = −10 V to −2.4 V
9
−ID, DRAIN CURRENT (AMPS)
−ID, DRAIN CURRENT (AMPS)
10
2
4
6
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. Drain−to−Source Leakage Current
vs. Voltage
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3
8
150
NTHS4101P
5000
C, CAPACITANCE (pF)
4500
VDS = 0 V
VGS = 0 V
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
TJ = 25°C
4000
3500
3000
2500
2000
Ciss
Crss
1500
1000
Coss
500
0
−6 −4 −2 0 2
−VGS −VDS
4
6
10 12 14 16 18 20
8
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
QT
4
3
2
Q2
Q1
1
ID = −4.5 A
TJ = 25°C
0
0
3
12
21
6
9
15
18
Qg, TOTAL GATE CHARGE (nC)
24
27
Figure 7. Gate−to−Source and Drain−to−Source
Voltage vs. Total Gate Charge
Figure 6. Capacitance Variation
1000
5
100
−IS, SOURCE CURRENT (AMPS)
VDD = −16 V
ID = −4.5 A
VGS = −4.5 V
td(off)
tf
tr
10
td(on)
1
1
10
VGS = 0 V
TJ = 25°C
4
3
2
1
0
0.4
100
0.5
0.6
Figure 8. Resistive Switching Time Variation
vs. Gate Resistance
10
10 ms
100 ms
1 ms
VGS = −8 V
SINGLE PULSE
TC = 25°C
0.1
0.01
0.1
0.8
0.9
1.0
Figure 9. Diode Forward Voltage vs. Current
100
1
0.7
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
RG, GATE RESISTANCE (OHMS)
−I D, DRAIN CURRENT (AMPS)
t, TIME (ns)
5
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
dc
1
10
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 10. Maximum Rated Forward Biased
Safe Operating Area
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4
100
NTHS4101P
PACKAGE DIMENSIONS
ChipFETt
CASE 1206A−03
ISSUE H
D
8
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
q
6
L
5
HE
5
6
7
8
4
3
2
1
E
1
2
3
e1
4
b
c
e
MILLIMETERS
NOM
MAX
1.05
1.10
0.30
0.35
0.15
0.20
3.05
3.10
1.65
1.70
0.65 BSC
0.55 BSC
0.28
0.35
0.42
1.80
1.90
2.00
5° NOM
DIM
A
b
c
D
E
e
e1
L
HE
q
A
0.05 (0.002)
MIN
1.00
0.25
0.10
2.95
1.55
INCHES
NOM
0.041
0.012
0.006
0.120
0.065
0.025 BSC
0.022 BSC
0.011
0.014
0.071
0.075
5° NOM
MIN
0.039
0.010
0.004
0.116
0.061
MAX
0.043
0.014
0.008
0.122
0.067
0.017
0.079
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. GATE
5. SOURCE
6. DRAIN
7. DRAIN
8. DRAIN
SOLDERING FOOTPRINTS*
1
2.032
0.08
1
2.032
0.08
1.727
0.068
2.362
0.093
0.635
0.025
PITCH
2.362
0.093
8X
8X
0.66
0.026
0.457
0.018
2X
2X
mm Ǔ
ǒinches
0.457
0.018
Basic
0.66
0.026
Style 1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
5
mm Ǔ
ǒinches
NTHS4101P
ChipFET is a trademark of Vishay Siliconix.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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6
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For additional information, please contact your local
Sales Representative
NTHS4101P/D