NCP4672 Dual Linear Voltage Regulators with Vin and Vout Voltage Detector The NCP4672 is a dual linear voltage regulator with input voltage and output voltage detectors. This part is useful in systems where multiple voltages are required such as for core and I/O. The NCP4672 is very accurate at 2% over full input voltage and full load current. The NCP4672 eliminates the need for external voltage supervision due to the two built in voltage detectors. The voltage detector on the input is set to 7.0 V. The output voltage detector is for channel 1 and is set to 2.9 V. An external capacitor is used to set the duration of this reset signal. Other features include short circuit protection and thermal shutdown protection. The NCP4672 has been designed to work with a 4.7 F output capacitor having an ESR between 0.1 and 5.0 . Features • • • • • • • http://onsemi.com MARKING DIAGRAM 8 SOIC−8 NB SUFFIX CASE 751 8 1 1 4672G A L YW Accuracy: 2% at Full Voltage and Load Excellent Ripple Rejection: 70 dB @ 1 kHz Voltage Detector for Input Voltage Voltage Detector for Output Voltage Programmable Delay of Reset Signal Thermal Short Circuit Protection This is a Pb−Free Device = Specific Device Code = Assembly Location = Wafer Lot = Date Code PIN CONFIGURATION Vin Rst 1 8 Vout1 Vout Rst 2 7 GND1 CD 3 6 GND2 Vin 4 5 Vout2 Typical Application • • • • 4672G ALYW Small Core and I/O Power Consumer Equipment Measurement Equipment Industrial Equipment (Top View) Vin RST ORDERING INFORMATION 10 K Vin Vin Rst Vout1 Vout1 Cout2 4.7 F Vout Rst GND1 10 nF Vin CD GND2 Vin Vout2 Cin 0.1 F Device Package NCP4672DR2G SOIC−8 (Pb−Free) Shipping† 2500 Tape & Reel Vout2 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Cout2 4.7 F Figure 1. Typical Application Circuit Semiconductor Components Industries, LLC, 2004 February, 2004 − Rev. 4 1 Publication Order Number: NCP4672/D NCP4672 MAXIMUM RATINGS Rating Input Voltage Symbol Value Unit Vinmax −0.3 ~ 18 V Vout −0.3 to Vin + 0.3 V Iout1max Iout2max 30 80 mA mA − Infinite − PD RJA Internally Limited W °C/W °C/W °C/W Output Voltage Output Current 1 Output Current 2 Output Short Circuit Duration Power Dissipation and Thermal Characteristics − SOIC−8 Power Dissipation Thermal Resistance, Junction−to−Ambient Minimum Pad Size 200 mm2 Pad Size (Note 1) Thermal Resistance, Junction−to−Case RJC 190 160 25 Operating Junction Temperature Range Tstg −40 to 125 °C Tsolder −55 to 150 °C Storage Temperature Range 1. Refer to Figure 4 for more information. PIN DESCRIPTION Pin Number Symbol 1 Vin RST Open−collector, active−low output of the input voltage detector with hysteresis. Threshold levels are typical 7.0 V/ 7.35 V at VCC pin. 2 Vo RST Active−low output of the reset generator. Reset generator is based on sensing of the Vout1 voltage. Sensing is with hysteresis − threshold levels are typically 2.9 V/ 2.95 V at Vout1. Reset is generated at rising edge of the Vout1 and it’s duration is set by external capacitor connected to CD pin. 3 CD Programmable delay of the reset generator. Delay is adjusted by inserting a capacitor between CD and GND (typically 10 ms for 10 nF capacitor). 4 VCC Supply Voltage 5 Vout2 1.8 V/ 80 mA LDO Regulator Output 6 GND2 Ground for Vout2 (internally connected with GND1) 7 GND1 Ground for Vout1 (internally connected with GND2) 8 Vout1 3.5 V/30 mA LDO Regulator Output Description Recommended Conditions (TA = 25°C, Cin = 0.1 F Ceramic, Cout = 4.7 F) Symbol Min Typ Max Unit Input Voltage Vin 3.8 12 16 V Output Current (where Vout remains within accuracy) Iout1 Iout2 0 0 − − 20 70 mA Characteristics http://onsemi.com 2 NCP4672 Vin Vout1 2.9 V − + 7.0 V VIn RST + − Vref − + Vref Vref + − Vo RST CD Vref Thermal Shutdown Vout2 − + Vref Thermal Shutdown GND1 GND2 Figure 1. http://onsemi.com 3 NCP4672 ELECTRICAL CHARACTERISTICS (Cin = 0.1 F Ceramic, Cout = 4.7 F with ESR = 0.1 − 5.0 , Vin = 12 V, TA = 25°C) Characteristics Symbol Output Voltage Vout1 (Vin = 4.5 V, Iout1 = 20 mA) Vout2 (Vin = 4.5 V, Iout2 = 40 mA) Min Typ Max 3.43 1.764 3.5 1.8 3.57 1.836 − − 3.0 3.0 30 30 − − 3.0 2.0 40 40 − 150 300 − − 1.0 3.0 2.0 − 30 80 60 150 − − − 165 − Vadj Line Regulation Vout1 (Vin = 4.5 V , Iout1 = 20 mA) Vout2 (Vin = 4.5 V to 10 V, Iout2 = 40 mA) Regline Load Regulation Vout1 (Vin = 4.5 V, Iout1 = 0.1 mA to 20 mA) Vout2 (Vin = 4.5 V, Iout2 = 0.1 mA to 70 mA) Regload Dropout Voltage Vout1 (Vin = 3.3 V, Iout1 = 20 mA) V mV mV Vin − Vout1 Ground Pin Current (Vin = 8.0 V, Iout1 = Iout2 = 0 mA) (Vin = 2.7 V, Iout1 = Iout2 = 0 mA, Rpu = infinite) mV IGND Short Current Limit Vout1 Vout2 mA ISC Thermal Shutdown Temperature Coefficient Vout1 (TJ = −30 to 85°C, Vin = 4.5 V, Iout1 = 20 mA) Vout2 (TJ = −30 to 85°C, Vin = 4.5 V, Iout2 = 40 mA) TC Ripple Rejection (Note 6) Vout1 (Vin = 4.5 V, Vripple = 1.0 V, Iout1 = 20 mA, 120 Hz) Vout2 (Vin = 4.5 V, Vripple = 1.0 V, Iout2 = 40 mA, 120 Hz) RR Output Noise Voltage Vout1 (Vin = 4.5 V, f = 20 Hz − 80 kHz, Iout1 = 20 mA) Vout2 (Vin = 4.5 V, f = 20 Hz − 80 kHz, Iout2 = 40 mA) Vn Unit mA °C ppm/°C − − 100 100 − − − − 65 70 − − − − 80 50 − − dB Vrms Vin Detect Detecting Voltage L (Vin = H to L) VSLin 6.72 7.0 7.28 V Detecting Voltage H (Vin = L to H) VSHin − 7.35 − V Hysteresis Voltage (Vin = H to L to H) VSin 140 350 560 mV VSlin TC − 100 − ppm/°C VOLin1 VOLin2 − − 100 − 200 0.4 mV V Detecting Voltage L (Vin = H to L) VSLout 2.78 2.9 3.020 V Detecting Voltage H (Vin = L to H) VSHout − 2.95 − V Hysteresis Voltage (Vin = H to L to H) VSout 25 50 100 mV VSLin Temperature Coefficient (TJ = −30°C to +85°C) VSLin TC − 100 − ppm/°C Low−Level Output o e e Ou u Voltage o age ((Vout1 = 2.6 6 V)) Threshold Operating Voltage (VOPLout = 0.85 V) VOLout1 VOLout2 − − 100 00 − 200 00 0.4 mV V Reset Delay Time (CD = 10 nF) tPLH 5 10 15 ms “L” Transmission Delay Time (CD = 10 nF) tPHL − 30 90 s VSLin Temperature Coefficient (TJ = −30°C to +85°C) Low−Level Output Voltage (Vin = 6.0 V, Vt1 = 5.0 V, Rt1 = 10 k) (Note 5) Threshold Operating Voltage (VOPLin = Vt1 = 1.0 V) Vout Detect 2. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MIL−STD−883, Method 3015 Machine Model Method 200 V. T TA 3. The maximum package power dissipation is: P D J(max) RJA 4. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 5. Refer to Figure 3. 6. Guaranteed by design. http://onsemi.com 4 NCP4672 VSHin VSin VSLin VOPLin* Vi (Pin4) VOPLin* Vin RST (Pin1) VSout VSHout VSLout Vout1 (Pin8) VOPLout* VOPLout* Vo RST (Pin2) tPLH tPHL tPLH *; VOPLin shows theoretical on this chart. VOPLin spec. must be specified on Pin 1 voltage (0.4 V) *; VOPLout shows theoretical on this chart. VOPLout spec. must be specified on Pin 2 voltage (0.4 V) Figure 2. Dual Regulator Timing Vin RST 1 10 k Vin 4 VOPLin = 1.0 Vtyp VOLin = 0.4 V + − + − GND1 7.0 V 7 Figure 3. Threshold Operating Voltage VOPLin Under Condition VOLin = 0.4 V http://onsemi.com 5 Vt1 Vtyp = 5.0 V Vmax = 16 V NCP4672 R JA , THERMAL RESISTANCE JUNCTION−TO−AIR (° C/W) 200.0 180.0 160.0 140.0 120.0 100.0 80.0 0 200 100 300 400 COPPER AREA 1 oz 500 600 (mm2) 4.0 1.4 3.5 Vout, OUTPUT VOLTAGE (V) 1.6 1.2 1.0 0.8 0.6 0.4 0.2 3.0 Vout1 2.5 Vout2 2.0 1.5 1.0 0.5 0 0 0 2 4 6 8 10 12 14 0 16 20 40 60 80 100 120 Vin, INPUT VOLTAGE (V) Iout, OUTPUT CURRENT (mA) Figure 5. Quiescent Current versus Input Voltage Figure 6. Peak Current Limit 1000 DELAY TIME (ms) IQ, QUIESCENT CURRENT (mA) Figure 4. SOP−8 Thermal Resistance versus P.C.B. Copper Area 100 10 1 0.001 0.01 0.1 CD, CAPACITANCE (F) Figure 7. Delay Time versus Capacitance http://onsemi.com 6 1 140 160 NCP4672 10 4 RPU = 10 k 8 3 VOLTAGE VOLTAGE Vo 6 Vin 4 2 CD = 10 nF Vin RST 1 2 0 0 0 5 10 15 20 25 30 35 0 40 6 8 10 12 14 16 Figure 8. Vin and Vin RST versus Time Figure 9. Vo and Vo RST versus Time 80 70 70 60 50 40 Vin = 12 V Vout1 = 3.5 V Iout1 = 10 mA Cout1 = 4.7 F 20 4 TIME (ms) 80 30 2 TIME (ms) RIPPLE REJECTION (dB) RIPPLE REJECTION (dB) Vo RST 10 18 20 60 50 40 30 Vin = 12 V Vout2 = 1.8 V Iout2 = 10 mA Cout2 = 4.7 F 20 10 0 0 0.01 0.1 1 10 0.01 100 0.1 1 10 FREQUENCY (kHz) FREQUENCY (kHz) Figure 10. Vout1 Ripple Rejection Figure 11. Vout2 Ripple Rejection http://onsemi.com 7 100 NCP4672 PACKAGE DIMENSIONS SOIC−8 NB SUFFIX CASE 751−07 ISSUE AB NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches SOIC−8 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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