Revised December 1998 74ACTQ16543 16-Bit Registered Transceiver with 3-STATE Outputs General Description Features The ACTQ16543 contains sixteen non-inverting transceivers containing two sets of D-type registers for temporary storage of data flowing in either direction. Each byte has separate control inputs which can be shorted together for full 16-bit operation. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent input and output control in either direction of data flow. ■ Utilizes Fairchild FACT Quiet Series technology The ACTQ16543 utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector for superior performance. ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Guaranteed pin-to-pin output skew ■ Independent registers for A and B buses ■ Separate controls for data flow in each direction ■ Back-to-back registers for storage Multiplexed real-time and stored data transfers ■ Separate control logic for each byte ■ 16-bit version of the ACTQ543 ■ Outputs source/sink 24 mA ■ Additional specs for Multiple Output Switching ■ Output loading specs for both 50 pF and 250pF loads Ordering Code: Order Number Package Number 74ACTQ16543SSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Description 74ACTQ16543MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Descriptions OEABn A-to-B Output Enable Input (Active LOW) OEBAn B-to-A Output Enable Input (Active LOW) CEABn A-to-B Enable Input (Active LOW) CEBAn B-to-A Enable Input (Active LOW) LEABn A-to-B Latch Enable Input (Active LOW) LEBAn B-to-A Latch Enable Input (Active LOW) A0–A15 A-to-B Data Inputs or B-to-A 3-STATE Outputs B0–B15 B-to-A Data Inputs or A-to-B 3-STATE Outputs FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS010967.prf www.fairchildsemi.com 74ACTQ16543 16-Bit Registered Transceiver with 3-STATE Outputs December 1991 74ACTQ16543 Connection Diagram Functional Description The ACTQ16543 contains sixteen non-inverting transceivers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins may be shorted together to obtain full 16-bit operation. The following description applies to each byte. For data flow from A to B, for example, the A-to-B Enable (CEABn) input must be LOW in order to enter data from A0–A15 or take data from B0–B15, as indicated in the Data I/O Control Table. With CEABn LOW, a LOW signal on the A-to-B Latch Enable (LEABn) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEABn signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEABn and OEABn both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBA n, LEBAn and OEBAn inputs. Pin Assignment for SSOP and TSSOP Data I/O Control Table Inputs CEABn LEABn OEABn Latch Status (Byte n) Output Buffers (Byte n) High Z H X X Latched X H X Latched — L L X Transparent — X X H — High Z L X L — Driving H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown; B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn www.fairchildsemi.com 2 74ACTQ16543 Logic Diagrams Byte 1 (0:7) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Byte 2 (8:15) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74ACTQ16543 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA Supply Voltage (VCC) DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) 0V to VCC 125 mV/ns VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V ±50 mA Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. ±50 mA per Output Pin −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) DC VCC or Ground Current Storage Temperature 0V to VCC Output Voltage (VO) −0.5V to VCC + 0.5V DC Output Source/Sink Current (IO) 4.5V to 5.5V Input Voltage (VI) −65°C to +150°C DC Electrical Characteristics Symbol VIH VIL VOH Parameter TA = +25°C VCC (V) Typ TA = −40°C to+85°C Guaranteed Limits Minimum HIGH 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Conditions Units V VOUT = 0.1V or VCC − 0.1V V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VILor VIH 4.5 5.5 VOL 4.86 4.76 Maximum LOW 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 IOH = −24 mA (Note 2) V IOUT = 50 µA V IOL = 24 mA VIN = VILor VIH IOZT Maximum I/O 5.5 0.36 0.44 5.5 ±0.5 ±5.0 µA IOL = 24 mA (Note 2) 5.5 ±0.1 ±1.0 µA IIN Maximum Input VI = VCC, 1.5 mA VI = VCC − 2.1V 80.0 µA VIN = VCC 75 mA VOLD = 1.65V Max −75 mA VOHD = 3.85V Min Leakage Current GND ICCT Maximum ICC/Input 5.5 ICC Max Quiescent 5.5 0.6 8.0 Supply Current IOLD Minimum Dynamic IOHD Output Current (Note 3) VOLP Quiet Output or GND 5.5 5.0 0.5 0.8 V Maximum Dynamic VOL VOLV Quiet Output Maximum 5.0 −0.5 −0.8 V Minimum 5.0 VOH + 1.0 VOH + 1.5 V 5.0 VOH − 1.0 VOH − 1.8 V Minimum HIGH Dynamic 5.0 1.7 2.0 V (Note 4)(Note 7) 5.0 1.2 0.8 V (Note 4)(Note 7) Figure 1, Figure 2 (Note 4)(Note 6) VCC Droop VIHD Figure 1, Figure 2 (Note 5)(Note 6) Overshoot VOHV Figure 1, Figure 2 (Note 5)(Note 6) Minimum Dynamic VOL VOHP VI = VIL, VIH VO = VCC, GND Leakage Current Figure 1, Figure 2 (Note 4)(Note 6) Input Voltage Level VILD Maximum LOW Dynamic Input Voltage Level Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms; one output loaded at a time. Note 4: Worst case package. www.fairchildsemi.com 4 74ACTQ16543 DC Electrical Characteristics (Continued) Note 5: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched LOW and one output held LOW. Note 6: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched HIGH and one output held HIGH. Note 7: Maximum number of data inputs (n) switching. (n − 1) inputs switching 0V to 3V Input under test switching 3V to threshold (VILD). AC Electrical Characteristics Symbol Parameter tPLH Propagation Delay tPHL Transparent Mode VCC TA = +25°C (V) CL = 50 pF Typ TA = −40°C to +85°C CL = 50 pF (Note 8) Min Max Min 3.8 5.9 8.3 3.0 9.0 5.0 3.5 5.5 7.9 2.6 8.5 4.7 6.9 9.8 3.4 10.8 3.9 6.3 9.0 3.1 9.8 Units Max ns An to Bnor Bn to An tPLH Propagation Delay tPHL LEBAn, LEABn 5.0 ns to An, Bn tPZH Output Enable Time tPZL OEBAn or OEABn to An or Bn 4.2 6.3 9.2 3.0 9.9 5.0 4.9 7.3 10.3 3.6 10.3 2.8 5.2 8.0 2.1 8.3 5.0 2.6 5.0 7.6 2.0 8.1 ns CEBAn or CEABn to An or Bn tPHZ Output Disable Time tPLZ OEBAn or OEABn to An or Bn ns CEBAn or CEABn to An or Bn Note 8: Voltage Range 5.0 is 5.0V ±0.5V. AC Operating Requirements Symbol Parameter VCC TA = +25°C (V) CL = 50 pF (Note 9) tS Setup Time, HIGH or LOW TA = −40°C to +85°C CL = 50 pF Typ Units Guaranteed Minimum 5.0 3.0 3.0 ns 5.0 1.5 1.5 ns 5.0 4.0 4.0 ns An or Bn to LEBAn or LEABn tH Hold Time, HIGH or LOW An or Bn to LEBAn or LEABn tW Latch Enable, B to A Pulse Width, LOW Note 9: Voltage Range 5.0 is 5.0V ±0.5V 5 www.fairchildsemi.com 74ACTQ16543 Extended AC Electrical Characteristics TA = −40 to +85°C VCC = Com Symbol TA = −40 to +85°C CL = 50 pF VCC = Com 16 Outputs Switching CL = 250 pF Parameter (Note 10) Min Typ Units (Note 11) Max Min Max tPLH Propagation Delay 4.5 11.1 5.8 14.3 tPHL Transparent Mode 3.7 9.6 5.1 13.4 ns ns An to Bn or Bn to An tPLH Propagation Delay 4.3 11.3 6.2 16.3 tPHL LEBAn, LEABn to An, Bn 3.7 9.7 5.8 14.9 tPZH Output Enable Time 4.0 10.7 tPZL OEBAn or OEABn to An or Bn 4.3 11.3 (Note 12) ns (Note 13) ns CEBAn or CEABn to An or Bn tPHZ Output Disable Time 3.0 8.0 tPLZ OEBAn or OEABn to An or Bn 2.8 7.6 CEBAn or CEABn to An or Bn tOSHL Pin to Pin Skew (Note 14) HL Data to Output tOSLH Pin to Pin Skew (Note 14) LH Data to Output tOSHL Pin to Pin Skew (Note 14) Latch to Output tOSLH Pin to Pin Skew (Note 14) Latch to Output tOST Pin to Pin Skew (Note 14) Data to Output tOST Pin to Pin Skew (Note 14) Latch to Output 1.1 ns 1.4 ns 2.6 ns 1.0 ns 1.0 ns 2.2 ns Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all low-to-high, high-to-low, etc.). Note 11: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 12: 3-STATE delays are load dominated and have been excluded from the datasheet. Note 13: The Output Disable Time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH to LOW (tOSHL), LOW to HIGH (tOSLH), or any combination switching LOW to HIGH and/or HIGH to LOW (tOST). Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = 5.0V CPD Power Dissipation.Capacitance 95.0 pF VCC = 5.0V www.fairchildsemi.com 6 Conditions VOLP/VOLV and VOHP/VOHV: The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture • Measure VOLP and VOLVon the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case for active and enable transition. Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VILD and VIHD: 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. • Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. • First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. 4. • Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. VOHV and VOLP are measured with respect to ground reference. Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability on the measurements. FIGURE 1. Quiet Output Noise Voltage Waveforms 5. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. 6. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. FIGURE 2. Simultaneous Switching Test Circuit 7 www.fairchildsemi.com 74ACTQ16543 FACT Noise Characteristics 74ACTQ16543 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (SSOP), JEDEC MO-153, 6.1mm Wide Package Number MS56A www.fairchildsemi.com 8 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74ACTQ16543 16-Bit Registered Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)