FUJITSU MB15F04

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21342-1E
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F04
■
DESCRIPTION
The Fujitsu MB15F04 is a serial input Phase Locked Loop (PLL) frequency synthesizer with two 2.0GHz prescalers.
A 64/65 or a 128/129 for both 2.0GHz prescalers can be selected that enables pulse swallow operation.
The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 11.0mA typ. at a
supply voltage of 3.0V.
Furthermore, a super charger circuit is included to provide a fast tuning as well as low noise performance. As a result
of this, MB15F04 is ideally suitable for digital mobile communications.
■
FEATURES
• High frequency operation
•
•
•
•
•
•
•
■
RX synthesizer : 2.0 GHz max.
TX synthesizer : 2.0 GHz max.
Low power supply voltage: VCC = 2.7 to 3.6 V
Very Low power supply current : ICC = 11.0 mA typ. (Vcc = 3V)
Power saving function : IPSTX = IPSTX = 10 µA max.
Serial input 14–bit programmable reference divider: R = 5 to 16,383
Serial input 18–bit programmable divider consisting of:
- Binary 7–bit swallow counter: 0 to 127
- Binary 11–bit programmable counter: 5 to 2,047
On–chip high performance charge pump circuit and phase comparator, achieving high–speed lock–up and low
phase noise
Wide operating temperature: Ta = −40 to 85°C
PACKAGE
20-pin, Plastic SSOP
(FPT-20P-M03)
MB15F04
■
PIN ASSIGNMENT
(TOP VIEW)
GNDRX1
1
20
Clock
OSCIN
2
19
Data
GNDTX
3
18
LE
finTX
4
17
finRX
VccTX
5
16
VccRX
XfinTX
6
15
XfinRX
BSCTX
7
14
LD/fout
PSTX
8
13
PSRX
DoTX
9
12
DoRFX
BSTX
10
11
GNDRX2
(FPT-20P-M03)
2
MB15F04
■
PIN DESCRIPTIONS
Pin No.
Pin name
I/O
1
GNDRX1
–
Ground for RX–PLL section.
2
OSCin
I
The programmable reference divider input. TCXO should be connected with a
AC coupling capacitor.
3
GNDTX
–
Ground for the TX-PLL section.
4
finTX
I
Prescaler input pin for the TX-PLL.
The connection with VCO should be AC coupling.
5
VccTX
–
Power supply voltage input pin for the TX-PLL section.
When power is OFF, latched data of TX-PLL is cancelled.
6
XfinTX
I
Prescaler complimentary input for the TX-PLL section.
This pin should be grounded via a capacitor.
I
Analog switch output (BSTX) control for the TX section.
Always pull-down the BSCTX pin when not using BSTX. (Do not leave open.)
BSCTX = “H”; outputs the DoTX state.
BSCTX = “L” ; goes to high impedance.
7
BSCTX
Descriptions
8
PSTX
I
Power saving mode control for the TX-PLL section. This pin must be set
at “L” Power-ON. (Open is prohibited.)
PSTX = “H” ; Normal mode
PSTX= “L” ; Power saving mode
9
DoTX
O
Charge pump output for the TX-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
10
BSTX
O
Analog switch output for the TX selection.
11
GNDRX2
–
Ground 2 for the RX section.
12
DoRX
O
Charge pump output for the RX-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
13
PSRX
I
Power saving mode control for the RX-PLL section. This pin must be set
at “L” Power-ON. (Open is prohibited.)
PSRX = “H” ; Normal mode
PSRX = “L” ; Power saving mode
14
LD/fout
O
Lock detect signal output (LD) / phase comparator monitoring output (fout)
The output signal is selected by a LDS bit in a serial data.
LDS bit = “H” ; outputs fout signal
LDS bit = “L” ; outputs LD signal
15
XfinRX
I
Prescaler complimentary input for the RX-PLL section.
This pin should be grounded via a capacitor.
16
VccRX
–
Power supply voltage input pin for the RX-PLL section.
When power is OFF, latched data of RX-PLL is cancelled.
17
finRX
I
Prescaler input pin for the RX-PLL.
The connection with VCO should be AC coupling.
18
LE
I
Load enable signal input (with the schmitt trigger circuit.)
When LE is “H”, data in the shift register is transferred to the corresponding
latch according to the control bit in a serial data.
19
Data
I
Serial data input (with the schmitt trigger circuit.)
A data is transferred to the corresponding latch (TX-ref counter, TX-Prog.
counter, RX-ref. counter, RX-prog. counter) according to the control bit in a
serial data.
20
Clock
I
Clock input for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a rising edge of the clock.
3
MB15F04
■
BLOCK DIAGRAM
8
PSTX
3-bit latch
Intermittent
mode
control
LDS SWTX FCTX
(TX–PLL)
7-bit latch
VccTX
GNDTX
5
3
11-bit latch
Binary 11-bit
Binary 7-bit
swallow counter programmable
(TX–PLL)
counter(TX–PLL)
fpTX
Phase
comp.
Charge Super
pump charger
(TX–PLL)
(TX–PLL)
9 DoTX
Prescaler
finTX 4
XfinTX 6
(TX–PLL)
64/65,
128/129
2-bit latch
T1
T2
Lock
Det.
14-bit latch
Binary 14–bit programmable ref.
counter(TX–PLL)
10 BSTX
Analog
switch
(TX–PLL)
7 BSCTX
LDTX
frTX
2
OSCin
AND
Selector
LD
frTX
frRX
fpTX
fpRX
OR
frRX
T1
T2
Binary 14-bit programmable ref.
counter(RX–PLL)
LDRX
2-bit latch
finRX 17
15
XfinRF
Lock
Det.
(RX–PLL)
Prescaler
(RX–PLL)
64/65,
128/129
LDS SWRX FCRX
PSRF 13
14-bit latch
Intermittent
mode
control
LE 18
Schmitt
circuit
Data 19
Schmitt
circuit
Clock 20
Schmitt
circuit
Binary 7-bit
swallow counter
(RX–PLL)
Binary 11-bit
programmable
counter(RX–PLL)
Phase
comp.
3-bit latch
7-bit latch
Charge Super
pump
(RX–PLL) charger
(RX–PLL)
fpRX
(RX–PLL)
11-bit latch
Latch selector
C
N
1
C
N
2
23-bit shift
register
16
VCCRX
4
14 LD/fout
1
GNDRX1
11
GNDRX2
12 DoRX
MB15F04
■
ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter
Symbol
Rating
Unit
VCC
–0.5 to +4.0
V
Input voltage
VI
–0.5 to VCC +0.5
V
Output voltage
VO
–0.5 to VCC +0.5
V
Output current
IO
–10 to +10
mA
TSTG
–55 to +125
°C
Power supply voltage
Storage temperature
Remark
WARNING: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
■
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Note
3.6
V
VCCTX = VCCRX
–
VCC
V
–
+85
°C
Min
Typ
Max
VCC
2.7
3.0
Input voltage
Vi
GND
Operating temperature
Ta
–40
Power supply voltage
Handling Precautions
• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are
properly grounded. Cover workbenches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.
5
MB15F04
■
ELECTRICAL CHARACTERISTICS
(VCC = 2.7 V to 3.6 V, Ta = –40°C to +85°C)
Parameter
finTX
finRX
OSCin
ICCTX
ICCRX
IPSTX
IPSRX
finTX*3
finRX*3
fOSC
finTX
VfinTX
finRX
VfinRX
OSCin
Data,
Clock,
LE
PSTX,
PSRX,
BSCTX
Data,
Clock,
LE,
PSTX,
PSRX,
BSCTX
VOSC
VIH
Power supply current*1
Power saving current*2
Operating
frequency
Input sensitivity
Input voltage
Input current
OSCin
LD/fout
Output voltage
High impedance
cutoff current
Output current
6
VIL
TX
RX
PSTX =“L”
PSTX/RX =“L”
TX
RX
–
TX–PLL, 50Ω load
(See TEST CIRCUIT)
RX–PLL, 50Ω load
(See TEST CIRCUIT)
–
Schmitt trigger input
Schmitt trigger input
Min.
–
–
–
–
100
100
3
Value
Typ.
5.0
6.0
0.1*2
0.1*2
–
–
–
Max.
–
–
10
10
2000
2000
40
–10
–
+2
dBm
–10
–
+2
dBm
500
VCCx0.7+0.4
–
–
VCC
–
mVp-p
–
–
VCCx0.3–0.4
Unit
mA
µA
MHz
V
–
VCCx0.7
–
–
VIL
–
–
–
VCCx0.3
IIH*4
–
–1.0
IL*4
–
–1.0
–
+1.0
IIH
IIL*4
VOH
–
–
VCC = 3.0V, IOH = –1.0 mA
VCC = 3.0V, IOL = 1.0 mA
VCC = 3.0V,
IDOH = –1.0 mA
VCC = 3.0V,
IDOL = 1.0 mA
VCC = 3.0V,
VOFF = GND to VCC
VCC = 3.0V
VCC = 3.0V
VCC = 3.0V,
VDOH = 2.0V,
Ta = +25°C
VCC = 3.0V,
VDOL = 1.0V,
Ta = +25°C
0
–100
VCC–0.4
–
–
–
–
–
+100
0
–
0.4
VCC–0.4
–
–
–
–
0.4
–
–
1.1
µA
–
1.0
–
–
–1.0
–
mA
–11
–
–6
V
+1.0
µA
I
VOL
VDOH
DoTX/RX,
BSTX
IOFF
LD/fout
IOH*4
IOL
DoIX,
DoRX,
BSTX
Condition
VIH
DoIF,
DoRF,
BSTX
Analog switch on BSTX
resistance
*1:
*2:
*3:
*4:
Symbol
VDOL
IDOH*4
IDOL
RON
–
µA
V
V
mA
8
–
15
–
50
–
Ω
Conditions ; fin TX/RX = 2000 MHz, fOSC = 12 MHz, VCCTX/RF = 3.0 V, Ta = +25°C, in locking state.
Conditions ; VCCTX/RX = 3.0 V, fOSC = 12.8 MHz, Ta = +25°C
AC coupling. The minimum operating frequency is specified with a coupling capacitor 1000 pF connected.
The symbol “–” (minus) means direction of current flow.
MB15F04
■
FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
fVCO = {(P x N) + A} x fOSC ÷ R
fVCO:
P:
N:
A:
fOSC:
R:
(A < N)
Output frequency of external voltage controlled ocillator (VCO)
Preset divide ratio of dual modulus prescaler (64 or 128)
Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
Preset divide ratio of binary 7-bit swallow counter (0≤ A ≤ 127)
Reference oscillation frequency
Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of TX/RX–PLL
sections, programmable reference dividers of TX/RX PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On rising edge of clock, one bit of serial data is transferred into the shift register. When load enable signal is high,
the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.
Table1. Control Bit
Control bit
Destination of serial data
CN1
CN2
L
L
The programmable reference counter for the TX-PLL.
H
L
The programmable reference counter for the RX-PLL.
L
H
The programmable counter and the swallow counter for the TX-PLL
H
H
The programmable counter and the swallow counter for the RX-PLL
Shift Register Configuration
Programmable Reference Counter
LSB
MSB
Data Flow
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
C
N
1
C
N
2
T
1
T
2
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
R
14
X
X
X
X
X
CNT1, 2
: Control bit
R1 to R14 : Divide ratio setting bits for the programmable reference counter (5 to 16,383)
T1, 2
: Test purpose bit
×
: Dummy bit (set to either 0 or 1)
NOTE: Data input with MSB first.
[Table. 1]
[Table. 2]
[Table. 3]
7
MB15F04
Programmable Counter
LSB
MSB
Data Flow
1
2
3
C
N
1
C
N
2
L
D
S
5
4
S
F
W
C
TX/ TX/
RX RX
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
CNT1, 2
N1 to N14
: Control bit
: Divide ratio setting bits for the TX section or RX section programmable counter
(5 to 2,047)
A1 to A7
: Divide ratio setting bits for the TX section or RX section swallow counter
(0 to 127)
SWTX/RX
: Divide ratio setting bit for the prescaler (TX section : SWTX, RX section: SWRX)
FCTX/RX
: Phase control bit for the phase detector (TX section : FCTX, RX section : FCRX)
LDS
: LD/fout signal select bit
NOTE: Data input with MSB first.
[Table. 1]
[Table. 4]
[Table. 5]
[Table. 6]
[Table. 7]
[Table. 8]
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
ratio
(R)
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
5
0
0
0
0
0
0
0
0
0
0
0
1
0
1
6
0
0
0
0
0
0
0
0
0
0
0
1
1
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 5 is prohibited.
Table.3 Test Purpose Bit Setting
8
T
1
T
2
LD/fout pin state
L
L
Outputs frTX
H
L
Outputs frRX
L
H
Outputs fpTX
H
H
Outputs fpRX
MB15F04
Table.4 Binary 11-bit Programmable Counter Data Setting
Divide
ratio
(N)
N
11
N
10
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
5
0
0
0
0
0
0
0
0
1
0
1
6
0
0
0
0
0
0
0
0
1
1
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
2047
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 5 is prohibited.
Table.5 Binary 7-bit Swallow Counter Data Setting
Divide
ratio
(A)
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
127
1
1
1
1
1
1
1
Note: Divide ratio (A) range = 0 to 127
Table. 6 Prescaler Data Setting
Prescaler
divide ratio
SW = “H”
SW = “L”
TX-PLL
64/65
128/129
RX-PLL
64/65
128/129
9
MB15F04
Table. 7 Phase Comparator Phase Switching Data Setting
FC = H
FC = L
fr > fp
H
L
fr = fp
Z
Z
fr < fp
L
H
VCO polarity
(1)
(2)
(1)
VCO Output
Frequency
Note: • Z = High–impedance
• Depending upon the VCO and LPF polarity,
FC bit should be set.
(2)
VCO Output Voltage
Table. 8 LD/fout Output Select Data Setting
LDS
LD/fout output signal
H
fout (frTX/RX, fpTX/RX) signals
L
LD signal
Serial Data Input Timing
2nd. Data
1st. Data
Control bit
Data
Invalid data
LSB
MSB
Clock
t1
LE
t2
t5
t0
t4
t3
t6
On rising edge of the clock, one bit of the data is transferred into the shift register.
Parameter
10
Min
Typ
Max
Unit
t1
20
–
–
ns
t2
20
–
–
t3
30
–
t4
20
–
Parameter
Min
Typ
Max
Unit
t5
30
–
–
ns
ns
t6
100
–
–
ns
–
ns
t7
100
–
–
ns
–
ns
MB15F04
■
PHASE DETECTOR OUTPUT WAVEFORM
frTX/RX
fpTX/RX
tWU
tWL
LD
(FC bit = High)
H
DoTX/RX
Z
L
(FC bit = Low)
DoTX/RX
Z
LD Output Logic Table
RX–PLL section
LD output
Locking state / Power saving state
Locking state / Power saving state
H
Locking state / Power saving state
Unlocking state
L
Unlocking state
Locking state / Power saving state
L
Unlocking state
Unlocking state
L
TX–PLL section
Note: • Phase error detection range = −2π to +2π
• Pulses on DoTX/RX signals are output to prevent dead zone.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCin input frequency as follows.
tWU > 8/fosc: i.e. tWU > 625ns when foscin = 12.8 MHz
tWL < 16/fosc: i.e. tWL < 1250ns when foscin = 12.8 MHz
11
MB15F04
■
POWER SAVING MODE (Intermittent Mode Control Circuit)
Setting a PSTX(RX) pin to Low, TX-PLL (RX-PLL) enters into power saving mode resultant current consumption can
be limited to 0.1 µA (typ.). Setting PS pin to High, power saving mode is released so that the device works normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from stand by mode.
In general, the power consumption can be saved by the intermittent operation that powering down or waking up the
synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal is
unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency (fp)
and may in the worst case take longer time for lock up of the loop.
To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector
during power up. Thus keeping the loop locked.
PS pin must be set “L” at Power-ON.
Allow 1 µs after frequency stabilization on power-up for exiting the power saving mode (PS: L to H)
Serial data can be entered during the power saving mode.
During the power saving mode, the corresponding section except for indispensable circuit for the power saving
function stops working, then current consumption is reduced to 10µA per one PLL section.
At that time, the Do and LD become the same state as when a loop is locking. That is, the Do becomes high
impedance.
A VCO control voltage is naturally kept at the locking voltage which defined by a LPF’s time constant. As a result
of this, VCO’s frequency is kept at the locking frequency.
12
PSTX
PSRX
TX-PLL counters
RX-PLL counters
OSC input buffer
L
L
OFF
OFF
OFF
H
L
ON
OFF
ON
L
H
OFF
ON
ON
H
H
ON
ON
ON
MB15F04
■
ANALOG SWITCH (BSCTX Pin)
The analog switch is set on or off by the BSCTX input. When the switch is on, the output of the charge pump (DoTX)
is output from the BSTX pin. (The pin goes to high impedance when the switch is off.)
Analog switch
BSCTX
ON
H
OFF
L
As in the example shown in the figure below, placing the analog switch midway through the LPF (LPF1 + LPF2)
allows the LPF time constant to be reduced during PLL channel switching so as to speed up the lock up time.
DoTX
CHP
LPF1
Analog
swtch
LPF2
VCO
BSTX
BSCTX
13
MB15F04
■
TYPICAL CHARACTERISTICS
Input sensivity of FIN (RX) vs. Input frequency
10
Ta = +25°C
5
Vfin RX (dBm)
0
–5
SPEC
–10
–15
–20
–25
V CC=2.7 V
V CC=3.0 V
V CC=3.6 V
–30
–35
–40
0
1000
2000
3000
4000
fin (MHz)
Input sensivity of FIN (TX) vs. Input frequency
10
Ta = +25°C
5
0
SPEC
Vfin TX (dBm)
–5
–10
–15
–20
–25
V CC=2.7 V
V CC=3.0 V
V CC=3.6 V
–30
–35
–40
0
1000
2000
3000
4000
fin (MHz)
Input sensivity of OSC vs. Input frequency
10
Ta = +25°C
SPEC
0
VOSC (dBm0)
–10
–20
–30
–40
V CC=2.7 V
V CC=3.0 V
V CC=3.6 V
–50
–60
0 10
50
100
fOSC (MHz)
(Continued)
14
MB15F04
RX Do output current
Conditions: Ta = +25°C
IDOH – VDOH
V CC = 3 V
Ta = +25°C
V DOH (V)
5.000
.0000
.0000
–25.00
I DOH (mA)
IDOL – VDOL
5.000
V DOL (V)
V CC = 3 V
Ta = +25°C
.0000
.0000
25.00
I DOL (mA)
(Continued)
15
MB15F04
TX Do output current
Conditions: Ta = +25°C
IDOH – VDOH
V CC = 3 V
Ta = +25°C
V DOH (V)
5.000
.0000
.0000
–25.00
I DOH (mA)
IDOL – VDOL
V CC = 3 V
Ta = +25°C
V DOL (V)
5.000
.0000
.0000
25.00
I DOL (mA)
(Continued)
16
MB15F04
Input impedance
fin
4
1;
9.7188 Ω
–67.062 Ω
500 MHz
2;
8.2324 Ω
–17.395 Ω
1 GHz
3;
11.075 Ω
6.2979 Ω
1.5 GHz
4;
12.635 Ω
23.558 Ω
2 GHz
1;
19.266 Ω
–132.09 Ω
500 MHz
2;
9.6855 Ω
–49.215 Ω
1 GHz
3;
11.299 Ω
–13.364 Ω
1.5 GHz
4;
12.398 Ω
10.659 Ω
2 GHz
3
finRX Pin
2
1
START 100.000 000 MHz
STOP 1 500.000 000 MHz
fin
finTX Pin
4
3
1
2
START 100.000 000 MHz
STOP 1 500.000 000 MHz
(Continued)
17
MB15F04
(Continued)
Input impedance
OSC IN
1;
28.862 k Ω
–33.732 k Ω
1 MHz
2;
77 Ω
–4.5602 k Ω
12.8 MHz
3;
114.63 Ω
–2.5294 k Ω
23 MHz
3 4;
112.13 Ω
–1.9848 k Ω
30 MHz
OSCin Pin
2
4
START .500 000 MHz
18
STOP 100.000 000 MHz
MB15F04
■
TEST CIRCUIT (Prescaler Input/Programmable Reference Divider Input Sensitivity Test)
1000pF
VccTX
S.G
1000p
0.1µF
S.G
50Ω
1000pF
GND
10
50Ω
9
8
7
6
5
4
3
17
18
2
1
MB15F04
11
12
13
14
15
16
19
20
S.G
1000pF
50Ω
VccRX
Oscilloscope
1000 pF
Controller (sets
the divide ratios)
0.1µF
19
MB15F04
■
APPLICATION EXAMPLE
Low pass
filter
VCO
Output
from controller
3V
1000 pF
0.1µF
1000 pF
20
19
18
17
16
15
Lock Det.
14
13
12
11
7
8
9
10
MB15F04
1
2
3
4
5
6
1000 pF
3V
0.1µF
TCXO
1000 pF
1000 pF
Output
VCO
Low pass
filter
Clock, Data, LE: Schmitt trigger circuit is provided (insert a pull-down or pull-up resistor to prevent oscillation
when open-circuited in the input).
BSCTX
: Always pull-down the BSCTX pin when not using the analog switch output (BSTX). (Do not
leave the pin open.)
20
MB15F04
■
ORDERING INFORMATION
Part number
Package
MB15F04 PFV
20pin, Plastic SSOP
(FPT-20P-M03)
Remarks
21
MB15F04
■
PACKAGE DIMENSION
* : These dimensions do not include resin protrusion.
20 pins, Plastic SSOP
(FPT-20P-M03)
+0.20
* 6.50±0.10(.256±.004)
1.25 –0.10
+.008
.049 –.004
0.10(.004)
INDEX
*4.40±0.10 6.40±0.20
(.173±.004) (.252±.008)
0.65±0.12
(.0256±.0047)
5.85(.230)REF
C
22
1994 FUJITSU LIMITED F20012S-2C-4
+0.10
0.22 –0.05
+.004
.009 –.002
"A"
5.40(.213)
NOM
+0.05
0.15 –0.02
+.002
.006 –.001
Details of "A" part
0.10±0.10(.004±.004)
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
Dimensions in mm (inches)
MB15F04
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3763
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are included as a
means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given.
The information contained in this document has been carefully
checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies.
The information contained in this document does not convey any
license under the copyrights, patent rights or trademarks claimed
and owned by Fujitsu.
Fujitsu reserves the right to change products or specifications
without notice.
No part of this publication may be copied or reproduced in any
form or by any means, or transferred to any third party without
prior written consent of Fujitsu.
The information contained in this document are not intended for
use with equipments which require extremely high reliability
such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support.
F9703
 FUJITSU LIMITED Printed in Japan
23