FAIRCHILD 74F403

Revised May 1999
74F403A
First-In First-Out (FIFO) Buffer Memory
General Description
Features
The 74F403A is an expandable fall-through type highspeed First-In First-Out (FIFO) Buffer Memory optimized
for high-speed disk or tape controllers and communication
buffer applications. It is organized as 16-words by 4-bits
and may be expanded to any number of words or any number of bits in multiples of four. Data may be entered or
extracted asynchronously in serial or parallel, allowing economical implementation of buffer memories.
■ Serial or parallel input
The 74F403A has 3-STATE outputs which provide added
versatility and is fully compatible with all TTL families.
■ Guaranteed 4000V minimum ESD protection
■ Serial or parallel output
■ Expandable without external logic
■ 3-STATE outputs
■ Fully compatible with all TTL families
■ Slim 24-pin package
■ 9403A replacement
Ordering Code:
Order Number
74F403ASPC
Package Number
N24C
Package Description
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
© 1999 Fairchild Semiconductor Corporation
Logic Symbol
DS009536.prf
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74F403A First-In First-Out (FIFO) Buffer Memory
January 1989
74F403A
Unit Loading/Fan Out:
Block Diagram
See Section 2 for U.L. definitions
Pin
U.L.
Input IIH/IIL
Description
HIGH/LOW Output IOH/IOL
Names
D0 − D3 Parallel Data Inputs
1.0/0.667
20 µA/400 µA
DS
Serial Data Input
1.0/0.667
20 µA/400 µA
PL
Parallel Load Input
1.0/0.667
20 µA/400 µA
CPSI
Serial Input Clock
1.0/0.667
20 µA/400 µA
IES
Serial Input Enable
1.0/0.667
20 µA/400 µA
TTS
Transfer to Stack Input
1.0/0.667
20 µA/400 µA
OES
Serial Output Enable
1.0/0.667
20 µA/400 µA
TOS
Transfer Out Serial
1.0/0.667
20 µA/400 µA
TOP
Transfer Out Parallel
1.0/0.667
20 µA/400 µA
MR
Master Reset
1.0/0.667
20 µA/400 µA
OE
Output Enable
1.0/0.667
20 µA/400 µA
CPSO
Serial Output Clock
1.0/0.667
20 µA/400 µA
Q0 − Q3 Parallel Data Outputs
285/26.7
5.7 mA/16 mA
QS
Serial Data Output
285/26.7
5.7 mA/16 mA
IRF
Input Register Full
20/13.3
−400 µA/8 mA
ORE
Output Register Empty
20/13.3
−400 µA/8 mA
Functional Description
the F3 flip-flop and resetting the other flip-flops. The Q output of the last flip-flop (FC) is brought out as the “Input
Register Full” output (IRF). After initialization this output is
HIGH.
Parallel Entry— A HIGH on the PL input loads the D0-D3
inputs into the F0-F3 flip-flops and sets the FC flip-flop. This
forces the IRF output LOW indicating that the input register
is full. During parallel entry, the CPSI input must be LOW. If
parallel expansion is not being implemented, IES must be
LOW to establish row mastership (see Expansion section).
Serial Entry— Data on the DS input is serially entered into
the F3, F2, F1, F0, FC shift register on each HIGH-to-LOW
transition of the CPSI clock input, provided IES and PL are
LOW.
As shown in the Block Diagram the 74F403A consists of
three sections:
1. An Input register with parallel and serial data inputs as
well as control inputs and outputs for input handshaking and expansion.
2. A 4-bit wide, 14-word deep fall-through stack with selfcontained control logic.
3. An Output Register with parallel and serial data outputs
as well as control inputs and outputs for output handshaking and expansion.
Since these three sections operate asynchronously and
almost independently, they will be described separately
below.
INPUT REGISTER (DATA ENTRY)
The Input Register can receive data in either bit-serial or in
4-bit parallel form. It stores this data until it is sent to the
fall-through stack and generates the necessary status and
control signals.
After the fourth clock transition, the four data bits are
located in the four flip-flops, F0-F3. The FC flip-flop is set,
forcing the IRF output LOW and internally inhibiting CPSI
clock pulses from affecting the register, Figure 2 illustrates
the final positions in a 74F403A resulting from a 64-bit
serial bit train. B0 is the first bit, B63 the last bit.
Figure 1 is a conceptual logic diagram of the input section.
As described later, this 5-bit register is initialized by setting
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2
74F403A
FIGURE 1. Conceptual Input Section
Transfer to the Stack— The outputs of Flip-Flops F0-F3
feed the stack. A LOW level on the TTS input initiates a
“fall-through” action. If the top location of the stack is
empty, data is loaded into the stack and the input register is
re-initialized. Note that this initialization is postponed until
PL is LOW again. Thus, automatic FIFO action is achieved
by connecting the IRF output to the TTS input.
An RS Flip-Flop (the Request Initialization Flip-Flop shown
in Figure 10) in the control section records the fact that
data has been transferred to the stack. This prevents multiple entry of the same word into the stack despite the fact
the IRF and TTS may still be LOW. The Request Initialization Flip-Flop is not cleared until PL goes LOW. Once in the
stack, data falls through the stack automatically, pausing
only when it is necessary to wait for an empty next location.
In the 74F403A as in most modern FIFO designs, the MR
input only initializes the stack control section and does not
clear the data.
OUTPUT REGISTER (DATA EXTRACTION)
FIGURE 2. Final Positions in a 74F403A
Resulting from a 64-Bit Serial Train
The Output Register receives 4-bit data words from the
bottom stack location, stores it and outputs data on a 3STATE 4-bit parallel data bus or on a 3-STATE serial data
bus. The output section generates and receives the necessary status and control signals. Figure 3 is a conceptual
logic diagram of the output section.
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74F403A
FIGURE 3. Conceptual Output Section
transferred twice. If TOP goes HIGH and returns to LOW
before data is available from the stack, ORE remains LOW
indicating that there is no valid data at the outputs.
Parallel Data Extraction— When the FIFO is empty after
a LOW pulse is applied to MR, the Output Register Empty
(ORE) output is LOW. After data has been entered into the
FIFO and has fallen through to the bottom stack location, it
is transferred into the Output Register provided the “Transfer Out Parallel” (TOP) input is HIGH. As a result of the
data transfer ORE goes HIGH, indicating valid data on the
data outputs (provided the 3-STATE buffer is enabled).
TOP can now be used to clock out the next word. When
TOP goes LOW, ORE will go LOW indicating that the output data has been extracted, but the data itself remains on
the output bus until the next HIGH level at TOP permits the
transfer of the next word (if available) into the Output Register. During parallel data extraction CPSO should be LOW.
TOS should be grounded for single slice operation or connected to the appropriate ORE for expanded operation
(see Expansion section).
Serial Data Extraction— When the FIFO is empty after a
LOW pulse is applied to MR, the Output Register empty
(ORE) output is LOW. After data has been entered into the
FIFO and has fallen through to the bottom stack location, it
is transferred into the Output Register provided TOS is
LOW and TOP is HIGH. As a result of the data transfer
ORE goes HIGH indicating valid data in the register. The 3STATE Serial Data Output, QS, is automatically enabled
and puts the first data bit on the output bus. Data is serially
shifted out on the HIGH-to-LOW transition of CPSO. To
prevent false shifting, CPSO should be LOW when the new
word is being loaded into the Output Register. The fourth
transition empties the shift register, forces ORE output
LOW and disables the serial output, QS (refer to Figure 3).
For serial operation the ORE output may be tied to the TOS
input, requesting a new word from the stack as soon as the
previous one has been shifted out.
TOP is not edge triggered. Therefore, if TOP goes HIGH
before data is available from the stack, but data does
become available before TOP goes LOW again, that data
will be transferred into the Output Register. However, internal control circuitry prevents the same data from being
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4
Vertical Expansion— The 74F403A may be vertically
expanded to store more words without external parts. The
interconnection is necessary to form a 46-word by 4-bit
FIFO are shown in Figure 4. Using the same technique,
and FIFO of (15n + 1)-words by 4-bits can be constructed,
where n is the number of devices. Note that expansion
does not sacrifice any of the 74F403A’s flexibility for serial/
parallel input and output.
Interlocking Circuitry— Most conventional FIFO designs
provide status signals analogous to IRF and ORE. However, when these devices are operated in arrays, variations
in unit to unit operating speed require external gating to
assure all devices have completed an operation. The
74F403A incorporates simple but effective “master/slave”
interlocking circuitry to eliminate the need for external gating.
In the 74F403A array of Figure 6 devices 1 and 5 are
defined as “row masters” and the other devices are slaves
to the master in their row. No slave in a given row will initialize its Input Register until it has received LOW on its IES
input from a row master or a slave of higher priority.
In a similar fashion, the ORE outputs of slaves will not go
HIGH until their OES inputs have gone HIGH.This interlocking scheme ensures that new input data may be
accepted by the array when the IRF output of the final
slave in that row goes HIGH and that output data for the
array may be extracted when the ORE of the final slave in
the output row goes HIGH.
The row master is established by connecting its IES input
to ground while a slave receives its IES input from the IRF
output of the next higher priority device. When an array of
74F403A FIFOs is initialized with a LOW on the MR inputs
of all devices, the IRF outputs of all devices will be HIGH.
Thus, only the row master receives a LOW on the IES input
during initialization. Figure 10 is a conceptual logic diagram
of the internal circuitry which determines master/slave
operation. Whenever MR and IES are LOW, the Master
Latch is set. Whenever TTS goes LOW the Request Initialization Flip-Flop will be set. If the Master Latch is HIGH, the
Input Register will be immediately initialized and the
Request Initialization Flip-Flop reset. If the Master Latch is
reset, the Input Register is not initialized until IES goes
LOW. In array operation, activating the TTS initiates a ripple input register initialization from the row master to the
last slave.
FIGURE 4. A Vertical Expansion Scheme
A similar operation takes place for the output register.
Either a TOS or TOP input initiates a load-from-stack operation and sets the ORE Request Flip-Flop. If the Master
Latch is set, the last Output Register Flip-Flop is set and
ORE goes HIGH. If the Master Latch is reset, the ORE output will be LOW until an OES input is received.
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74F403A
Horizontal and Vertical Expansion— The 74F403A can
be expanded in both the horizontal and vertical directions
without any external parts and without sacrificing any of its
FIFO’s flexibility for serial/parallel input and output. The
interconnections necessary to form a 31-word by 16-bit
FIFO are shown in Figure 6. Using the same technique,
any FIFO of (15m + 1)-words by (4n)-bits can be constructed, where m is the number of devices in a column
and n is the number of devices in a row. Figure 7 and Figure 8 show the timing diagrams for serial data entry and
extraction for the 31-word by 16-bit FIFO shown in Figure
6. The final position of data after serial insertion of 496 bits
into the FIFO array of Figure 6 is shown in Figure 9.
EXPANSION
74F403A
FIGURE 5. A Horizontal Expansion Scheme
FIGURE 6. A 31 x 16 FIFO Array
GRAPHIC 00953610
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6
74F403A
FIGURE 7. Serial Data Entry for Array of Figure 6
FIGURE 8. Serial Data Extraction for Array of Figure 6
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74F403A
FIGURE 9. Final Position of a 496-Bit Serial Input
FIGURE 10. Conceptual Diagram, Interlocking Circuitry
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8
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
−55°C to +125°C
Free Air Ambient Temperature
Junction Temperature under Bias
−55°C to +175°C
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
In HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Current Applied to Output
in LOW State (Max)
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
twice the rated IOL (mA)
ESD Last Passing Voltage (Min)
4000V
DC Electrical Characteristics
Symbol
Parameter
Min
Type
Max
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
−1.5
V
VOH
Output HIGH
10% VCC
2.5
Voltage
10% VCC
2.5
5% VCC
2.7
5% VCC
2.7
VOL
2.0
Units
VIH
V
0.5
Voltage
10% VCC
0.5
Input HIGH Current
Input HIGH Current
Breakdown Test
Recognized as a LOW Signal
Min
IIN = −18 mA
Min
IOH = −5.7 mA (Qn, Qs)
IOH = −400 µA (IRF, ORE)
IOH = −5.7 mA (Qn, Qs)
10% VCC
IBVI
Conditions
Recognized as a HIGH Signal
IOH = −400 µA (IRF, ORE)
Output LOW
IIH
VCC
V
V
Min
IOL = 8 mA (IRF, ORE)
IOL = 16 mA (Qn, Qs)
20
µA
Max
VIN = 2.7V
100
µA
Max
VIN = 7.0V
VIN = 0.5V
IIL
Input LOW Current
−0.4
mA
Max
IOZH
Output Leakage Current
50
µA
Max
VOUT = 2.7V
IOZL
Output Leakage Current
−50
µA
Max
VOUT = 0.5V
IOS
Output Short-Circuit Current
−130
mA
Max
VOUT = 0V
ICEX
Output HIGH Leakage Current
250
µA
Max
VOUT = VCC
ICCL
Power Supply Current
170
mA
Max
V0 = LOW
−20
9
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74F403A
Absolute Maximum Ratings(Note 1)
74F403A
AC Electrical Characteristics
Symbol
tPHL
Parameter
TA = +25°C
TA = 0° to +70°C
VCC = +5.0V
VCC = +5.0V
CL = 50 pF
CL = 50 pF
Min
Max
Min
Max
7.5
14.0
7.0
15.0
Figure
Number
ns
Figure 11
Figure 12
ns
Figure 13
Figure 14
Propagation Delay,
Negative-Going
CPSI to IRF Output
tPLH
Units
Propagation Delay,
Negative-Going
11.0
20.5
10.0
22.5
TTS to IRF
tPLH
Propagation Delay,
8.5
17.0
7.5
18.5
tPHL
Negative-Going
8.0
14.5
7.0
15.5
CPSO to QS Output
tPLH
Propagation Delay,
10.0
18.0
9.0
20.0
tPHL
Positive-Going
8.5
15.5
8.0
16.5
ns
Figure 15
9.5
17.5
9.0
19.0
ns
Figure 13
Figure 14
8.0
15.0
7.5
16.5
ns
Figure 15
ns
Figure 13
Figure 14
ns
Figure 17
Figure 18
TOP to Outputs Q0-Q3
tPHL
Propagation Delay,
Negative-Going
CPSO to ORE
tPHL
Propagation Delay,
Negative-Going
TOP to ORE
tPLH
Propagation Delay,
Positive-Going
12.5
22.0
11.5
25.0
12.5
22.0
11.0
25.0
7.0
13.0
6.5
14.0
TOP or ORE
tPLH
Propagation Delay,
Negative-Going
TOS to Positive Going ORE
tPHL
Propagation Delay,
Positive-Going
PL to Negative-Going IRF
tPLH
Propagation Delay,
Negative-Going
9.5
17.0
8.5
19.5
10.0
18.0
9.0
20.5
ns
8.5
15.5
7.5
17.5
ns
8.0
15.0
7.5
17.0
ns
9.0
16.0
8.0
17.5
ns
8.0
PL to Positive-Going IRF
tPLH
Propagation Delay,
Apostatize-Going
OES to ORE
tPLH
Propagation Delay,
Positive-Going
IES to Positive-Going IRF
tPLH
Propagation Delay,
MR to IRF
tPHL
Propagation Delay,
MR to ORE
tPZH
Propagation Delay,
2.5
6.5
2.0
tPZL
OE to Q0, Q1, Q2, Q3
2.5
7.5
2.0
8.5
tPHZ
Propagation Delay,
2.5
6.5
2.0
8.0
tPLZ
OE to Q0, Q1, Q2, Q3
2.5
7.5
2.0
8.0
tPZH
Propagation Delay,
5.5
12.0
5.0
15.0
tPZL
Negative-Going
5.5
14.0
5.0
15.0
OES to QS
tPHZ
Propagation Delay,
5.5
12.0
5.0
14.0
tPLZ
Negative-Going
5.5
14.5
5.0
16.0
OES to QS
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10
ns
ns
Figure 18
Symbol
(Continued)
Parameter
TA = +25°C
TA = 0° to +70°C
VCC = +5.0V
VCC = +5.0V
CL = 50 pF
CL = 50 pF
Min
Max
Min
Max
tPZH
Turn On Time
8.5
21.0
8.0
24.0
tPZL
TOS to QS
8.5
20.0
8.0
21.0
tDFT
Fall Through Time
45.0
80.0
35.0
95.0
tAP
Parallel Appearance Time,
−10.0
−1.0
−10.0
−1.0
−10.0
2.0
−10.0
20
ORE to Q0-Q3
tAS
Serial Appearance Time,
ORE to QS
74F403A
AC Electrical Characteristics
Units
Figure
Number
ns
ns
Figure 16
ns
AC Operating Requirements
Symbol
Parameter
TA = +25°C
TA = 0°C to +70°C
VCC = +5.0V
VCC = +5.0V
Min
tS(H)
Max
Min
Units
Figure
Number
ns
Figure 11
Figure 12
Max
Set-up Time HIGH or LOW
1.0
1.0
tS(L)
DS to Negative CPSI
1.0
1.0
tH(H)
Hold Time, HIGH or LOW
3.5
3.5
tH(L)
DS to CPSI
3.5
3.5
tS(L)
Set-up Time, LOW
0
0
ns
Figure 11
Figure 12
Figure 17
Figure 18
0
0
ns
Figure 13
Figure 14
3.0
4.0
ns
Figure 12
14.0
15.5
ns
Figure 12
0
TTS to IRF
Serial or Parallel Mode
tS(L)
Set-up Time, LOW
Negative-Going ORE to
Negative-Going TOS
tS(L)
Set-up Time, LOW
Negative-Going IES to CPSI
tS(L)
Set-up Time, LOW
Negative-Going TTS to CPSI
tS(H)
Set-up Time, HIGH or LOW
0
tS(L)
Parallel Inputs to PL
0
0
tH(H)
Hold Time, HIGH or LOW
2.0
2.5
tH(L)
Parallel Inputs to PL
2.0
2.5
tW(H)
CPSI Pulse Width
5.0
6.0
tW(L)
HIGH or LOW
3.0
5.0
tW(H)
PL Pulse Width, HIGH
4.0
Serial or Parallel Mode
tW(L)
tW(H)
tW(L)
ns
ns
Figure 11
Figure 12
5.0
ns
Figure 17
Figure 18
3.5
4.0
ns
Figure 11
Figure 12
Figure 13
Figure 14
MR Pulse Width, LOW
3.5
4.0
ns
Figure 16
TOP Pulse Width
4.5
5.5
HIGH or LOW
3.5
4.0
ns
Figure 15
tW(H)
CPSO Pulse Width
4.5
5.5
ns
tW(L)
HIGH or LOW
3.0
4.0
Figure 13
Figure 14
tREC
Recovery Time
5.0
5.5
ns
Figure 16
tW(L)
TTS Pulse Width, LOW
MR to Any Input
11
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74F403A
Timing Waveforms
Conditions: stack not full, IES, PL LOW
FIGURE 11. Serial Input, Unexpanded or Master Operation
Conditions: stack not full, IES HIGH when initiated, PL LOW
FIGURE 12. Serial Input, Expanded Slave Operation
Conditions: data in stack, TOP HIGH, IES LOW when initiated, OES LOW
FIGURE 13. Serial Output, Unexpanded or Master Operation
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12
74F403A
Timing Waveforms
(Continued)
Conditions: data in stack, TOP HIGH, IES HIGH when initiated
FIGURE 14. Serial Output, Slave Operation
Conditions: IES LOW when initiated, OE, CPSO LOW; data available in stack
FIGURE 15. Parallel Output, 4-Bit Word or Master in Parallel Expansion
Conditions: TTS connected to IRF, TOS connected to ORE, IES, OES, OE, CPSO LOW, TOP HIGH
FIGURE 16. Fall Through Time
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74F403A
Timing Waveforms
(Continued)
Conditions: stack not full, IES LOW when initialized
NOTE A:TTS normally connected to IRF.
NOTE B: If stack is full, IRF will stay LOW.
FIGURE 17. Parallel Load Mode, 4-Bit Word (Unexpanded) or Master in Parallel Expansion
Conditions: stack not full, device initialized (Note 3) with IES HIGH
FIGURE 18. Parallel Load, Slave Mode
Note 3: Initialization requires a master reset to occur after power has been applied.
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24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Package Number N24C
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
74F403A First-In First-Out (FIFO) Buffer Memory
Physical Dimensions inches (millimeters) unless otherwise noted