Revised September 2000 74ACQ657 • 74ACTQ657 Quiet Series Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs General Description Features The ACQ/ACTQ657 contains eight non-inverting buffers with 3-STATE outputs and an 8-bit parity generator/ checker. Intended for bus oriented applications, the device combines the 245 and the 280 functions in one package. ■ Guaranteed simultaneous switching noise level and dynamic threshold performance The ACQ/ACTQ utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus or superior performance. ■ Guaranteed pin-to-pin skew AC performance ■ Combines the 245 and the 280 functions in one package ■ 300 mil 24-pin slim dual-in-line package ■ Outputs source/sink 24 mA ■ ACTQ has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74ACQ657SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACTQ657SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACTQ657SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description A0–A7 Data Inputs/3-STATE Outputs B0–B7 Data Inputs/3-STATE Outputs T/R Transmit/Receive Input OE Enable Input PARITY Parity Input/3-STATE Output ODD/EVEN ODD/EVEN Parity Input ERROR Error 3-STATE Output FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS010636 www.fairchildsemi.com 74ACQ657 • 74ACTQ657 Quiet Series Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs January 1990 74ACQ657 • 74ACTQ657 Functional Description The Transmit/Receive (T/R) input determines the direction of the data flow through the bidirectional transceivers. Transmit (active HIGH) enables data from the A-Port to the B-Port; Receive (active LOW) enables data from the B-Port to the A-Port. select (ODD/EVEN). If the Parity Select is HIGH and an even number of A inputs are HIGH, the Parity output is HIGH. In receiving mode (T/R LOW), the parity select and number of HIGH inputs on port B are compared to the condition of the Parity input. If an even number of bits on the B-Port are HIGH, the parity select is HIGH, and the PARITY input is HIGH, then ERROR will be HIGH to indicate no error. If an odd number of bits on the B-Port are HIGH, the parity select is HIGH, and the PARITY input is HIGH, the ERROR will be LOW indicating an error. The Output Enable (OE) input disables the parity and ERROR outputs and both the A and B Ports by placing them in a HIGH-Z condition when the Output Enable input is HIGH. When transmitting (T/R HIGH), the parity generator detects whether an even or odd number of bits on the A-Port are HIGH and compares these with the condition of the parity Function Table Number of Input/ Inputs Inputs That Outputs Output Are High OE T/R ODD/EVEN Parity ERROR 0, 2, 4, 6, 8 L H H H Z Transmit L H L L Z Transmit L L H H H Receive L L H L L Receive L L L H L Receive L L L L H Receive 1, 3, 5, 7 Immaterial L H H L Z Transmit L H L H Z Transmit L L H H L Receive L L H L H Receive L L L H H Receive L L L L L Receive H X X Z Z Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Function Table Inputs Outputs OE T/R L L Bus B Data to Bus A L H Bus A Data to Bus B H X High-Z State H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial www.fairchildsemi.com Outputs Mode 2 74ACQ657 • 74ACTQ657 Functional Block Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74ACQ657 • 74ACTQ657 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 MA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC +0.5V VO =VCC + 0.5V +20 mA 0V to VCC −40°C to +85°C Minimum Input Edge Rate ∆V/∆t ACQ Devices DC Output Source VIN from 30% to 70% of VCC ±50 mA VCC @3.0V, 4.5V, 5.5V 125 mV/ns Minimum Input Edge Rate ∆V/∆t DC VCCor Ground Current ±50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) 0V to VCC Operating Temperature (TA) −0.5V to VCC +0.5V or Sink Current (IO) 4.5V to 5.5V Output Voltage (VO) −20 mA DC Output Voltage (VO) 2.0V to 6.0V ACTQ Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V ACQ ACTQ Devices −65°C to +150°C VIN from 0.8V to 2.0V DC Latch-up Source VCC @4.5V, 5.5V ±300 mA Sink Current Junction Temperature (TJ) 140°C PDIP 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC Electrical Characteristics for ACQ Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL VOH VCC TA = +25°C (V) Typ 3.0 1.5 TA = −40°C to +85°C Guaranteed Limits 2.1 2.1 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Voltage Output 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.85 4.76 0.1 Units Conditions VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA VIN = VIL or VIH VOL IOH = −12 mA V IOH = −24mA IOH = −24 mA (Note 2) Maximum LOW Level 3.0 0.002 0.1 Output Voltage 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA VI = VCC, GND 75 mA VOLD = 1.65V Max −75 mA VOHD = 3.85V Min 80.0 µA V IOUT = 50 µA VIN = VIL or VIH IIN Maximum Input Leakage Current (Note 4) (T/R, OE, ODD/EVEN Inputs) IOLD Minimum Dynamic IOHD Output Current (Note 3) 5.5 ICC (Note 4) Maximum Quiescent Supply Current 5.5 IOZT 5.5 8.0 V IOL = 24 mA IOL = 24 mA (Note 2) VIN = VCC or GND VI (OE) = VIL, VIH Maximum I/O Leakage Current (An, Bn Inputs) IOL = 12 mA ±0.6 5.5 ±6.0 µA VI = VCC, GND VO = VCC, GND VOLP Quiet Output Maximum Dynamic VOL www.fairchildsemi.com 5.0 1.1 1.5 4 V Figures 1, 2 (Note 5)(Note 6) Symbol VOLV Parameter Quiet Output Minimum Dynamic VOL VIHD Minimum HIGH Level Dynamic Input Voltage VILD Maximum LOW Level Dynamic Input Voltage (Continued) TA = +25°C VCC TA = −40°C to +85°C Units Conditions (V) Typ Guaranteed Limits 5.0 −0.6 −1.2 V 5.0 3.1 3.5 V (Note 5)(Note 7) 5.0 1.9 1.5 V (Note 5)(Note 7) Figures 1, 2 (Note 5)(Note 6) Note 2: Maximum of 8 outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. Note 5: DIP package. Note 6: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One output @ GND. Note 7: Max number of Data Inputs (n) switching. (n−1) Inputs switching 0V to 5V (ACQ).Input-under-test switching: 5V to threshold (VILD), 0V to threshold (VIHD) f = 1 MHz. DC Electrical Characteristics for ACTQ Symbol VIH VIL VOH Parameter TA = +25°C VCC (V) Typ TA = −40°C to +85°C Guaranteed Limits Minimum HIGH Level 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Units V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA V IOH = −24mA VIN = VIL or VIH 4.5 5.5 VOL 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 Maximum I/O Leakage Current 5.5 ±0.6 ±6.0 (An, Bn Inputs) 5.5 IOH = −24 mA (Note 8) V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IIN Maximum Input Leakage Current (T/R, OE, ODD/EVEN Inputs) IOZT µA µA VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC − 2.1V ICCT Maximum ICC/Input 5.5 1.5 mA IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 9) 5.5 −75 mA VOHD = 3.85V Min ICC (Note 4) Maximum Quiescent Supply Current 5.5 80.0 µA VIN = VCC or GND VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL 0.6 IOL = 24 mA (Note 8) 8.0 5.0 1.1 1.5 V 5.0 −0.6 −1.2 V Figures 1, 2 (Note 10)(Note 11) Figures 1, 2 (Note 10)(Note 11) VIHD Minimum HIGH Level Dynamic Input Voltage 5.0 1.9 2.2 V (Note 10)(Note 12) VILD Maximum LOW Level Dynamic Input Voltage 5.0 1.2 0.8 V (Note 10)(Note 12) Note 8: All outputs loaded; thresholds on input associated with output under test. Note 9: Maximum test duration 2.0 ms, one output loaded at a time. Note 10: DIP package. Note 11: Max number of outputs defined as (n). n−1 Data Inputs are driven 0V to 3V; one output @ GND. Note 12: Max number of Data Inputs (n) switching. (n−1) Inputs switching 0V to 3V (ACQ). Input-under-test switching; 3V to threshold (VILD), 0V to threshold (VIHD) f =1 MHz. 5 www.fairchildsemi.com 74ACQ657 • 74ACTQ657 DC Electrical Characteristics for ACQ 74ACQ657 • 74ACTQ657 AC Electrical Characteristics for ACQ Symbol Parameter VCC TA = 25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF (Note 13) Min Typ Max Min Max tPLH Propagation Delay 3.3 2.5 8.0 11.5 2.5 12.0 tPHL An to Bn, Bn to An 5.0 1.5 5.0 7.5 1.5 8.0 tPLH Propagation Delay 3.3 3.0 11.5 16.5 3.0 17.0 tPHL An to Parity 5.0 2.0 7.0 10.5 2.0 11.0 tPLH Propagation Delay 3.3 3.0 10.0 15.0 3.0 15.5 tPHL ODD/EVEN to PARITY 5.0 2.5 6.5 10.0 2.5 10.5 tPLH Propagation Delay 3.3 3.0 10.0 15.0 3.0 15.5 tPHL ODD/EVEN to ERROR 5.0 2.5 6.5 10.0 2.5 10.5 tPLH Propagation Delay 3.3 3.5 11.5 16.0 3.5 16.5 tPHL Bn to ERROR 5.0 2.5 7.0 10.5 2.5 11.0 tPLH Propagation Delay 3.3 3.0 9.0 13.5 3.0 14.0 tPHL PARITY to ERROR 5.0 2.0 6.0 9.0 2.0 9.5 tPZH Output Enable Time 3.3 2.5 9.0 13.5 2.5 14.0 tPZL OE to An/Bn 5.0 2.0 6.0 9.0 2.0 9.5 tPHZ Output Disable Time 3.3 1.0 8.5 13.0 1.0 13.5 tPLZ OE to An/Bn 5.0 1.0 5.5 8.5 1.0 9.0 tPZH Output Enable Time 3.3 2.5 9.0 13.5 2.5 14.0 tPZL OE to ERROR (Note 15) 5.0 2.0 6.0 9.0 2.0 9.5 tPHZ Output Disable Time 3.3 1.0 8.5 13.0 1.0 13.5 tPLZ OE to ERROR 5.0 1.0 5.5 8.5 1.0 9.0 tPZH Output Enable Time 3.3 2.5 9.0 13.5 2.5 14.0 tPZL OE to PARITY 5.0 2.0 6.0 9.0 2.0 9.5 tPHZ Output Disable Time 3.3 1.0 8.5 13.0 1.0 13.5 tPLZ OE to PARITY 5.0 1.0 5.5 8.5 1.0 9.0 tOSHL Output to Output Skew (Note 14) 3.3 1.0 1.5 1.5 tOSLH An, Bn to Bn, An 5.0 0.5 1.0 1.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns Note 13: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V Note 14: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Not tested. Note 15: These delay times reflect the 3-STATE recovery time only and not the signal time through the buffers or the parity check circuitry. To assure VALID information at the ERROR pin, time must be allowed for the signal to propagate through the drivers (B to A), through the parity check circuitry (same as A to PARITY), and to the ERROR output after the ERROR pin has been enabled (Output Enable times). VALID data at the ERROR pin ≥ (A to PARITY) +(Output Enable Time). www.fairchildsemi.com 6 Symbol Parameter tPLH Propagation Delay tPHL An to Bn, Bn to An tPLH Propagation Delay tPHL An to Parity tPLH Propagation Delay tPHL ODD/EVEN to PARITY tPLH Propagation Delay tPHL ODD/EVEN to ERROR tPLH, Propagation Delay tPHL Bn to ERROR tPLH Propagation Delay tPHL PARITY to ERROR tPZH Output Enable Time tPZL OE to An/Bn tPHZ Output Disable Time tPLZ OE to An/Bn tPZH Output Enable Time tPZL OE to ERROR (Note 18) tPHZ Output Disable Time tPLZ OE to ERROR tPZH Output Enable Time tPZL OE to PARITY tPHZ Output Disable Time tPLZ OE to PARITY tOSHL Output to Output Skew tOSLH An, Bn to Bn, An (Note 17) VCC TA = 25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 16) Min Typ Max Min Max 5.0 1.5 5.0 8.0 1.5 8.5 ns 5.0 2.5 7.5 11.0 2.5 11.5 ns 5.0 2.5 6.5 10.5 2.5 11.0 ns 5.0 2.5 6.5 10.5 2.5 11.0 ns 5.0 3.0 7.5 11.0 3.0 11.5 ns 5.0 2.0 6.0 9.5 2.0 10.0 ns 5.0 2.0 6.0 9.5 2.0 10.0 ns 5.0 1.0 5.0 9.0 1.0 9.5 ns 5.0 2.0 6.0 9.5 2.0 10.0 ns 5.0 1.0 6.0 9.0 1.0 9.5 ns 5.0 2.0 6.0 9.5 2.0 10.0 ns 5.0 1.0 5.0 9.0 1.0 9.5 ns 0.5 1.0 1.0 ns 5.0 Note 16: Voltage Range 5.0 is 5.0V ±0.5V Note 17: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Not tested. Note 18: These delay times reflect the 3-STATE recovery time only and not the signal time through the buffers or the parity check circuitry. To assure VALID information at the ERROR pin, time must be allowed for the signal to propagate through the drivers (B to A), through the parity check circuitry (same as A to PARITY), and to the ERROR output after the ERROR pin has been enabled (Output Enable times). VALID data at the ERROR pin ≥ (A to PARITY) + (Output Enable Time). Capacitance Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance Typ Units 4.5 pF VCC = 5.0V 160.0 pF VCC = 5.0 7 Conditions www.fairchildsemi.com 74ACQ657 • 74ACTQ657 AC Electrical Characteristics for ACTQ 74ACQ657 • 74ACTQ657 FACT Noise Characteristics The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. VOLP/VOLV and VOHP/VOHV: • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture • Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case transition. Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. VILD and VIHD: • Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. • First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as V ILD. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. • Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as V IHD. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. FIGURE 1. Quiet Output Noise Voltage Waveforms Note 19: VOHV and VOLP are measured with respect to ground reference. Note 20: Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps. FIGURE 2. Simultaneous Switching Test Circuit www.fairchildsemi.com 8 74ACQ657 • 74ACTQ657 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 9 www.fairchildsemi.com 74ACQ657 • 74ACTQ657 Quiet Series Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10