Application Note 1799 Author: Manjing Xie ISL9444EVAL3Z: Triple PWM Step-Down Synchronous Converters Introduction Evaluation Board Specifications ISL9444EVAL3Z consists of three PWM step-down synchronous converters, which features the triple PWM controller, ISL9444. The PWM1 delivers 5V output at 5A. PWM2 and PWM3 deliver 5V at 25A and 3.3V at 25A, respectively. A power failure monitor and three independent enable pins accommodate variable power sequencing requirement. The Extbias option is provided to achieve low standby power. TABLE 1. EVALUATION BOARD ELECTRICAL SPECIFICATIONS SPEC DESCRIPTION MIN TYP MAX UNIT VIN Input for PWM2 and PWM3 5.6 12 16 V VOUT2 IOUT = 0A 4.75 5.0 5.25 V VOUT3 IOUT = 0A 3.15 3.3 3.65 V IOUT_2 Output Current of PWM2 IOUT_3 and PWM3 Strong gate driver and adaptive deadtime control achieve excellent efficiency over 96%. VIN2 ISL9444 Key Features Input for PWM1 VOUT1 IOUT = 0A IOUT_1 Output Current of PWM1 • Wide input voltage range: 4.5V to 28V • Use lower MOSFET’s rDS(ON) for current sensing 25 5.6 12 16 V 4.75 5 5.25 V 6 FSW • Extbias pin to save operating loss • Power failure monitor • Complete protection: overvoltage, overcurrent, thermal shutdown • Three independent power-good indicators η VIN = 12V, PWM1, 6A, EN2 = EN3 = GND η VIN = 12V, PWM1 at 6A, PWM 2 and PWM3 at 25A respectively A A 330 kHz 96 % 95.9 % +++ FIGURE 1. ISL9444EVAL3Z TOP AND BOTTOM VIEW TABLE 2. RECOMMENDED COMPONENT SELECTION FOR QUICK EVALUATION FOR PWM CHANNEL VOUT (V) IOUT (A) VIN (V) FSW(kHz) /RT(kΩ) MOSFET(s), LOWER, UPPER 12 15 19 to 26.4 250/130 1XBSC059N04, 1XBSC059N04 RSEN INDUCTOR (L, ISAT) 2.0kΩ 4.7µH, 20A COUTs 270µF, OSCON, 16V and 2x1.0µF, ceramic FEEDBACK RES (LOWER, UPPER, kΩ) CFF 3.24, 52.3 1nF NOTES: 1. Please select the output capacitor with a voltage rating higher than the output. 2. Please adjust ROCSET accordingly. 3. Please contact Intersil Sales for assistance. December 5, 2012 AN1799.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1799 Recommended Equipment The following equipment is recommended for evaluation: • 0V to 20V power supply with 30A source current capability • Electronic load capable of sinking 30A @ 20V 6. Use an oscilloscope to observe the output ripple voltage and phase node ringing. For accurate measurement, please refer to Figure 3 for proper probe set-up. 7. Optimization. Please refer to Table 2 on page 1 for optimization recommendation. NOTE: All Test points are for voltage measurement or small signal only. Do not allow high current through these test points. • Digital Multimeters (DMMs) • 100MHz Quad-Trace Oscilloscope TABLE 3. JUMPER DEFAULT POSITIONS Quick Test Setup 1. Ensure that the evaluation board is correctly connected to the power supply and the electronic load prior to applying any power. Please refer to Figure 2 for proper set-up. 2. Refer to Table 3 for jumper default positions. For set-up different than the default setting, please refer to the datasheet for details (ISL9444, FN7665). JUMPER NAME PFI EN1 EN2 EN3 MODE Positions VIN EN PFO EN2 CCM Probe Set-up 3. Turn on the power supplies; VIN < 16V; VIN2 < 16V 4. Adjust input voltage VIN and VIN2 within the specified range and observe output voltage. The output voltage variation should be within 5%. OUTPUT CAP OUTPUT OUTPUT CAP CAP OR MOSFET OR MOSFET 5. Adjust load current within specified range. The output voltage variation should be within 5%. FIGURE 3. OSCILLOSCOPE PROBE SET-UP FIGURE 2. ISL9444EVAL3Z TEST SET-UP 2 AN1799.0 December 5, 2012 Application Note 1799 Output Setting Transient Load Test The output voltage is set by the feedback resistor divider, Rlow and Rup. The ISL9444EVAL3Z provides optional load transient test footprints for high di/dt load transient response tests. Please refer to Figure 4 for the load transient circuit of PWM1. By sensing the positive rail from load, significant voltage drop along the PCB trace can be compensated. For applications with load far from the ISL9444, it is likely that the remote sensing trace picks up noise from the environment. To prevent noise being coupled into the feedback loop, it is recommended to connect the phase boosting capacitors, Cff1, Cff2 and Cff3 to the local output capacitors. For applications that Cffx is not used for phase boosting, a pair of Cff and Cp is recommended for remote sensing. Please set Cff and Cp according to Equation 2. R low ⋅ C P = R up ⋅ C ff (EQ. 2) In case the remote sensing trace become open-circuit, a default resistor is recommended to connect the resistor Rup to the local VOUT. The ISL9444 does not provide dedicated differential amplifier for remote sensing. 3. Apply pulse square waveform to the gate of the load transient test MOSFET, Q10. The duty cycle of the pulse waveform should be small (<5%) to limit thermal stress on current sensing resistor and the MOSFETs. Set the amplitude of the square waveform below 0.5V at the beginning. 4. The amplitude of the square waveform set the current step amplitude. Slowly increase the amplitude of the square waveform and monitor the current amplitude. Adjust the square waveform rising and falling time to set the current step slew rate. 5. Monitor overshoot and undershoot at the corresponding output. VO1 LOAD TRANSIENT CIRCUIT 1 DNP R20 DNP, 10k Q10 R21 DNP, 0.01 VO1 1 Remote Sensing 2. Install the load transient circuit as indicated in the “Schematic (Optional Circuits and Optional Footprints)” on page 8. R18, R20 and R22 are 10kΩ resistors for MOSFET gate discharging. J5 ISTEP2 J4 2 Where Rlow is the resistor from FBx to GND, Rup is the resistor from VOx to FBx. Resistor R10, R12 and R13 are resistor jumpers for loop gain measurement. They are not must-to-have components. It is recommended to use 50Ω for loop gain measurement. 1. Select a powerpak or SOIC8 MOSFET with VDSS breakdown greater than VOUT. Select a current sensing resistor. For accurate current sensing, please use tighter than 5% tolerance resistors. To alleviate thermal stress, use 0.1Ω or smaller resistance. For 25A application, a 10mΩ precision resistor is recommended. Use an oscilloscope to monitor voltage across R21 and the output voltage. 1 (EQ. 1) 2 R low + R up V OUT = ----------------------------- × 0.7V R low FIGURE 4. LOAD TRANSIENT SET-UP 3 AN1799.0 December 5, 2012 Application Note 1799 Typical Performance Curves 98 97 96 96 94 95 EFFICIENCY (%) EFFICIENCY (%) Oscilloscope Plots were taken at VIN = 12V, VIN2 = 12V and jumpers in default positions, unless otherwise noted. 92 90 88 86 93 92 91 84 90 82 89 80 88 0 1.0 2.0 3.0 4.0 LOAD CURRENT (A) 5.0 6.0 0 FIGURE 5. EFFICIENCY vs LOAD CURRENT FOR PWM1 (EN2 = EN3 = GND) 5.0 97 5.2 96 5.15 VOUT REGULATION(V) 94 93 92 91 90 20 25 5.10 5.05 5.00 4.95 4.90 4.85 89 88 4.80 0 20 40 60 80 100 0 1.2 LOAD(%) 3.6 4.8 6.0 FIGURE 8. LOAD REGULATION OF PWM1 (V IN2 = 12V) 3.34 5.15 3.33 VOUT REGULATION (V) 5.20 5.10 5.05 5.00 4.95 4.90 4.85 4.80 2.4 LOAD CURRENT(A) FIGURE 7. EFFICIENCY vs LOAD(%) FOR ALL PWMs (6A, 25A, 25A) VOUT REGULATION (V) 10 15 LOAD CURRENT (A) FIGURE 6. TOTAL EFFICIENCY vs LOAD PWM2 AND PWM3 (EN/SS1 IS GROUNDED) 95 EFFICIENCY (%) 94 3.32 3.31 3.30 3.29 3.28 3.27 0 5 10 15 20 LOAD CURRENT (A) FIGURE 9. LOAD REGULATION of PWM2 (V IN = 12V) 4 25 3.26 0 5 10 15 20 25 LOAD CURRENT (A) FIGURE 10. LOAD REGULATION of PWM3 (V IN = 12V) AN1799.0 December 5, 2012 Application Note 1799 Typical Performance Curves Oscilloscope Plots were taken at VIN = 12V, VIN2 = 12V and jumpers in default positions, unless otherwise noted. (Continued) VO1(AC) AT 50mV/DIV VO1(AC) AT 50mV/DIV VO2(AC) AT 50mV/DIV VO3(AC) AT 50mV/DIV TIME AT 200µs/DIV TIME AT 5µs/DIV FIGURE 11. OUTPUT RIPPLE (V IN = 12V, FULL LOAD, 20MHz BW) FIGURE 12. LOAD TRANSIENT RESPONSE of PWM1 (1.25A TO 3.75A AT 2A/µs) VO3(AC) AT 50mV/DIV VO2(AC) AT 100mV/DIV TIME AT 200µs/DIV FIGURE 13. LOAD TRANSIENT RESPONSE of PWM2 (6.25A TO 18.75A AT 2A/µs) TIME AT 200µs/DIV FIGURE 14. LOAD TRANSIENT RESPONSE OF PWM1 (6.25A TO 18.75A AT 2A/µs) VIN AT 5V/DIV VIN AT 5V/DIV VO1 AT 2V/DIV VO1 AT 2V/DIV VO2 AT 2V/DIV VO2 AT 2V/DIV VO3 AT 2V/DIV VO3 AT 2V/DIV TIME AT 10ms/DIV FIGURE 15. POWER-UP SEQUENCING (DEFAULT CONFIGURATION) 5 TIME AT 10ms/DIV FIGURE 16. POWER-UP SEQUENCING (EN2 = PGOOD1) AN1799.0 December 5, 2012 Application Note 1799 Typical Performance Curves Oscilloscope Plots were taken at VIN = 12V, VIN2 = 12V and jumpers in default positions, unless otherwise noted. (Continued) PHASE AT 5V/DIV VO AT 100mV/DIV TIME AT 200ms/DIV FIGURE 17. OVERCURRENT PROTECTION RESPONSE OF PWM1 6 PHASE AT 5V/DIV VO AT 0.5V/DIV TIME AT 20ms/DIV FIGURE 18. OVERCURRENT PROTECTION OF PWM2 AN1799.0 December 5, 2012 Schematic, Main VIN 7V to 16V 1 VFB1 3 VO1SNS VO1 TP12 1 CLKOUT Cf f1 PGOOD1 Cp1 PGOOD1 DNP R2 4.99k 1% PGOOD2 RPG2 100k 3 PGOOD3 VCC5V 1 CBS 1µ 16V J16 UG3 PH3 PH3 CO21 CO25 CO27 CO28 CO24 270µ 16V DNP 6. 3V DNP 10V 10µF 10V 10µ 10V CO23 5V@25A 10µ J9 10V 1 CO22 CO26 CO29 DNP 10V DNP 10V 1 TP8 GND 40 ISEN1 39 PHASE1 38 BOOT1 37 UGATE1 36 LGATE1 35 LGATE2 34 UGATE2 33 BOOT2 32 PHASE2 31 ISEN2 RPG3 100k CIN5 VO3 CB3 0.22µ 16V 25 PHASE3 24 ISEN3 23 MODE/SYNC 22 EN3 21 TK/SS3 Rsen3 2.0k Q3 BSC0902NS MODESYNC EN3 1% R7 DNP CS3 47n PH3 2 LG3 1 L3 1.0µH VO3 1 CO35 CO31 CO37 270µ 16V DNP DNP CO32 CO36 270µ 16V DNP VO3 1%59k R3 DNP VO2SNS R8 30.9k 1% 2 VO1 BIAS VO2 Cff2 470p R11 4. 99k 1% Cp2 Do NOT connect unless VO1 is less than 6V DNP R19, R20, R21 and R23 are for EVAL board testing only. They are not necessary in end applications. EN2 PFO_N PFO_N DISABLE PGOOD1 PGOOD1 TP14 JMODE 61 MODESYNC 5 Ext. Clock SYNC 5 6 4 3 VCC5V CCM 3 4 2 1 1 2 DEM MODE/SYNC 5 EN3 3 1 JEN3 5 6 3 4 1 2 6 VCC5V 4 2 VCC5V JEN1 DISABLE EN2 EN2 EN3 PWM3 is configured to track the VO2 by default. 1 23 EN1 2 3 AN1799.0 December 5, 2012 5 6 5 6 TP13 1 EN2 3 4 3 4 1 2 EN2 1 2 TP15 EN3 1 1 JEN2 J10 CO34 3.3V@25A 10µ 16V CO38 VO3SNS Cp3 TP9 VO3 CO33 10µ 16V 10µ 16V 1 J11 1 TP10 GND 330p Cf f3 R6 15.8k 1% 1 VO3SNS CL3 820p QL3 BSC0902NS VO2 R9 DNP 0.1% R13 10 RL3 1.6 RB3 0 26 BOOT3 FB3 PGOOD2 10µ 25V J8 1 270µ 16V QU3 BSC0902NS 28 27 UGATE3 ISL9444 PGOOD EXTBIAS 29 PGND LGATE3 RPG1 100k 3 2 1000p CLKOUT 1 1 R1 30.9k 1% RL2 1.6 Q7 DNP 30 ROC3 243k PFI_x TP4 PFI_Ext 2 0.47µ 35V PFI_Ext 1 CFIN 2 PFI EXTBIAS 3 EXTBIAS VCC5V 4 VCC_5V 10V 5 VIN Cs1 47n EN/SS1 6 EN/SS1 7 FB1 8 OCSET1 88.7k RT 9 RT ROC1 10 243k PGOOD1 CVCC 4. 7µ 47n CS2 DNP SVIN DNP RFIN 22 243k ROC2 1 1 2 VIN 23 CO11 VIN2 2 10µ 25V 13 PG3_DLY EN2 14 EN2 15 SGND 16 OCSET2 17 FB2 18 TK/SS2 19 OCSET3 20 FB3 VIN R5 12.1k 1% DNP CO15 R12 10 1% VIN CLKOUT CLKOUT PFO_N DNP CDLY DNP 1 Rsen2 2. 0k VO2SNS ENABLE EN/SS1 DISABLE Application Note 1799 CO12 CO13 PFI_Select R4 51.1k 1% QL2 BSC0902NS VO2 CIN4 U1 PFI_x TP6 1 GND TP3 PFO_N CL1 470p PGOOD3 560µF PAD CO16 DNP 10V CIN7 10µ 25V CL2 820p PGOOD2 PGOOD3 CO14 12 1µF 10V RB2 0 RB1 0 Rsen1 2. 0k 11 10µ 10V CO18 1 RL1 1. 6 LG2 CB2 0.22µ 16V CB1 0.22µ 16V L1 4. 7µH CO17 5Vsb @ 5A PH2 Q2 BSC0902NS LG1 QL1 BSC057N03 L2 1.0µH 1 PH2 Q1 DNP VO1 VO1 CIN11 10µF 25V QU2 BSC0902NS UG2 41 7 1 J15 UG1 VO1SNS CIN8 10µ 25V Q6 DNP PH1 R10 10 1% J14 CIN6 10µ 25V 100µ 35V QU1 BSC057N03 DNP CIN3 10µ 25V CIN1 PH1 TP2 1 GND TP16 1 GND TP5 1 VO1 J7 CIN9 100µ 35V 1 TP7 VO2 VIN Q5 DNP 100µ 35V CIN2 1 J13 J6 VIN2 PFO_N 1 J2 1 CIN10 3 1 TP11 1 VIN2 J1 3 TP1 1 VIN J3 Application Note 1799 Schematic (Optional Circuits and Optional Footprints) VO2 LOAD TRANSIENT CIRCUIT 2 VO3 LOAD TRANSIENT CIRCUIT 3 2 1 2 PH1 VO1 LOAD TRANSIENT CIRCUIT 1 VO2 L5 DNP PH2 VO3 L6 DNP J12 2 VO2 1 J19 ISTEP3 DNP Q10 VO1 1 R21 DNP, 0.01 J5 ISTEP2 J4 2 R20 DNP, 10k 1 PH3 2 L4 DNP R22 R17 DNP DNP, 10k 0.1 J18 2 1 J17 ISTEP2 3 VO1 1 R19 DNP 0.01 2 R18 DNP 10k VO3 1 Q9 DNP Q8 DNP Bill of Materials ITEM QTY REFERENCE VALUE DESCRIPTION PART # VENDOR ESSENTIAL COMPONENTS 1 1 CBS 1µ Ceramic CAP, X5R, 16V, SM0603 Generic Generic 2 3 CB1, CB2, CB3 0.22µ Ceramic CAP, X5R, 16V, SM0603 Generic Generic 3 1 CFIN 0.47µ Ceramic CAP, X5R, 35V, SM0603 Generic Generic 4 3 CIN1, CIN2, CIN10 100µ Alum. CAP, 25V UTT1E101MPD Nichicon 5 7 Ceramic CAP, X5R, 25V, SM1206 Generic Generic 6 1 CL1 470p Ceramic CAP, NP0 or C0G, SM0805 Generic Generic 7 2 CL2, CL3 820p Ceramic CAP, NP0 or C0G, SM0805 Generic Generic 8 8 CO17, CO18, CO23, CO24, CO28, CO33, CO34, CO38 10µ Ceramic CAP, X5R, 10V, SM0805 Generic Generic 9 5 CO16, CO21, CO22, CO32, CO35 270µF OSCON, 16V, RADIAL 8x8 16SEPC270MX SANYO 10 3 CS1, CS2, CS3 47n Ceramic CAP, NP0 or C0G, SM0603 Generic Generic 11 1 CVCC 4.7µ Ceramic CAP, X5R 10V, SM0805 Generic Generic 12 2 Cff1 1000p Ceramic CAP, NP0 or C0G, SM0603 Generic Generic 13 1 Cff2 470p Ceramic CAP, NP0 or C0G, SM0603 Generic Generic 14 1 Cff3 330p Ceramic CAP, NP0 or C0G, SM0604 Generic Generic 15 1 L1 4.7µH INDUCTOR, ISAT > 10A 7443320470 Wurth Electronics 16 2 L2, L3 1.0µH INDUCTOR, ISAT > 35A SER2010-102ML Coilcraft 17 2 QU1, QL1 Single Channel NFET, 30V BSC057N03 Infineon 18 6 QU2, QL2, Q2, QU3, QL3, Q3 Single Channel NFET, 30V BSC0902NS Infineon 19 3 RB1, RB2, RB3 0 RESISTOR, SM0603 Generic Generic 20 1 RFIN 22 RESISTOR, SM0603, 10% Generic Generic 21 3 RL1, RL2, RL3 1.6 RESISTOR, SM0805, 10% Generic Generic 22 3 ROC1, ROC2, ROC3 243k RESISTOR, SM0603, 1% Generic Generic 23 3 RPG1, RPG2, RPG3 100k RESISTOR, SM0603, 10% Generic Generic CIN3, CIN4, CIN5, CIN6, CIN7, CIN8, CIN11 10µ 8 AN1799.0 December 5, 2012 Application Note 1799 Bill of Materials (Continued) ITEM QTY REFERENCE VALUE DESCRIPTION PART # VENDOR 24 1 RT 88.7k RESISTOR, SM0603, 1% Generic Generic 25 3 Rsen1, Rsen2, Rsen3 2.0k RESISTOR, SM0603, 1% Generic Generic 26 2 R1, R8 30.9k RESISTOR, SM0603,1% Generic Generic 27 2 R2, R11 4.99k RESISTOR, SM0603,1% Generic Generic 28 1 R3 59k RESISTOR, SM0603,1% Generic Generic 29 1 R4 51.1k RESISTOR, SM0603, 1% Generic Generic 30 1 R5 12.1k RESISTOR, SM0603,1% Generic Generic 31 1 R6 15.8k RESISTOR, SM0603, 1% Generic Generic 32 3 R10, R12, R13 10 RESISTOR, SM0603, 10% Generic Generic 33 1 U1 Triple PWM Controller, 40L- 5x5 QFN ISL9444IRZ Intersil EVAL BOARD HARDWARE AND RESISTOR JUMPERs 34 3 JEN1, J14, J15 1x3 Header Generic Generic 35 3 JEN2, JEN3, JMODE 2x3 Header Generic Generic 36 10 J1, J2, J3, J6, J7, J8, J9, J10, J11, J13 CONN- Big Lug, TERMINAL POST KPA8CTP 37 1 J16 1x2 Header Generic Generic 38 16 TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9, TP10, TP11, TP12, TP13, TP14, TP15, TP16 CONN-TURRET, TERMINAL POST, TH 1514-2 KEYSTONE 39 5 JEN1, J14, JEN2, JEN3, JMODE Connector Jumper SPC02SYAN Sullins BIAS OPTIONAL FOOTPRINTs 40 4 Cp1, Cp2, Cp3, CDLY DNP Ceramic CAP, NP0 or C0G, SM0603 41 2 CO25, CO11, CO31 DNP ELEC. CAP, RADIAL 8x8 42 2 CO13, CO29, CO14 DNP CAP, SM1210 43 4 CO12, CO15, CO26, CO27, CO36, CO37 DNP ELEC. CAP, SM7343 44 6 J4, J5, J12, J17, J18, J19 DNP 45 3 L4, L5, L6 DNP INDUCTOR 46 2 Q1, Q5, Q6, Q7 DNP Single Channel NFET 47 2 R7, R9 DNP RESISTOR, SM0603 DNP N-Channel MOSFET, TO252 COMPONENTs FOR LOAD TRANSIENT TEST CIRCUITs 48 3 Q8, Q9, Q10 49 1 R17, R19, R21 DNP, 0.01 RESISTOR, SM2512 50 3 R18, R20, R22 DNP, 10k RESISTOR, SM0603 9 AN1799.0 December 5, 2012 Application Note 1799 ISL9444EVAL3Z PCB Layout FIGURE 19. TOP SILKSCREEN 10 AN1799.0 December 5, 2012 Application Note 1799 ISL9444EVAL3Z PCB Layout (Continued) FIGURE 20. TOP LAYER 11 AN1799.0 December 5, 2012 Application Note 1799 ISL9444EVAL3Z PCB Layout (Continued) FIGURE 21. TOP LAYER ZOOM IN 12 AN1799.0 December 5, 2012 Application Note 1799 ISL9444EVAL3Z PCB Layout (Continued) FIGURE 22. SECOND LAYER 13 AN1799.0 December 5, 2012 Application Note 1799 ISL9444EVAL3Z PCB Layout (Continued) FIGURE 23. BOTTOM SILKSCREEN 14 AN1799.0 December 5, 2012 Application Note 1799 ISL9444EVAL3Z PCB Layout (Continued) FIGURE 24. 15 AN1799.0 December 5, 2012 Application Note 1799 ISL9444EVAL3Z PCB Layout (Continued) FIGURE 25. BOTTOM SILKSCREEN Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 16 AN1799.0 December 5, 2012