MOTOROLA MC14001UBCL

SEMICONDUCTOR TECHNICAL DATA
#$ ! "!
The UB Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired. The UB set of CMOS gates are inverting
non–buffered functions.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Linear and Oscillator Applications
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
• Double Diode Protection on All Inputs
• Pin–for–Pin Replacements for Corresponding CD4000 Series UB Suffix
Devices
# #" "
# #" "
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#" "
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LOGIC DIAGRAMS
MC14001UB
Quad 2–Input
NOR Gate
1
2
5
6
8
9
12
13
MC14002UB
Dual 4–Input
NOR Gate
3
4
10
11
MC14011UB
Quad 2–Input
NAND Gate
1
2
3
4
1
13
NC = 6, 8
MC14012UB
Dual 4–Input
NAND Gate
1
13
NC = 6, 8
4
9
4
6
5
11
12
10
VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES
P SUFFIX
PLASTIC
CASE 646
11
13
D SUFFIX
SOIC
CASE 751A
MC14025UB
Triple 3–Input
NOR Gate
2
8
3
13
10
9
12
MC14023UB
Triple 3–Input
NAND Gate
1
2
3
4
5
9
10
11
12
2
5
6
8
5
9
10
11
12
L SUFFIX
CERAMIC
CASE 632
3
1
2
8
3
4
5
11
12
13
ORDERING INFORMATION
9
MC14XXXUBCP
MC14XXXUBCL
MC14XXXUBD
Plastic
Ceramic
SOIC
6
TA = – 55° to 125°C for all packages.
10
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of
any voltage higher than maximum rated voltages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
v
v
REV 3
1/94
MC14001UB
Motorola, Inc. 1995
18
MOTOROLA CMOS LOGIC DATA
PIN ASSIGNMENTS
MC14001UB
Quad 2–Input NOR Gate
MC14002UB
Dual 4–Input NOR Gate
IN 1A
1
14
VDD
OUTA
1
14
VDD
MC14011UB
Quad 2–Input NAND Gate
IN 1A
1
14
VDD
IN 2A
2
13
IN 2D
IN 1A
2
13
OUTB
IN 2A
2
13
IN 2D
OUTA
3
12
IN 1D
IN 2A
3
12
IN 4B
OUTA
3
12
IN 1D
OUTB
4
11
OUTD
IN 3A
4
11
IN 3B
OUTB
4
11
OUTD
IN 1B
5
10
OUTC
IN 4A
5
10
IN 2B
IN 1B
5
10
OUTC
IN 2B
6
9
IN 2C
NC
6
9
IN 1B
IN 2B
6
9
IN 2C
VSS
7
8
IN 1C
VSS
7
8
NC
VSS
7
8
IN 1C
MC14012UB
Dual 4–Input NAND Gate
MC14023UB
Triple 3–Input NAND Gate
MC14025UB
Triple 3–Input NOR Gate
OUTA
1
14
VDD
IN 1A
1
14
VDD
IN 1A
1
14
VDD
IN 1A
2
13
OUTB
IN 2A
2
13
IN 3C
IN 2A
2
13
IN 3C
IN 2A
3
12
IN 4B
IN 1B
3
12
IN 2C
IN 1B
3
12
IN 2C
IN 3A
4
11
IN 3B
IN 2B
4
11
IN 1C
IN 2B
4
11
IN 1C
IN 4A
5
10
IN 2B
IN 3B
5
10
OUTC
IN 3B
5
10
OUTC
NC
6
9
IN 1B
OUTB
6
9
OUTA
OUTB
6
9
OUTA
VSS
7
8
NC
VSS
7
8
IN 3A
VSS
7
8
IN 3A
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
NC = NO CONNECTION
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
– 0.5 to + 18.0
V
Vin, Vout
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
lin, lout
Input or Output Current (DC or Transient),
per Pin
± 10
mA
PD
Power Dissipation, per Package†
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
260
_C
TL
Lead Temperature (8–Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
MOTOROLA CMOS LOGIC DATA
MC14001UB
19
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
“0” Level
VIL
5.0
10
15
—
—
—
1.0
2.0
2.5
—
—
—
2.25
4.50
6.75
1.0
2.0
2.5
—
—
—
1.0
2.0
2.5
5.0
10
15
4.0
8.0
12.5
—
—
—
4.0
8.0
12.5
2.75
5.50
8.25
—
—
—
4.0
8.0
12.5
—
—
—
5.0
5.0
10
15
– 1.2
– 0.25
– 0.62
– 1.8
—
—
—
—
– 1.0
– 0.2
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
—
—
—
—
– 0.7
– 0.14
– 0.35
– 1.1
—
—
—
—
IOL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
0.25
0.5
1.0
—
—
—
0.0005
0.0010
0.0015
0.25
0.5
1.0
—
—
—
7.5
15
30
µAdc
IT
5.0
10
15
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
“1” Level
IIH
Vdc
IOH
Source
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Total Supply Current**†
(Dynamic plus Quiescent,
Per Gate CL = 50 pF)
Sink
Vdc
mAdc
IT = (0.3 µA/kHz) f + IDD/N
IT = (0.6 µA/kHz) f + IDD/N
IT = (0.8 µA/kHz) f + IDD/N
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
package.
MC14001UB
20
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
Output Rise Time
tTLH = (3.0 ns/pF) CL + 30 ns
tTLH = (1.5 ns/pF) CL + 15 ns
tTLH = (1.1 ns/pF) CL + 10 ns
tTLH
Output Fall Time
tTHL = (1.5 ns/pF) CL + 25 ns
tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL
Propagation Delay Time
tPLH, tPHL = (1.7 ns/pF) CL + 30 ns
tPLH, tPHL = (0.66 ns/pF) CL + 22 ns
tPLH, tPHL = (0.50 ns/pF) CL + 15 ns
VDD
Vdc
Min
Typ #
Max
5.0
10
15
—
—
—
180
90
65
360
180
130
5.0
10
15
—
—
—
100
50
40
200
100
80
5.0
10
15
—
—
—
90
50
40
180
100
80
Unit
ns
ns
tPLH, tPHL
ns
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
20 ns
VDD
INPUT
14
PULSE
GENERATOR
INPUT
20 ns
VDD
90%
50%
10%
OUTPUT
0V
tPHL
*
CL
7
tPLH
VSS
* All unused inputs of AND, NAND gates must be
connected to VDD.
All unused inputs of OR, NOR gates must be
connected to VSS.
VOH
90%
50%
10%
OUTPUT
INVERTING
tTHL
VOL
tTLH
Figure 1. Switching Time Test Circuit and Waveforms
MC14001UB CIRCUIT SCHEMATIC
3
VDD
14
MC14002UB CIRCUIT SCHEMATIC
(1/2 of Device Shown)
VDD
10
14
2, 9
1
8
3, 10
2
9
4, 11
5, 12
1, 13
6
13
5
12
4
7
VSS
VSS
7
11
MOTOROLA CMOS LOGIC DATA
MC14001UB
21
MC14011UB CIRCUIT SCHEMATIC
(1/4 of Device Shown)
MC14012UB CIRCUIT SCHEMATIC
(1/2 of Device Shown)
MC14023UB CIRCUIT SCHEMATIC
(1/3 of Device Shown)
14 VDD
14 VDD
14 VDD
1, 13
3, 4, 10, 11
1, 6, 8, 13
2, 9
2, 5, 9, 12
3, 10
6, 9, 10
5, 1, 11
4, 11
7 VSS
4, 2, 12
5, 12
3, 8, 13
7 VSS
1, 3, 11
2, 4, 12
8, 5, 13
9, 6, 10
12
10
8.0
8.0
b
6.0
5.0 Vdc
4.0
b
a
6.0
15 Vdc
b a
a
4.0
10 Vdc
2.0
7 VSS
0
2.0
0
0
2.0 4.0 6.0 8.0 10 12 14 16
Vin, INPUT VOLTAGE (Vdc)
– 2.0
– 4.0
a TA = – 55°C
b TA = + 25°C
c TA = + 125°C
c
– 10 Vdc
– 8.0
a TA = + 125°C
b TA = – 55°C
8.0
a
6.0
b
5.0 Vdc
4.0
0
a b
0
2.0 4.0 6.0 8.0 10 12 14 16
Vin, INPUT VOLTAGE (Vdc)
Figure 3. Typical Voltage Transfer
Characteristics versus
Temperature
a
a
– 6.0
10 Vdc
10
10
c
b
I D, DRAIN CURRENT (mAdc)
I D, DRAIN CURRENT (mAdc)
VGS = – 5.0 Vdc
12
2.0
Figure 2. Typical Voltage and
Current Transfer Characteristics
0
VDD = 15 Vdc Unused input
connected to
b
VSS.
a
14
Vout , OUTPUT VOLTAGE (Vdc)
Vout , OUTPUT VOLTAGE (Vdc)
14
14 VDD
16
VDD = 15 Vdc TA = + 25°C
Unused input
connected to
VSS.
a One input only
10 Vdc
b Both inputs
I D, DRAIN CURRENT (mAdc)
16
MC14025UB CIRCUIT SCHEMATIC
(1/3 of Device Shown)
7 VSS
b
c
– 15 Vdc
b
8.0
15 Vdc
b
c
a
VGS = 10 Vdc
b
c
6.0
a TA = – 55°C
b TA = + 25°C
c TA = + 125°C
4.0
a
2.0
b
5.0 Vdc
c
– 10
– 10
a
– 8.0
– 6.0
– 4.0
VDS, DRAIN VOLTAGE (Vdc)
a
– 2.0
Figure 4. Typical Output Source
Characteristics
MC14001UB
22
0
0
0
2.0
4.0
6.0
VDS, DRAIN VOLTAGE (Vdc)
8.0
10
Figure 5. Typical Output Sink
Characteristics
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
–A–
14
9
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
C
–T–
L
K
SEATING
PLANE
F
G
D
N
M
J
14 PL
0.25 (0.010)
M
T A
S
14 PL
0.25 (0.010)
M
T B
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
14
8
1
7
B
A
F
L
C
J
N
H
G
D
SEATING
PLANE
MOTOROLA CMOS LOGIC DATA
K
M
S
DIM
A
B
C
D
F
G
J
K
L
M
N
INCHES
MIN
MAX
0.750
0.785
0.245
0.280
0.155
0.200
0.015
0.020
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15_
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.94
6.23
7.11
3.94
5.08
0.39
0.50
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15_
0.51
1.01
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0_
10_
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0_
10_
0.39
1.01
MC14001UB
23
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
14
8
–B–
1
P 7 PL
0.25 (0.010)
7
G
M
F
–T–
M
K
D 14 PL
0.25 (0.010)
M
T B
S
M
R X 45 _
C
SEATING
PLANE
B
A
S
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.228
0.244
0.010
0.019
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MC14001UB
24
◊
*MC14001UB/D*
MOTOROLA CMOSMC14001UB/D
LOGIC DATA