MOTOROLA MC145173DW

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by MC145173/D
SEMICONDUCTOR TECHNICAL DATA
Advance Information
! !#
# $ " !# ! DW SUFFIX
SOG PACKAGE
CASE 751E
24
1
CMOS
ORDERING INFORMATION
The MC145173 is a single–chip CMOS synthesizer with a four–wire serial
interface for primary use in AM–FM broadcast receivers. The device also finds
use in long–wave (LW) and short–wave (SW) receivers. Two inputs to a single
high–speed N counter are provided, along with 2 phase detectors; one for a
VHF loop up to 130 MHz, and another for an HF loop up to 40 MHz. The VHF
phase detector has a current source/sink output and both detectors feature
linear transfer functions (no dead zones). An external crystal ties across
on–chip circuitry which drives a completely–programmable reference counter.
Thus, a broad range of tuning resolution is possible. The crystal oscillator is
buffered and fed to an open–drain output which is active in the HF mode only.
Due to the patented BitGrabber registers, address or steering bits are not
needed in the serial data stream for random access of the registers. The serial
port is byte–oriented to facilitate control via an MCU. Tuning across a band is
accomplished with a two–byte transfer to the N register.
The 6–bit analog–to–digital converter (ADC) has two input channels. The
converter is read via a one–byte transfer which includes an end–of–conversion
(EOC) bit.
A 22–stage frequency counter is provided and accepts two IF (intermediate
frequency) signals. Primary use for the frequency counter is for the seek or
scan function on broadcast radio receivers. A proper frequency count ensures
tuning of valid stations on their center frequencies. Reading the count is
accomplished with a three–byte serial transfer which includes a count–complete (CC) bit.
Four general purpose digital outputs are included. One of the outputs is
open–drain; the others are totem–pole (push–pull). Two general purpose digital
inputs are provided also. One input has a comparator with a switch point at 33%
of VDD.
• Operating Voltage Range: 4.5 to 5.5 V
• Maximum Operating Frequency: VHFin = 130 MHz @ 210 mV p–p
HFin = 40 MHz @ 210 mV p–p
• Maximum Frequency of Reference Counter: 15 MHz
• Maximum Frequency of Frequency Counter: 20 MHz
• Maximum Supply Current: Operating Mode = 12 mA
Standby Mode = 30 µA
• Approximate ADC Conversion Time: 360 µs
• Operating Temperature Range: – 40 to + 85°C
• R Counter Division Range: 1 and 5 to 16,383
• N Counter Division Range: 40 to 32,767
• Accommodates Downconversion or Upconversion Receiver Design
for AM Broadcast Band
• Direct Interface to Motorola SPI Data Port
• Programmer’s Guide Included in Datasheet
MC145173DW SOG Package
PIN ASSIGNMENT
OSCin
1
24
OSCout
ENB
2
23
REFout
Din
3
22
OUTPUT D
CLK
4
21
VHF PDout
Dout
5
20
Rx
INPUT D
6
19
VSS
INPUT C
7
18
HF PDout
INPUT B
8
17
VDD
INPUT A
9
16
HFin
HF IFin
10
15
VHFin
VHF IFin
11
14
OUTPUT C
OUTPUT A
12
13
OUTPUT B
BitGrabber is a trademark of Motorola, Inc.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
 Motorola, Inc. 1995
MOTOROLA
REV 1
3/95
MC145173
1
BLOCK DIAGRAM
23
1
24
OSCin
OSCout
14–STAGE R COUNTER
OSCILLATOR
PRESCALER
fR
STANDBY
LOGIC
ACQUISITION
WINDOW
DIVIDER
14
RESET
ACQ. WINDOW
CURRENT
SOURCE/SINK
PHASE/FREQUENCY
DETECTOR
2
BitGrabber
R REGISTER
24 BITS
24
SHIFT REGISTER
AND
CONTROL LOGIC
5
Dout
14
13
12
BitGrabber
C REGISTER
8 BITS
2
2
ENB
21
22
3
Din
READ
BitGrabber
N REGISTER
16 BITS
24
HFin
20
POL
4
CLK
REFout
(OPEN DRAIN)
16
Rx
VHF PDout
OUTPUT D
OUTPUT C
OUTPUT B
OUTPUT A
(OPEN DRAIN)
ZONE
15
fV
15–STAGE
N COUNTER
VHFin
15
HF/VHF SELECT
F SMPL
RESPONSE
HF PDout
10
22–STAGE F COUNTER
AND 24–BIT F REGISTER
11
INPUT D
6
9
INPUT C
7
(INTERNALLY
CONNECTED TO VDD/3)
INPUT B
+
A REGISTER
–
8
SAMPLE
AND HOLD
MUX
INPUT A
9
7
MC145173
2
PIN 17 = VDD
PIN 19 = VSS
I SMPL
VHF IFin
18
MUX CONTROL
HF IFin
PHASE/
FREQUENCY
DETECTOR
6–BIT ADC
CONVERSION RESULT + EOC
MOTOROLA
ABSOLUTE MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
– 0.5 to + 6.0
V
Vin
DC Input Voltage
– 0.5 to VDD + 0.5
V
Vout
DC Output Voltage
– 0.5 to VDD + 0.5
V
DC Input Current, per Pin
± 10
mA
Iout
DC Output Current, per Pin
± 20
mA
IDD
DC Supply Current, VDD and VSS Pins
± 30
mA
PD
Power Dissipation, per Package
Tstg
Storage Temperature
Iin
TL
300
mW
– 65 to + 150
°C
260
°C
Lead Temperature, 1 mm from Case
for 10 seconds
This device contains protection circuitry to
guard against damage due to high static voltages or electric fields. However, precautions
must be taken to avoid applications of any voltage higher than maximum rated voltages to
this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the
range VSS ≤ (Vin or Vout) ≤ VDD.
For proper termination of unused pins, see
the Pin Descriptions section.
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or
Pin Descriptions section.
DC ELECTRICAL CHARACTERISTICS (VDD = 4.5 to 5.5 V, Voltages Referenced to VSS, TA = – 40 to + 85°C)
Symbol
Parameter
Test Condition
Guaranteed
Limit
Unit
0.25 x VDD
V
VIL
VIH
Maximum Low–Level Input Voltage (Din, CLK, ENB)
0.65 x VDD
V
VIL
Maximum Low–Level Input Voltage
(Input D, HF IFin, VHF IFin, HFin, VHFin, OSCin)
dc coupled
0.3 x VDD
V
VIH
Minimum High–Level Input Voltage
(Input D, HF IFin, VHF IFin, HFin, VHFin, OSCin)
dc coupled
0.7 x VDD
V
0.3
V
V
Minimum High–Level Input Voltage (Din, CLK, ENB)
VHys
VTH
Minimum Hysteresis Voltage (CLK, ENB)
Threshold Voltage (INPUT C)
Vin Ramped Down from VDD
VOL
Maximum Low–Level Output Voltage
(Dout, OUTPUT A, OUTPUT B, OUTPUT C, OUTPUT D, HF PDout)
Iout = 20 µA
0.28 x VDD
to
0.38 x VDD
0.1
VOH
Minimum High–Level Output Voltage
(Dout, OUTPUT B, OUTPUT C, OUTPUT D, HF PDout, REFout)
Iout = –20 µA
VDD – 0.1
V
IOL
IOH
Minimum Low–Level Output Current (HF PDout)
Vout = 0.4 V
Vout = VDD – 0.4 V
0.36
mA
– 0.36
mA
IOL
IOH
Minimum Low–Level Output Current (Dout)
1.6
mA
– 1.6
mA
IOL
Minimum Low–Level Output Current
(OUTPUT B, OUTPUT C, OUTPUT D)
Vout = 1.0 V
2.0
mA
IOH
Minimum High–Level Output Current
(OUTPUT B, OUTPUT C, OUTPUT D)
Vout = VDD – 1.0 V
– 2.0
mA
IOL
IOH
Iin
Minimum Low–Level Output Current (OUTPUT A)
Vout = 1.0 V
Vout = VDD – 1.0 V
2.0
mA
Minimum High–Level Output Current (REFout)
– 1.75
mA
Maximum Input Leakage Current
(Din, CLK, ENB, OSCin, INPUT A, INPUT B, INPUT C, INPUT D)
Vin = VDD or VSS,
Device NOT in Standby**
± 1.0
µA
Maximum Input Current
(HFin, VHFin, HF IFin, VHF IFin)
Vin = VDD or VSS,
Device NOT in Standby
± 120
µA
IOZ
Maximum Output Leakage Current (HF PDout)
Vout = VDD or VSS,
Output in High–Impedance State
± 200
nA
IOZ
Maximum Output Leakage Current (VHF PDout)
Vout = 1.75 or VDD – 1.5 V,
Output in High–Impedance State
± 200
nA
IOZ
Maximum Output Leakage Current (REFout, OUTPUT A, Dout)
Vout = VDD or VSS,
Output in High–Impedance State
±2
µA
Iin
Minimum High–Level Output Current (HF PDout)
Minimum High–Level Output Current (Dout)
Vout = 0.4 V
Vout = VDD – 0.4 V
V
Continued on next page.
** While in Standby, the OSCin pin is pulled low by a weak on–chip FET.
MOTOROLA
MC145173
3
DC ELECTRICAL CHARACTERISTICS (continued) (VDD = 4.5 to 5.5 V, Voltages Referenced to VSS, TA = – 40 to + 85°C)
Parameter
Symbol
ISTBY
Idd
Test Condition
Guaranteed
Limit
Unit
Maximum Standby Supply Current
Vin on Din, CLK, INPUT A, INPUT
B, INPUT C, INPUT D = VDD or
VSS; Vin on ENB = VDD; Vin on
OSCin, HF IFin, VHF IFin = VSS or
Floating (ac coupled); Vin on HFin
= VDD or VSS or Floating (ac
coupled); Vin on VHFin = Floating
(ac coupled); Dout tied to VDD or
VSS through 100 kΩ resistor; Other Outputs Open
30
µA
Maximum Operating Supply Current
Vin on Din, CLK, INPUT A, INPUT
B, INPUT C, INPUT D = VDD or
VSS; Dout tied to VDD or VSS
through 100 kΩ resistor; Vin on
ENB = VDD; OSCin = 10.35 MHz
@ 1 V p–p; VHFin = 120 MHz @
210 mV p–p; VHF IFin = 10.7 MHz
@ 210 mV p–p
12
mA
ANALOG CHARACTERISTICS — CURRENT SOURCE/SINK OUTPUT — VHF PDout
(Iout ≤ 2.5 mA, VDD = 4.5 to 5.5 V, Voltages Referenced to VSS)
Parameter
Test Condition
Guaranteed
Limit
Unit
Maximum Source Current Variation (Part–to–Part)
Vout = 0.5 x VDD
± 20
%
Maximum Sink–vs–Source Mismatch (Note 3)
Vout = 0.5 x VDD
12
%
Output Voltage Range (Note 3)
Iout variation ≤ 20%
1.25 to VDD – 1.25 V
V
NOTES:
1. Percentages calculated using the following formula: (Maximum Value – Minimum Value)/Maximum Value.
2. See Rx Pin Description for external resistor value.
3. This parameter is guaranteed for any specific temperature within – 40 to + 85°C.
ADC CHARACTERISTICS (TA = – 40 to 85°C, VDD = 4.5 to 5.5 V, fOSC = 9.5 to 10.4 MHz)
Parameter
Test Condition
Guaranteed
Limit
Unit
6
Bits
Resolution
Conversion Time
Per Figure 1
3584
OSCin
Cycles
Maximum Nonlinearity
Vin = VSS + (0.1 x VDD) to
VDD – (0.09 x VDD)
± 1.5
LSBs
Din
SET BIT C7 HIGH
IN C REGISTER
ENB
CONVERSION TIME
EOC FLIP–FLOP OUTPUT
(INTERNAL)
ADC READY TO BE
READ VIA SERIAL PORT
Figure 1.
MC145173
4
MOTOROLA
AC INTERFACE CHARACTERISTICS
(VDD = 4.5 to 5.5 V, TA = – 40 to + 85°C, CL = 50 pF, Input tr = tf = 10 ns unless otherwise indicated)
Symbol
fclk
Parameter
Serial Data Clock Frequency (Note: Refer to CLK tw below)
Figure #
Guaranteed
Limit
Unit
2
dc to 2.1
MHz
tPLH, tPHL
Maximum Propagation Delay, CLK to Dout
2, 8
150
ns
tPLH, tPHL
Maximum Propagation Delay, ENB to Output B, Output C, Output D
6, 8
300
ns
tPLZ, tPZL
Maximum Propagation Delay, ENB to Output A
7, 9
300
ns
tPLZ, tPHZ
Maximum Disable Time, Dout Active to High Impedance
3, 9
400
ns
tPZL, tPZH
Access Time, Dout High Impedance to Active
tTLH, tTHL
Maximum Output Transition Time, Dout
Cin
Cout
3, 9
0 to 200
ns
CL = 50 pF
2, 8
100
ns
CL = 200 pF
2, 8
400
ns
Maximum Input Capacitance – Din, ENB, CLK
10
pF
Maximum Output Capacitance – Dout
10
pF
Figure #
Guaranteed
Limit
Unit
Minimum Setup and Hold Times, Din vs CLK
4
100
ns
Minimum Setup, Hold, and Recovery Times, ENB vs CLK
5
200
ns
Minimum Inactive–High Pulse Width, ENB
5
600
ns
Minimum Pulse Width, CLK
2
238
ns
Maximum Input Rise and Fall Times, CLK (Source Impedance ≤ 5 kΩ)
2
50
µs
TIMING REQUIREMENTS (TA = – 40 to + 85°C, Input tr = tf = 10 ns unless otherwise indicated)
Parameter
Symbol
tsu, th
tsu, th, trec
tw(H)
tw
tr, tf
AC ELECTRICAL CHARACTERISTICS (VDD = 4.5 to 5.5 V, TA = – 40 to + 85°C)
Guaranteed Range
Symbol
fin
Parameter
Input Frequency, HFin
Test Condition
Figure #
Min
Max
Unit
Vin ≥ 210 mV p–p Sine Wave,
N Counter set to divide ratio
such that fV ≤ 1 MHz (Note 1)
10
10
(Note 4)
40
MHz
Vin ≥ 2.2 V p–p Sine Wave,
N Counter same as above
10
1
40
MHz
fin
Input Frequency, VHFin
Vin ≥ 210 mV p–p Sine Wave,
N Counter set to divide ratio
such that fV ≤ 1 MHz (Note 1)
11
40
(Note 4)
130
MHz
fin
Input Frequency, OSCin
Externally driven with ac–coupled signal
(Note 2)
Vin ≥ 1.0 V p–p Sine Wave,
R Counter set to divide ratio
such that fR ≤ 1 MHz (Note 3)
12
2
(Note 4)
15
MHz
fXTAL
Crystal Frequency, OSCin and OSCout
(Note 2)
C1 ≤ 30 pF, C2 ≤ 30 pF,
Includes Stray Capacitance,
R Counter set to divide ratio
such that fR ≤ 1 MHz (Note 3)
13
2
15
MHz
fin
Input Frequency, HF IFin
Vin ≥ 85 mV p–p Sine Wave,
K bit cleared low or set high
10
400
500
kHz
fin
Input Frequency, VHF IFin
Vin ≥ 85 mV p–p Sine Wave
10
8
(Note 4)
20
MHz
fout
Output Frequency, REFout
CL = 20 pF,
Vout ≥ 1.5 V p–p
14, 15
dc
10.4
MHz
NOTES:
1. fV is the output signal of the N Counter.
2. The ADC is guaranteed over an OSCin range of 9.5 to 10.4 MHz only.
3. fR is the output signal of the R Counter.
4. For operation below this frequency, use dc coupling with a signal level of at least VIL to VIH. See Pin Description.
MOTOROLA
MC145173
5
SWITCHING WAVEFORMS
tf
tr
VDD
90%
CLK 50%
10%
VSS
VSS
tw
tPZL
tw
1/fclk
Dout
tPLH
tPLZ
HIGH
IMPEDANCE
50%
10%
tPHL
tPZH
90%
50%
10%
Dout
VDD
50%
ENB
90%
50%
Dout
tTLH
tPHZ
HIGH
IMPEDANCE
tTHL
Figure 2.
Figure 3.
tw(H)
VDD
VALID
ENB
VDD
50%
50%
Din
tsu
VSS
tsu
th
VDD
50%
CLK
VSS
th
trec
VDD
CLK
50%
FIRST
CLK
VSS
Figure 4.
LAST
CLK
VSS
Figure 5.
50%
ENB
VSS
tPZL
VDD
VSS
tPLZ
OUTPUT B,
OUTPUT C,
OUTPUT D
50%
OUTPUT A
Figure 6.
HIGH
IMPEDANCE
10%
Figure 7.
TEST POINT
TEST POINT
5 kΩ
CL *
*Includes all probe and fixture capacitance.
Figure 8. Test Circuit
MC145173
6
HIGH
IMPEDANCE
50%
OUTPUT A
tPLH, tPHL
DEVICE
UNDER
TEST
VDD
50%
ENB
DEVICE
UNDER
TEST
CL *
CONNECT TO VDD
WHEN TESTING tPLZ
AND tPZL.
CONNECT TO VSS
WHEN TESTING tPHZ
AND tPZH.
*Includes all probe and fixture capacitance.
Figure 9. Test Circuit
MOTOROLA
0.01 µF
SINE WAVE
GENERATOR
Vin
0.01 µF
SINE WAVE
GENERATOR
INPUT
VHFin
MC145173
MC145173
Vin
50 Ω
50 Ω*
VSS
VDD
VSS
V+
VDD
V+
* Characteristic impedance
Figure 11. Test Circuit
Figure 10. Test Circuit
0.01 µF
SINE WAVE
GENERATOR
OSCin
OSCin
50 Ω
10 MΩ
Vin
C1
MC145173
MC145173
OSCout
VSS
VDD
OSCout
VSS VDD
C2
V+
Figure 12. Test Circuit
V+
Figure 13. Test Circuit
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
1/f REFout
REFout
1 kΩ
CL *
* Includes all probe and
fixture capacitance.
50%
Figure 14. Switching Waveform
MOTOROLA
Figure 15. Test Circuit
MC145173
7
PIN DESCRIPTIONS
DIGITAL INTERFACE PINS
CLK typically switches near 45% of V DD and has a
Schmitt–triggered input buffer. See the last paragraph of Din
for more information.
Din
Serial Data Input (Pin 3)
The bit stream begins with the most significant bit (MSB)
and is shifted in on the low–to–high transition of CLK. The bit
pattern is 1 byte (8 bits) long to access the C register, 2 bytes
(16 bits) to access the N register, or 3 bytes (24 bits) to access the R register. (See Table 1.) The values in the C, N,
and R registers do not change during shifting because the
transfer of data to the registers is controlled by ENB.
The bit stream needs neither address nor steering bits due
to the innovative BitGrabber registers. Therefore, all bits in
the stream are available to be data for the three registers.
Random access of any register is provided (i.e., the registers
may be accessed in any sequence). Data is retained in the
registers over a supply range of 4.5 to 5.5 V. The formats are
shown in Figures 17, 18, and 20.
Din typically switches near 45% of VDD for good noise immunity. This input can be directly interfaced to CMOS devices with outputs guaranteed to switch near rail–to–rail.
When interfacing to NMOS or TTL devices, either a level
shifter (MC74HC14A, MC14504B) or pull–up resistor of 1 to
10 kΩ must be used. Parameters to consider when sizing the
resistor are worst–case IOL of the driving device, maximum
tolerable power consumption, and maximum data rate.
Table 1Write–Only Registers
(MSBs are shifted in first, C0, N0, and R0 are the LSBs)
Number
of Clocks
Accessed
Register
Bit
Nomenclature
8
16
24
Other Values ≤ 32
Values > 32
C Register
N Register
R Register
Not Allowed
Not Allowed
C7, C6, C5, . . ., C0
N15, N14, N13, . . ., N0
R23, R22, R21, . . ., R0
Table 2Read–Only Registers
(MSBs are shifted out first; A7 and F23 are the MSBs)
Number
of Clocks
Register
Bit
Nomenclature
8, 9, or 16
A Register
A7, A6, A5, . . ., A0, A#
24
F Register
F23, F22, F21, . . ., F0
CLK
Serial Data Clock Input (Pin 4)
Low–to–high transitions on Clock shift bits available at Din,
while high–to–low transitions shift bits from Dout. The chip’s
24–1/2–stage shift register is static, allowing clock rates
down to dc in a continuous or intermittent mode.
Eight clock cycles are required to access the C register.
Sixteen clock cycles are needed for the N register. 24 cycles
are used to access the R register. (See Table 1 and Figures
17, 18, and 20.)
The A register is read using 8, 9, or 16 clock cycles. The F
register is read using 24 clocks. (See Table 2 and Figures 21
and 22.)
MC145173
8
NOTE
To guarantee proper operation of the power–on
reset (POR) circuit, the CLK pin must be held at
the potential of either the VSS or VDD pin during
power up. That is, the CLK input should not be
floated or toggled while the VDD pin is ramping
from 0 to at least 4.5 V. If control of the CLK pin is
not practical during power up, then the RST bit in
the R Register must be utilized. See the R Register Bits section.
ENB
Active–Low Enable Input (Pin 2)
This pin is used to activate the serial interface to allow the
transfer of data to/from the device. When ENB is in an inactive high state, shifting is inhibited, Dout is forced to the high–
impedance state, and the port is held in the initialized state.
To transfer data to and from the device, ENB (which must
start inactive high) is taken low, a serial transfer is made via
Din, Dout, and CLK, and ENB is taken back high. The low–to–
high transition on ENB transfers data to the C, N, or R write–
only registers depending on the data stream length per
Table 1.
To minimize standby current, ENB must be high.
CAUTION
Transitions on ENB must not be attempted while
CLK is high. This puts the device out of synchronization with the microcontroller. Resynchronization occurs when ENB is high and CLK is low.
This input is also Schmitt–triggered and switches near
45% of VDD, thereby minimizing the chance of loading erroneous data into the registers. See the last paragraph of Din
for more information.
Dout
Three–State Serial Data Output (Pin 5)
Data is transferred out of the 24–1/2 stage shift register
through Dout on the high–to–low transition of CLK. The bit
stream begins with the MSB. The bit pattern is 1 byte, 9 bits,
or 2 bytes long to read the A register. The F register’s data is
contained in 3 bytes. (See Table 2.)
Before the A register can be read, the Read A bit must be
set in the C register. Likewise, the Read F bit must be set to
read the F register.
To minimize supply current during the standby state, the
Dout pin should not be floated. A pull–down resistor to VSS or
pull–up resistor to VDD should be used. The value can be
50 kΩ to 100 kΩ.
GENERAL–PURPOSE DIGITAL I/O PINS
Input C
Digital Input (Pin 7)
Input C is a general–purpose digital input which may be
used for MCU port expansion. The state of this input is indicated by the In C bit in the A register. (See Figure 21.)
MOTOROLA
The switch point is precisely controlled by use of a
comparator. The reference for the comparator is internally
set to approximately 33% of VDD. The input has a small
amount of hysteresis voltage (approximately 50 mV).
If not used, this pin should be tied to VDD or VSS.
Input D
Digital Input (Pin 6)
Input D is a general–purpose digital input which may be
used for MCU port expansion. The state of this input is indicated by the In D bit in both the A and F registers. That is, the
state of the pin may be read from either register. (See Figures 21 and 22.)
This pin is a standard CMOS input with a switch point at
approximately 50% of VDD. Input D has a hysteresis voltage
of approximately 600 mV.
If not used, this pin should be tied to VDD or VSS.
Output A
Open–Drain Digital Output (Pin 12)
Output A is a general–purpose digital output which may be
used for MCU port expansion. An N–channel MOSFET tied
to VSS is used to drive this open–drain output. Thus, an external pull–up device is required at this pin. The state of this
output is determined by the Out A bit in the C register. (See
Figure 17.)
Upon power–up, this pin is low. If not used, Output A
should be tied to VSS or floated.
Output B
Digital Output (Pin 13)
Output B is a general–purpose digital output which may be
used for MCU port expansion. This is a standard totem–pole
(push–pull) CMOS output. The state of this output is determined by the Out B bit in the C register. (See Figure 17.)
Upon power–up, this pin is low. If not used, Output B
should be floated.
Output C
Digital Output (Pin 14)
Output C is a general–purpose digital output which may be
used for MCU port expansion. This is a standard totem–pole
(push–pull) CMOS output. The state of this output is determined by the Out C bit in the C register. (See Figure 17.)
Upon power–up, this pin is low. If not used, Output C
should be floated.
Output D
Digital Output (Pin 22)
Output D is a general–purpose digital output which may be
used for MCU port expansion. This is a standard totem–pole
(push–pull) CMOS output. The state of this output is determined by the Out D bit in the R register. (See Figure 18.)
Upon power–up, this pin is low. If not used, Output D
should be floated.
MOTOROLA
ADC INPUT PINS
Input A, Input B
Analog Inputs (Pins 9, 8)
These are inputs to the 2–channel multiplexer which feeds
the 6–bit analog–to–digital converter (ADC). The selected
channel is determined by the Chan bit in the C register.
Each pin is a high–impedance input which appears as
a mostly–capacitive load of approximately 6 pF.
If not used, these pins should be tied to VSS or VDD.
REFERENCE PINS
OSCin /OSCout
Reference Oscillator Input/Output (Pins 1, 24)
These pins form a reference oscillator when connected to
terminals of an external parallel–resonant crystal. Frequency–setting capacitors of appropriate values as recommended by the crystal supplier are connected from each pin
to ground (up to a maximum of 30 pF each, including stray
capacitance). An external feedback resistor of 1 to 10 MΩ is
connected directly across the pins to ensure linear operation
of the amplifier. The MC145173 is designed to operate with
crystals from 2 to 15 MHz. However, frequencies are restricted to 9.5 to 10.4 MHz when the ADC is utilized. (See
Figure 13.)
If desired, an external clock source can be ac coupled to
OSCin. A 0.01 µF coupling capacitor is used for measurement purposes and is the minimum size recommended for
applications. The input capacitance of the OSCin pin is
approximately 6 pF. An external feedback resistor of approximately 10 MΩ is required across the OSCin and OSCout pins
in the ac–coupled case. (See Figure 12.) OSCout is an internal node on the device and should not be used to drive any
loads (i.e., OSCout is unbuffered). However, the buffered
REFout is available to drive external loads in the HF mode.
The external signal level must be at least 1 V p–p; the minimum and maximum frequencies are given in the AC Electrical Characteristics table. These frequencies apply for R
Counter divide ratios as indicated in the table. For very small
ratios, the maximum frequency is limited to the divide ratio
times 1 MHz (Reason: the phase/frequency detectors are
limited to a maximum input frequency of 1 MHz).
If an external source is available which swings from at
least the VIL to VIH levels listed in the DC Electrical Characteristics table, then dc coupling can be used. In the dc–
coupled case, no external feedback resistor is needed.
OSCout must be a No Connect to avoid loading an internal
node on the MC145173, as noted above. For frequencies below 2 MHz, a signal level of at least VIL and VIH is needed,
and dc coupling must be used. The R counter is a static
counter and may be operated down to dc. However, wave
shaping by a CMOS buffer may be required to ensure fast
rise and fall times into the OSCin pin at these low frequencies.
Each rising edge on the OSCin pin causes the R counter to
decrement by one. In the standby mode, OSCin is pulled low
by an on–chip FET.
REFout
Open–Drain Reference Frequency Output (Pin 23)
This output is the buffered output of the crystal–generated
reference frequency or externally provided reference source.
MC145173
9
A P–channel MOSFET tied to VDD is used to drive this open–
drain output. Thus, an external pull–down device is required
at this pin. This output is disabled and assumes the high–impedance state in the VHF mode per bit HF/VHF in the R register. (See Figure 18.)
REFout is capable of operation to 10.4 MHz; see the AC
Electrical Characteristics table.
If unused, the pin may be floated or tied to VDD.
FREQUENCY COUNTER INPUT PINS
HF IFin
HF Intermediate–Frequency Input (Pin 10)
This pin feeds an on–chip amplifier. The amp drives the F counter
when the HF/VHF bit in the R register is low. (See Figure 18.) The
signal driving this pin is normally sourced from the IF (intermediate
frequency) circuit in the radio and is ac coupled. The input capacitance is approximately 6 pF.
This input is optimized for use with frequencies around
450 kHz. An on–chip low–pass filter is employed to roll off response above 1 MHz. In addition, for further suppression of high–
frequency signals, the Kuligowski Acceptor Circuit may be
engaged via the K bit in the R register. This is a digital integrator
which allows acceptance of frequencies only below the frequency at
the OSCin pin divided by 8.
In the standby mode, HF IFin is pulled low by an on–chip
FET. If not used, this pin should be tied to VSS.
VHF IFin
VHF Intermediate–Frequency Input (Pin 11)
This pin feeds an on–chip amplifier. The amp drives the F
counter when the HF/VHF bit in the R register is high. (See
Figure 18.) The signal driving this pin is normally sourced
from the IF circuit in the radio and is ac coupled. The input
capacitance is approximately 6 pF. Usually, the frequency of
the signal driving this pin is about 10.7 MHz.
For signals which swing from at least the VIL to VIH levels
listed in the DC Electrical Characteristics table, dc coupling may be used. Also, for signals less than the minimum
frequencies in the AC Electrical Characteristics table, dc
coupling with at least VIL and VIH levels is a requirement. The
F counter is a static counter and may be operated down to
dc. However, wave shaping by a CMOS buffer may be required to ensure fast rise and fall times into the VHF IFin pin.
In the standby mode, VHF IFin is forced to a high–impedence state. If not used, this pin should be tied to VSS.
LOOP PINS
HFin, VHFin
High Frequency Input,
Very High Frequency Input (Pins 16, 15)
These pins feed on–chip amplifiers which drive the N
counter; the HF/VHF bit in the R register determines which
input is selected. (See Figure 18.) These signals are normally sourced from external voltage–controlled oscillators
(VCOs), and are ac–coupled. (See Figures 10 and 11.) The
input capacitance is approximately 6 pF. For small divide ratios, the maximum frequency is limited to the divide ratio
times 1 MHz. (Reason: the phase/frequency detectors are
limited to a maximum frequency of 1 MHz.)
For signals which swing from at least the VIL to VIH levels
listed in the DC Electrical Characteristics table, dc coupling may be used. Also, for signals less than the minimum
MC145173
10
frequencies in the AC Electrical Characteristics table, dc
coupling with at least VIL and VIH levels is a requirement. The
N counter is a static counter and may be operated down to
dc. However, wave shaping by a CMOS buffer may be required to ensure fast rise and fall times into the HFin and
VHFin pins.
Each rising edge on these pins cause the N counter to
decrement by one.
In the standby mode, HFin is forced to a high–impedence
state, and VHFin is pulled low by an on–chip FET. If not used,
these pins should be tied to VSS.
HF PDout
Single–Ended Phase/Frequency Detector Output
(Pin 18)
This is a three–state output for use as a loop error signal
when combined with an external low–pass filter. Through use
of a Motorola patented technique, the detector’s dead zone
has been eliminated. Therefore, the phase/frequency detector is characterized by a linear transfer function. The operation of the phase/frequency detector is described below and
is shown in Figure 16.
POL bit (R23) in the R register = low (see Figure 18)
Frequency of fV > fR or Phase of fV Leading fR: negative
pulses from high impedance
Frequency of fV < fR or Phase of fV Lagging fR: positive
pulses from high impedance
Frequency and Phase of fV = fR: essentially high–impedance state; voltage at pin determined by loop filter
POL bit (R23) = high
Frequency of fV > fR or Phase of fV Leading fR: positive
pulses from high impedance
Frequency of fV < fR or Phase of fV Lagging fR: negative
pulses from high impedance
Frequency and Phase of fV = fR: essentially high–impedance state; voltage at pin determined by loop filter
This output is enabled and disabled via the HF/VHF bit in
the R register. HF PDout is forced to the high–impedance
state when disabled. This pin should be floated when it is not
used.
VHF PDout
Single–Ended Phase/Frequency Detector Output
(Pin 21)
This is a three–state current–source/sink output for use as
a loop error signal when combined with an external low–pass
filter. The phase/frequency detector is characterized by a linear transfer function. The operation of the phase/frequency
detector is described below and is shown in Figure 16.
POL bit (R23) in the R register = low (see Figure 18)
Frequency of fV > fR or Phase of fV Leading fR: current–
sinking pulses from a floating state
Frequency of fV < fR or Phase of fV Lagging fR: current–
sourcing pulses from a floating state
Frequency and Phase of fV = fR: essentially a floating
state; voltage at pin determined by loop filter
POL bit (R23) = high
Frequency of fV > fR or Phase of fV Leading fR: current–
sourcing pulses from a floating state
Frequency of fV < fR or Phase of fV Lagging fR: current–
sinking pulses from a floating state
MOTOROLA
Frequency and Phase of fV = fR: essentially a floating
state; voltage at pin determined by loop filter
This output is enabled and disabled via the HF/VHF bit in
the R register. VHF PDout is forced to the floating state when
disabled.
If not used, this pin should be a no connect.
Rx
External Resistor (Pin 20)
A resistor is tied between this pin and VSS. This sets a reference current which determines the current delivered
(I PDout) at the current source/sink phase/frequency detector
output, VHF PDout. For a nominal current of 2.2 mA at the
VHF PDout pin, a 15 kΩ resistor is utilized.
In addition, the Rx pin must be bypassed to VDD with a
low–inductance 0.1 µF capacitor mounted very close to
these pins. Lead lengths on the capacitor should be minimized.
If the VHF PDout pin is not used, the Rx pin may be floated.
POWER SUPPLY
VDD
Most–Positive Supply Potential (Pin 17)
This pin may range from 4.5 to 5.5 V with respect to VSS.
For optimum performance, VDD should be bypassed to
VSS using low–inductance capacitor(s) mounted very close
to the MC145173. Lead lengths and traces to the capacitor(s) should be minimized. (The very fast switching speed of
the device can cause excessive current spikes on the power
leads if they are improperly bypassed.)
Power supply ramp up time should be less than 20 ms
from 0 to 4.5 V. If the ramp up time exceeds 20 ms, the POR
circuit may not function and the outputs will be in an unknown
state. The RST bit must be used in this case.
VSS
Most–Negative Supply Potential (Pin 19)
This pin is usually ground.
fR
REFERENCE
OSCin ÷ R
VH
VL
fV
FEEDBACK
(fin ÷ N)
VH
VL
*
VH
HIGH IMPEDANCE
HF PDout
VL
*
VHF PDout
SOURCING CURRENT
FLOAT
SINKING CURRENT
VH = High voltage level
VL = Low voltage level
*At this point, when both fR and fV are in phase, both the source and sink drivers are turned on for a short duration. For exceptions,
see Figure 19.
NOTE: HF PDout and VHF PDout are shown with the polarity bit (POL) = low; see Figure 18 for POL.
Figure 16. Phase/Frequency Detectors Output Waveforms
MOTOROLA
MC145173
11
C REGISTER BITS
I SMPL
Input Sample (C7)
RESERVED
Reserved Bit (C5)
This bit must be kept low.
When the input sample bit is cleared low, the ADC is held
in the initialized state. When I SMPL is set high, the ADC
converts the input channel selected by bit C4, and holds the
conversion value. When the ADC is read via the serial port,
I SMPL must remain high. Otherwise, the EOC bit is reset
low. The previous converison value is not lost, however.
I SMPL may be set at any time, even if the F SMPL bit in
the R register is already set. That is, an A/D conversion may
be initiated during an F count. The state of C4 may not be
changed simultaneously with C7 being set high.
I SMPL is cleared low upon power up. However, this bit is
not automatically cleared low after a conversion and read sequence.
CHAN
Channel Select for ADC (C4)
When the channel bit is low, Input A is selected to be converted by the ADC. When the bit is high, Input B is selected.
The state of C4 may not be changed simultaneously with the
I SMPL bit being set high.
READ F
Read F Register (C3)
Setting the Read F register bit high causes the frequency
counter’s value and the state of Input D to be parallel loaded
into the serial port’s shift register. ENB is then taken low and
24 bits are shifted from the Dout pin. (See Figure 22.)
While the Read F bit is set, writing to any register is inhibited. After the read occurs (F register data shifted out), C3 is
automatically cleared low. When C3 is low, the shift register
is not parallel loaded and any of the registers of Table 1 may
be written.
Read F should not be set when Read A is set. If both Read
F and Read A are set simultaneously, a Read A Register operation is performed and the Read F Register request is ignored.
Read F is cleared low at power up.
READ A
Read A Register (C6)
Setting the Read A register bit high causes the ADC’s value and the states of Inputs C and D to be parallel loaded into
the serial port’s shift register. ENB is then taken low and either 8, 9, or 16 bits are shifted from the Dout pin. If only 8 bits
are shifted, the state of Input D is not read. To read Input D,
use either a 9 or 16 bit shift. (See Figure 21.) Alternatively,
Input D may be read from the F Register.
While the Read A bit is set, writing to any register is inhibited. After the read occurs (A register data shifted out), C6 is
automatically cleared low. When C6 is low, the shift register
is not parallel loaded and any of the registers of Table 1 may
be written.
Read A should not be set when Read F is set. If both Read
A and Read F are set simultaneously, a Read A Register operation is performed and the Read F Register request is ignored.
Read A is cleared low at power up.
OUT C, OUT B, OUT A
Output C, Output B, Output A Control (C2, C1, C0)
When Out A, Out B, or Out C is cleared low, the Output A,
Output B, or Output C pins are forced low, respectively.
When set high, the associated output is forced high, except
for Output A which is forced to the high–impedance state.
These bits are cleared low at power up.
ENB
1
CLK
2
3
4
5
6
7
MSB
Din
C7
8
LSB
C6
I SMPL
READ A
C5
C4
C3
C2
RESERVED
READ F
CHAN
OUT C
C1
C0
OUT B
OUT A
NOTE: This is a write–only register.
Figure 17. C Register Access and Format (8 Clock Cycles are Used)
MC145173
12
MOTOROLA
Figure 18. R Register Access and Format (24 Clock Cycles Are Used)
MOTOROLA
MC145173
13
POL
R23
MSB
1
RST
R22
R21
3
HF/VHF
2
K
R20
4
STBY
R19
5
φDET1
R18
6
φDET0
R17
7
R16
8
OUT D
NOTE: This is a write-only register.
*Direct access to reference side of phase/frequency detectors.
D in
CLK
ENB
ACQ
R15
9
F SMPL
R14
10
12
0
0
0
0
0
0
0
0
.
.
.
1
1
R12
BINARY
VALUE
0
0
0
0
0
0
0
0
.
.
.
1
1
R13
11
0
0
0
0
0
0
0
0
.
.
.
F
F
R10
14
0
1
2
3
4
5
6
7
.
.
.
E
F
R9
15
HEXADECIMAL VALUE
0
0
0
0
0
0
0
0
.
.
.
F
F
R11
13
R7
17
R6
R COUNTER =
R COUNTER =
19
R5
R4
20
R3
21
R2
DECIMAL EQUIVALENT
÷ 16,382
÷ 16,383
5
6
7
1*
18
NOT ALLOWED
R COUNTER = ÷
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
R COUNTER = ÷
R COUNTER = ÷
R COUNTER = ÷
R8
16
22
R1
23
R0
LSB
24
R REGISTER BITS
Do not attempt to write to the R register when both the F
counter and A/D converter are simultaneously active.
POL
Polarity (R23)
The polarity bit controls both phase/frequency detector
outputs. When low, the detector outputs are per Figure 16.
When R23 is high, the output polarity of both phase/frequency detectors is inverted.
Upon power up, this bit is forced low.
RST
Reset (R22)
pulling the OSCin pin low). The HFin, VHFin, HF IFin, and
VHF IFin inputs are shut off, which inhibits the counters from
toggling. Finally, the comparator and ADC are turned off.
Data is retained in the C, N, and R registers during standby.
CAUTION
Setting the STBY bit high aborts any frequency
count or A/D conversion which may be in
progress.
STBY is forced high upon power up.
φdet1, φdet0
Phase/Frequency Detector Response (R18, R17)
When high, this bit resets the device except for the serial
port. RST is kept low for normal operation. However, if a
power glitch occurs which does not reduce the power supply
voltage to 0 volts, the R register should be written twice with
the RST bit set high. Also, if the CLK pin is floating upon power up, the RST bit should be written high twice for initialization.
Controls the VHF phase/frequency detector response per
Table 3. The HF phase/frequency detector is unaffected.
These bits also control several test modes as shown in
Table 4.
NOTE
The on–chip POR (power–on reset) circuit resets
the device during a cold start, if the CLK pin is not
floating or toggled during supply ramp up to 4.5 V.
When cleared low, the Output D pin is forced low. When
high, Output D is high.
This bit is cleared low upon power up.
This bit is automatically cleared low after the chip is reset.
HF/VHF
HF/VHF Band Selection (R21)
When this bit is low, the HFin and HF IFin inputs are enabled, along with the HF PDout pin. The VHF PDout pin is
forced to the float condition and VHFin is pulled low with an
on–chip FET.
When this bit is high, the VHFin and VHF IFin inputs are
enabled, along with the VHF PDout pin. Both the HF PDout
and HFin pins are forced to the high–impedance state, and
REFout is disabled (high–impedance).
K
HF IFin Response (R20)
This bit is used to control the input response of the HF IFin
pin.
When the K bit is high, the Kuligowski acceptor circuit is
engaged, which allows acceptance of signals only below the
frequency at the OSCin pin divided by 8. Use of this digital
integrator allows further suppression of high–frequency signals into the HF IFin pin.
In the VHF mode, the K bit should be kept low.
STBY
Standby (R19)
If STBY is low, the chip is in the normal mode of operation.
When this bit is high, the device is placed in the standby
state for reduced power consumption. In standby, both
phase/frequency detector outputs and the REFout pin are
forced to the high–impedance state, the Rx reference current
is shut off, and the oscillator is stopped (via an on–chip FET
MC145173
14
Out D
Output D Control (R16)
ACQ
Acquisition Window (R15)
This bit determines the frequency counter (F counter)
acquisition window. A low level is for a narrow window, and a
high is for a wide window.
The formula to determine the window is
t
+2
(19
) 2a)
f
where t is the acquisition window in seconds, a is the logic
level of the ACQ bit (0 or 1), and f is the frequency at the
OSCin pin in hertz.
F SMPL
Frequency Sample (R14)
When this bit is low, the frequency counter (F counter) is
initialized to all highs (ones).
When F SMPL is set high, the frequency counter “rolls
over” to zero, increments for one acquisition window, and
then holds the count. When the frequency counter is read via
the serial port, R14 must remain high; otherwise, the frequency counter is initialized and outputs all ones.
F SMPL must not be set high if I SMPL is already high.
That is, a frequency count cannot be initiated if an A/D conversion is in progress.
This bit is cleared low upon power up. However, this bit is
not automatically cleared low after a frequency count and
read sequence.
R13 to R0
R Counter Divide Ratio
These bits control the divide ratio of the R counter per Figure 18.
MOTOROLA
Table 3. VHF PDout Response
N Register
Bit
R Register Bits
VHF Phase
Detector
Response
(Nominal)
Ph
D
R
(N
i l)
N15
R18
R17
L
L
L
Linear response, no low–gain region
L
L
H
Low–gain region, 5 ns wide
L
H
L
Low–gain region, 10 ns wide
L
H
H
Low–gain region, 15 ns wide
H
L
L
Linear response, no dead zone
H
L
H
Dead zone, 5 ns wide
H
H
L
Dead zone, 10 ns wide
H
H
H
Dead zone, 15 ns wide
NOTES:
1. L = Low Level, H = High Level.
2. See Figure 19.
LOW–PASS FILTER
OUTPUT VOLTAGE
LINEAR
RESPONSE
NONLINEAR RESPONSES
LOW
GAIN
REGION
PHASE ERROR
DEAD ZONE
OR
LOW–GAIN REGION
NOTES:
1. Output HF PDout always has a linear transfer characteristic. Therefore, for HF PDout, the Dead Zone = 0 ns.
2. Output VHF PDout has a response which is programmable via bits φdet1 (R18), φdet0 (R17), and Zone (N15).
See Table 3.
3. The gain in the “low–gain region” is reduced to 7% of the gain in the other region.
Figure 19. VHF PDout Transfer Characteristic
Table 4. Test Modes
R Register Bits
Pin Configurations
R21
R18
R17
Pin 12 — OUTPUT A
Pin 13 — OUTPUT B
L
L
L
OUTPUT A, normal configuration
OUTPUT B, normal configuration
L
L
H
fV, N counter output — HFin feeds the counter input
OUTPUT B, normal configuration
L
H
L
fV, N counter output — VHFin feeds the counter input
OUTPUT B, normal configuration
L
H
H
OUTPUT A, normal configuration
fR, R counter output
H
X
X
OUTPUT A, normal configuration
OUTPUT B, normal configuration
NOTE: L = Low Level, H = High Level, X = Don’t Care.
MOTOROLA
MC145173
15
ENB
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MSB
N15
Din
16
LSB
N14
N13
N12
N11
N10
ZONE
(SEE TABLE 3)
N9
N7
N6
N5
N4
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
5
6
7
8
9
A
B
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
N COUNTER =
N COUNTER =
N COUNTER =
N COUNTER =
÷ 40
÷ 41
÷ 42
÷ 43
7
7
F
F
F
F
E
F
N COUNTER =
N COUNTER =
÷ 32,766
÷ 32,767
⋅⋅
⋅
⋅⋅
⋅
OCTAL VALUE
N8
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
HEXADECIMAL VALUE
N3
N2
N1
N0
DECIMAL EQUIVALENT
NOTE: This is a write–only register.
Figure 20. N Register Access and Format (16 Clock Cycles Are Used)
MC145173
16
MOTOROLA
A REGISTER BITS
EOC
End of Conversion (A7)
ADC CONVERSION VALUE
A/D Conversion Value (A5 – A0)
The end of conversion bit is set high when the analog–to–
digital conversion is complete. This high level indicates that
the A/D conversion value read via the serial port is valid.
EOC is cleared low when the I SMPL bit in the C register is
cleared low.
These bits contain the analog–to–digital conversion result
in binary format. A5 is the MSB of the value; A0 is the LSB.
IN D
Input D Level (A#)
In D indicates the state of the Input D pin. A high level on
the Input D pin causes the In D bit to be high. A low level on
the pin causes a low level to be read on In D. The digital value is stored at the falling edge of ENB on the read cycle.
A 9– or 16–bit shift must be used to read the In D bit from
the A register. Optionally, the In D bit may be read from the F
register.
IN C
Input C Level (A6)
In C indicates the state of the Input C pin. A high level on
the Input C pin causes the In C bit to be high. A low level on
the pin causes a low level to be read on In C. The digital value is stored at the falling edge of ENB on the read cycle.
ENB
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MSB
Dout
A7
A6
A5
A4
IN C
A3
A2
A1
A0
A#
ADC
CONVERSION
VALUE
EOC
x
x
x
IN D
x
x
x
x
DON’T CARE
ENB
CLK
1
2
3
4
5
6
7
8
9
MSB
Dout
A7
A6
A5
A4
A3
IN C
A2
A1
A0
ADC
CONVERSION
VALUE
EOC
A#
IN D
ENB
CLK
1
2
3
4
5
6
7
8
MSB
Dout
A7
A6
IN C
EOC
NOTE: This is a read–only register.
A5
A4
A3
A2
A1
A0
ADC
CONVERSION
VALUE
Figure 21. A Register Formats (8, 9, or 16 Clock Cycles May Be Used)
MOTOROLA
MC145173
17
F REGISTER BITS
F0
F1
23
F2
22
F3
21
F4
20
F5
19
F6
18
F
0
0
0.
.
.
F
F
F8
F
0
0
0.
.
.
F
F
F9
F
0
0
0.
.
.
F
F
F10
F
0
0
0.
.
.
F
F
F11
HEXADECIMAL VALUE
F
0
1
2.
.
.
D
E
F7
17
16
15
14
13
1
0
0
0.
.
.
1
1
F13
F14
BINARY
VALUE
1
0
0
0.
.
.
1
1
F12
12
11
10
F15
9
F16
8
F17
7
F18
6
F20
CC
IN D
F21
F22
F23
Dout
MSB
NOTE: This is a read-only register.
F19
5
4
3
2
1
CLK
ENB
FREQUENCY COUNTER HAS INCREMENTED BY 4,194,302
FREQUENCY COUNTER HAS INCREMENTED BY 4,194,303
In D indicates the state of the Input D pin. A high level on
the Input D pin causes the In D bit to be high. A low level on
the pin causes a low level to be read on In D.
Optionally, the In D bit may be read from the A register.
INITIAL VALUE OF FREQUENCY COUNTER
FREQUENCY COUNTER HAS INCREMENTED BY 1
FREQUENCY COUNTER HAS INCREMENTED BY 2
FREQUENCY COUNTER HAS INCREMENTED BY 3
The count complete bit is set high when the frequency
counter has gone through a count cycle for a complete acquisition window. This high level indicates that the count read
via the serial port is valid.
CC is cleared low when the F SMPL bit in the R register is
cleared low.
LSB
IN D
Input D Level (F22)
24
CC
Count Complete (F23)
Figure 22. F Register Format (24 Clock Cycles Are Used)
MC145173
18
MOTOROLA
CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a reference frequency to Motorola’s CMOS frequency synthesizers.
Use of a Hybrid Crystal Oscillator
Commercially available temperature–compensated crystal
oscillators (TCXOs) or crystal–controlled data clock oscillators provide very stable reference frequencies. An oscillator
capable of CMOS logic levels at the output may be direct or
dc coupled to OSCin. If the oscillator does not have CMOS
logic levels on the outputs, capacitive or ac coupling to
OSCin must be used. (See Figure 12.)
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem Electronic Engineers Master Catalog, the Gold Book, or similar
publications.
shift in operating frequency. R1 in Figure 23 limits the drive
level. The use of R1 is not necessary in most cases.
To verify that the maximum dc supply voltage does not
cause the crystal to be overdriven, monitor the output
frequency at the OSCout pin. An active probe should be used
to minimize loading. The frequency should increase very
slightly as the dc supply voltage is increased. An overdriven
crystal decreases in frequency or becomes unstable with an
increase in supply voltage. The operating supply voltage
must be reduced or R1 must be increased in value if the
overdriven condition exists. The user should note that the oscillator start–up time is proportional to the value of R1.
Through the process of supplying crystals for use with CMOS inverters, many crystal manufacturers have developed expertise in
CMOS oscillator design with crystals. Discussions with such manufacturers can prove very helpful. (See Table 5)
FREQUENCY
SYNTHESIZER
Design an Off–Chip Reference
The user may design an off–chip crystal oscillator using
discrete transistors or ICs specifically developed for crystal
oscillator applications, such as the MC12061 MECL device.
The reference signal from the MECL device is ac coupled to
OSCin. (See Figure 12.) For large amplitude signals (standard CMOS logic levels), dc coupling may be used.
OSCin
R1*
C1
Use of the On–Chip Oscillator Circuitry
The on–chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure 23.
The crystal should be specified for a loading capacitance
(CL) which does not exceed 20 pF when used at the highest
operating frequency. Larger CL values are possible for lower
frequencies. Assuming R1 = 0 Ω, the shunt load capacitance
(CL) presented across the crystal can be estimated to be:
CL =
Figure 23. Pierce Crystal Oscillator Circuit
Ca
OSCin
MOTOROLA
OSCout
Cin
Cout
Cstray
where
The oscillator can be “trimmed” on–frequency by making a
portion or all of C1 variable. The crystal and associated components must be located as close as possible to the OSCin
and OSCout pins to minimize distortion, stray capacitance,
stray inductance, and startup stabilization time. Circuit stray
capacitance can also be handled by adding the appropriate
stray value to the values for Cin and Cout. For this approach,
the term Cstray becomes 0 in the above expression for CL.
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure 25. The maximum drive level specified
by the crystal manufacturer represents the maximum stress
that the crystal can withstand without damage or excessive
C2
*May be needed in certain cases. See text.
CinCout
C1 • C2
+ Ca + Cstray +
Cin + Cout
C1 + C2
Cin = 6 pF (see Figure 24)
Cout = 6 pF (see Figure 24)
Ca = 1 pF (see Figure 24)
C1 and C2 =external capacitors (see Figure 23)
Cstray = the total equivalent external circuit stray capaci–
tance appearing across the crystal terminals
(see Figure 24)
OSCout
Rf
Figure 24. Parasitic Capacitances of the Amplifier
and Cstray
1
2
CS
LS
RS
1
2
CO
1
Re
Xe
2
Note: Values are supplied by crystal manufacturer
(parallel resonant crystal).
Figure 25. Equivalent Crystal Networks
MC145173
19
Recommended Reading
Technical Note TN–24, Statek Corp.
Technical Note TN–7, Statek Corp.
E. Hafner, “The Piezoelectric Crystal Unit–Definitions and
Method of Measurement”, Proc. IEEE, Vol. 57, No. 2, Feb.
1969.
D. Kemper, L. Rosine, “Quartz Crystals for Frequency
Control”, Electro–Technology, June 1969.
P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic
Design, May 1966.
D. Babin, “Designing Crystal Oscillators”, Machine Design,
March 7, 1985.
D. Babin, “Guidelines for Crystal Oscillator Design”,
Machine Design, April 25, 1985.
Table 6. Partial List of Crystal Manufacturers
Name
Address
Phone
United States Crystal Corp.
Crystek Crystal
Statek Corp.
Fox Electronics
3605 McCart Ave., Ft. Worth, TX 76110
2351 Crystal Dr., Ft. Myers, FL 33907
512 N. Main St., Orange, CA 92668
5570 Enterprise Parkway, Ft. Myers, FL 33905
(817) 921–3013
(813) 936–2109
(714) 639–7810
(813) 693–0099
Note: Motorola cannot recommend one supplier over another and in no way suggests that this is a
complete listing of crystal manufacturers.
MC145173
20
MOTOROLA
PROGRAMMER’S GUIDE
C REGISTER
Write Only
MOST
SIGNIFICANT NIBBLE
(SHIFTED IN FIRST)
LEAST
SIGNIFICANT NIBBLE
(SHIFTED IN LAST)
C7
C3
C6
C5
C4
I SMPL
READ A
RESERVED
CHAN
C2
C1
C0
OUT A <––– LSB
OUT B
OUT C
READ F
I SMPL = Analog Input Sample Command
0 = Initialize the ADC
1 = Sample the voltage on the Input A or B pins (see Chan bit)
Out A = Output A Pin Logic State
0 = Pin is forced to a 0 (default)
1 = Pin is forced to the high–impedance state
Read A = Read A Register Command
0 = Allow writes to any registers, normal state
1 = Read the Input A or B analog value* and the Input C and D
digital values
Out B = Output B Pin Logic State
0 = Pin is forced to a 0 (default)
1 = Pin is forced to a 1
Reserved = Reserved Bit
0 = (Must be in this state)
1 = (This state not allowed at this time, reserved)
Chan = Analog Channel Address
0 = Input A
1 = Input B
Out C = Output C Pin Logic State
0 = Pin is forced to a 0 (default)
1 = Pin is forced to a 1
Read F = Read F Register
0 = Allow writes to any registers, normal state
1 = Read the Frequency Counter’s value and Input D
state
*6–bit analog–to–digital converter output value.
MOTOROLA
MC145173
21
PROGRAMMER’S GUIDE (continued)
R REGISTER
Write Only
MOST
SIGNIFICANT NIBBLE
(SHIFTED IN FIRST)
R23 R22
R21 R20
POL RST
K
LEAST
SIGNIFICANT NIBBLE
(SHIFTED IN LAST)
R19 R18
R17 R16
R15 R14
R13 R12
R11 R10
OUT D ACQ
F SMPL MSB OF R
φdet1 φdet0
COUNTER
DIVIDE VALUE
POL = Polarity of Phase Detector Outputs
0 = Normal (default)
1 = Inverted
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
STBY
HF/VHF
LSB OF R
COUNTER
DIVIDE VALUE
φdet1, φdet0 = VHF Phase Detector Response
0, 0 = Linear Response
0, 1 = Low–Gain Region or Dead Zone – 5 ns wide
1, 0 = Low–Gain Region or Dead Zone – 10 ns wide
1, 1 = Low–Gain Region or Dead Zone – 15 ns wide
RST = Reset
0 = Normal
1 = Reset the chip (automatically cleared low)
Suggestion: set to 1 after power glitch
Out D = Output D Pin Logic State
0 = Pin is forced to a 0 (default)
1 = Pin is forced to a 1
HF/VHF = HF or VHF Band Select
0 = HFin, HF IFin, and HF PDout pins are activated (default)
1 = VHFin, VHF IFin, and VHF PDout pins are activated
ACQ = Acquisition Window
0 = Narrow Sample Window
1 = Wide Sample Window
K = HF IFin Input Response
0 = Normal (must be 0 when VHF band is selected)
1 = Engage Acceptor Circuit
F SMPL = Frequency Counter Sample Command
0 = Initialize Counter to all 1’s (default)
1 = Sample the Frequency at HF IFin or VHF IFin pins
STBY = Standby
0 = Normal
1 = Low–Power Standby State
Example:
To program the R Counter to divide by 1000 in decimal, first convert to hexadecimal: $3E8. Then, add leading bits to form 3 bytes
(6 nibbles). The leading bits should be adjusted to control the above functions. Finally, load the R Register.
CAUTION:
When both the A/D converter and F Counter are simultaneously active, a write to the R Register causes the F Counter operation
to abort.
N REGISTER
Write Only
MOST
SIGNIFICANT NIBBLE
(SHIFTED IN FIRST)
N15 N14
N13 N12
MSB OF N
COUNTER
DIVIDE VALUE
LEAST
SIGNIFICANT NIBBLE
(SHIFTED IN LAST)
N11 N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
LSB OF N
COUNTER
DIVIDE VALUE
ZONE
(SEE TABLE 3)
Example:
To program the N Counter to divide by 1000 in decimal, first convert to hexadecimal: $3E8. Then, add leading zeroes to form 2 bytes
(4 nibbles): $03E8. Finally, Load the N Register with $03E8.
NOTE:
The chip’s VHF PDout is controlled by bit N15 as follows: low = low–gain region, high = dead zone. See Figure 19.
MC145173
22
MOTOROLA
PROGRAMMER’S GUIDE (continued)
A REGISTER
Read Only
OPTIONAL
2–BYTE SHIFT
(BIT A# NOT READ)
MOST
SIGNIFICANT NIBBLE
(SHIFTED OUT FIRST)
A7
A6
EOC
A5
A4
LEAST
SIGNIFICANT NIBBLE
(SHIFTED OUT LAST)
A3
MSB OF
ADC
A2
A1
A0
A#
LSB OF
ADC
IN D
X
X
X
X
X
X
X
DON’T CARE
IN C
EOC = End of Conversion
0 = Invalid ADC Results (also, this bit is 0 when the ADC is in the initialized state)
1 = A/D Conversion Complete, Results are Valid
IN C = Input C Pin Status
0 = Pin is a Logic 0
1 = Pin is a Logic 1
MSB to LSB of ADC = Binary Representation of the 6–Bit Conversion value
For example, zero is 000000, full scale is 111111 in binary.
IN D = Input D Pin Status
0 = Pin is a Logic 0
1 = Pin is a Logic 1
Example:
To read just the ADC value, the user may shift out 1 byte. The ADC value is contained in the 6 LSBs. If the MSB is a 1, this indicates that
the conversion is complete and the results are valid. The MSB – 1 is the Input C pin value.
A 2–byte shift allows reading the In D bit in addition to the above. (In D is also contained in the F Register.) As illustrated above, the MSB
is the EOC bit, and the 7 LSBs are don’t care bits. A 9–bit shift also allows reading the In D bit.
F REGISTER
Read Only
MOST
SIGNIFICANT NIBBLE
(SHIFTED OUT FIRST)
F23 F22
CC
F21 F20
F19 F18
F17 F16
F15 F14
F13 F12
F11 F10
LEAST
SIGNIFICANT NIBBLE
(SHIFTED OUT LAST)
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
IN D
MSB OF
F COUNTER
LSB OF F
COUNTER
CC = Count Complete Bit
0 = Count NOT Complete, invalid F Count data (also, this bit is 0 when the F Counter is in the initialized state)
1 = Count Complete, valid F Count data
IN D = Input D Pin Status
0 = Pin is a Logic 0
1 = Pin is a Logic 1
MSB to LSB of F Counter = Binary Representation of the Frequency Counter’s Value.
For Example, if the Frequency Counter counts to 10,000 in decimal, this is $2710 in hexadecimal. Therefore, the value read, when
Input D is at a logic low level, is $802710. Note for this example that the CC bit is set to a 1 which indicates a valid count.
MOTOROLA
MC145173
23
PROGRAMMER’S GUIDE (continued)
ACCESSING THE WRITE–ONLY REGISTERS
ENB
Din
MSB
CLK
1
LSB
2
3
4
8 CLOCKS TO ACCESS THE C REGISTER
16 CLOCKS TO ACCESS THE N REGISTER
24 CLOCKS TO ACCESS THE R REGISTER
= when the PLL frequency synthesizer loads the data bit.
ACCESSING THE READ–ONLY REGISTERS
The Read F Bit or Read A Bit in the C Register must be set to a 1 prior to the following operation
ENB
DON’T
CARE
Dout
MSB
LSB
HIGH
IMPEDANCE
CLK
X
HIGH
IMPEDANCE
1
2
3
4
8 CLOCKS TO READ THE A REGISTER WITHOUT READING THE IN D BIT
9 OR 16 CLOCKS TO READ THE A REGISTER INCLUDING THE IN D BIT
24 CLOCKS TO READ THE F REGISTER
= when the PLL frequency synthesizer changes the data bit.
MC145173
24
MOTOROLA
PROGRAMMER’S GUIDE (continued)
CONFIGURING FOR HF AND MF OPERATION
HF = HIGH FREQUENCY: 3 TO 30 MHZ
MF = MEDIUM FREQUENCY 500 kHZ TO 3 MHZ
The write–only registers retain data indefinitely as long as
power is applied to the device. Therefore, they do not need to
be re–written with the same data when tuning across the
band. These registers only need to be written if the contents
need to be changed.
Step 1: Load the C Register
The Out A, Out B, and Out C bits must be properly programmed to configure the Output A, Output B, and Output C
pins. These outputs switch a few nanoseconds after the C
Register is loaded, i.e., after ENB makes a low–to–high transition on a C Register access.
Step 2: Load the R Register
This register determines the tuning resolution of the radio
by setting the divide ratio of the R Counter. Also, the HF/VHF
bit must be cleared low for HF and MF operation.
As an example, assume that the external crystal connected to pins 1 and 24 is 10.25 MHz. Also, assume that the
tuning resolution is 10 kHz. Then, the divide ratio needed is
10.25 MHz divided by 10 kHz; this is 1025 decimal. In hexadecimal, this is $401.
Loading the R Register is accomplished with 3 bytes.
Therefore, if all other bits are low, the serial data is $000401.
For HF and MF operation, the ACQ bit is usually set high for
a wide acquisition window. Therefore, it is more likely the
data is: $008401.
Tuning the HF or MF Band
To tune across the HF or MF band, the N Register needs to
be changed.
For example, if the first I.F. is 10.7 MHz, and 530 kHz
needs to be tuned, then the L.O. needs to be running at
10.7 MHz plus 530 kHz for high–side injection; this is
11.23 MHz. The resolution is 10 kHz. Therefore, the ratio required for the N Counter is 11.23 MHz divided by 10 kHz; this
is 1123 decimal. In hexadecimal, this is $463.
Loading the N register requires 2 bytes. Therefore, the serial data is $0463.
To tune 1000 kHz, use 1170 decimal or $0492.
To tune 1710 kHz, use 1241 decimal or $04D9.
CONFIGURING FOR VHF OPERATION
VHF = VERY HIGH FREQUENCY: 30 TO 130 MHz
The write–only registers retain data indefinitely as long as
power is applied to the device. Therefore, they do not need to
be re–written with the same data when tuning across the
band. These registers only need to be written if the contents
need to be changed.
Step 2: Load the R Register
This register determines the tuning resolution of the radio
by setting the divide ratio of the R Counter. Also, the HF/VHF
bit must be set high for VHF operation.
As an example, assume that the external crystal connected to pins 1 and 24 is 10.35 MHz. Also, assume that the
tuning resolution is 50 kHz. Then, the divide ratio needed is
10.35 MHz divided by 50 kHz; this is 207 decimal. In hexadecimal, this is $CF.
Loading the R Register is accomplished with 3 bytes.
Therefore, if all other bits are low, the serial data is $0000CF.
For VHF operation, the ACQ bit is usually cleared low for a
narrow acquisition window.
Tuning the VHF Band
To tune across the VHF Band, the N Register needs to be
changed.
For example, if the I.F. is 10.7 MHz, and 87.5 MHz needs
to be tuned, then the L.O. needs to be running at 10.7 MHz
plus 87.5 MHz for high–side injection; this is 98.2 MHz. The
resolution is 50 kHz. Therefore, the ratio required for the N
Counter is 98.2 MHz divided by 50 kHz; this is 1964 decimal.
In hexadecimal, this is $7AC.
Loading the N Register requires 2 bytes. Therefore, the
serial data is $07AC.
To tune 98.5 MHz, use 2184 decimal or $0888.
To tune 107.9 MHz, use 2372 decimal or $0944.
READING THE A REGISTER
The A Register contains the binary representation of the
Analog–to–Digital Converter’s value plus the End of Conversion bit (EOC). The EOC bit must be a 1 to indicate a valid
conversion. Also, the A Register has bits which indicate the
logic levels on the Input C and D pins.
Reading the Logic Levels on the Input C and D Pins
Step 1: Store the Values in the Shift Register
To store the value, set the Read A bit in the C Register to a
1. The digital value present at the Input C and D pins during
the falling edge of ENB on the read cycle is stored in the shift
register.
Step 2: Read the Serial Data
To read the Input C value only, take the ENB pin low and
shift out 8 bits. The Input C value is contained in the In C bit.
To read both the Input C and D values, take the ENB pin
low and shift out 9 or 16 bits. The values are in the In C and
In D bits.
NOTE: In D may also be read from the F Register.
Reading the Analog–to–Digital Converter Value
Step 1: Load the C Register
Step 1: Initialize
The Out A, Out B, and Out C bits must be properly programmed to configure the Output A, Output B, and Output C
pins. These outputs switch a few nanoseconds after the C
Register is loaded; i.e., after ENB makes a low–to–high transition on a C Register access.
To initialize the converter, clear the I SMPL bit in the C
Register to a 0. At this time, the Read A bit in the C Register
must be 0. The Chan bit must be 0 to select Input A or 1 to
select Input B. The state may not be changed simultaneously
with the I SMPL bit being set high.
MOTOROLA
MC145173
25
Step 2: Acquire the Value
To sample the analog input selected, set the I SMPL bit in
the C Register to a 1. The Read A bit must not be changed; it
must be a 0.
MC145173
26
MOTOROLA
PROGRAMMER’S GUIDE (continued)
NOTE: I SMPL may be set high, even if F SMPL is already
set high. I SMPL is not automatically cleared low.
The length of time required to acquire the data is dependent on the crystal frequency (tied to pins 1 and 24) or OSCin
frequency. The formula is: T = 3584/f; where T is the acquisition time in seconds and f is the frequency at OSCin in
hertz. After the I SMPL bit is set, the EOC bit is set high after
the acquisition time T above, and data is available to be read.
Step 3: Read the Serial Data
To read the ADC value, set the Read A bit in the C Register
to a 1. I SMPL must not be changed; it must be a 1.
Take the ENB pin low and shift out 8 bits. The value is contained in the least–significant 6 bits. In addition, the EOC bit
should be checked to ensure it is a 1; this indicates that the
conversion was complete before the data was read. If EOC is
a 0, the conversion result is not valid.
The In C bit is valid and indicates the logic level present on
the Input C pin. (Alternatively, 9 or 16 bits could be shifted out
if the user desires to read both the In C and In D bits.)
NOTE: When the Read A bit is set to a 1, writing to any
register is inhibited. After the serial shift which reads the A
Register occurs, Read A is automatically cleared to a 0.
CAUTION
If both Read A and Read F are set simultaneously,
a Read A Register operation is performed and the
Read F Register request is ignored.
READING THE F REGISTER
The F Register contains the binary representation of the
Frequency Counter’s value plus the Count Complete flag
(CC). The CC bit must be a 1 to indicate a valid count. Also,
the F Register has a bit which indicates the logic level on the
Input D pin.
Reading the Logic Level on the Input D Pin
Step 1: Store the Value in the Shift Register
To store the value, set the Read F bit in the C Register to a
1. The digital value present at the Input D pin during the falling edge of ENB on the read cycle is stored in the shift register.
Step 2: Read the Serial Data
To read the Input D value, take the ENB pin low and shift
out 24 bits. The Input D value is contained in the In D bit.
NOTE: In D may also be read from the A Register.
MOTOROLA
Reading the Frequency Counter Value
Step 1: Initialize
To initialize the counter, clear the F SMPL bit in the R Register to a 0. At this time, the Read F bit in the C Register must
be 0. The HF/VHF bit in the R Register must be a 0 for HF–
MF operation or 1 for VHF operation. The ACQ (Acquisition
Window) bit must be a 0 for a narrow acquisition window or a
1 for a wide window. The formula for the window:
t
+2
(19
) 2a)
f
where t = acquisition window (in seconds), a = logic level of
acquisition bit (0 or 1), f = crystal frequency or OSC in
frequency in hertz.
Step 2: Acquire the Count
To sample the frequency, set the F SMPL bit in the R Register to a 1. The Read F bit must not be changed; it must be
a 0.
CAUTION
F SMPL must not be set if I SMPL is already set
high.
The data is available to be read after the acquisition window time above. The CC bit is set high immediately after the
acquisition is complete.
Step 3: Read the Serial Data
To read the F Counter value, set the Read F bit in the C
Register to a 1. F SMPL must not be changed; it must be a 1.
Take the ENB pin low and shift out 24 bits. The value is contained in the least–significant 22 bits. In addition, the CC bit
should be checked to ensure it is a 1; this indicates that the
count was complete before the data was read. If CC is a 0,
the count is not valid. The In D bit is valid and indicates the
logic level present on the Input D pin.
NOTE: When the Read F bit is set to a 1, writing to any
register is inhibited. After the serial shift which reads the F
Register occurs, Read F is automatically cleared to a 0.
CAUTION
If both Read A and Read F are set simultaneously,
a Read A Register operation is performed and the
Read F Register request is ignored.
MC145173
27
10.25 MHz
RBIAS
NOTE
6
MC145173
+5V
1 OSC
in
2 ENB
3
MCU
4
5
GENERAL-PURPOSE
SPECIAL DIGITAL
DIGITAL INPUT
INPUT WITH
SWITCHPOINT AT
33% OF VDD
ANALOG INPUTS
(SIGNAL LEVEL, ETC.)
6
7
8
9
10
AM SECOND I.F. (450 kHz)
NOTE 5
FM I.F. (10.7 MHz)
11
12
+5V
Din
CLK
Dout
INPUT D
INPUT C
INPUT B
OSCout 24
REFout 23
22
OUTPUT D
21
VHF PDout
20
Rx
19
VSS
18
HF PDout
VDD 17
VHF IFin
HFin 16
VHFin 15
OUTPUT C 14
OUTPUT A
OUTPUT B
INPUT A
HF IFin
+5V
R1
NOTE 8
10.25 MHz
BUFFERED
OUTPUT
(AM SECOND L.O.)
GENERAL-PURPOSE
DIGITAL OUTPUT
OPTIONAL
GAIN
BLOCK
LOW–PASS
FILTER
0.1 µF
NOTE 3
+5V
15 kΩ
LOW-PASS
FILTER
+5V
13
NOTE 7
NOTE 3
OPTIONAL GAIN BLOCK
HF
VCO
AM FIRST L.O.
VHF
VCO
FM L.O.
GENERAL PURPOSE DIGITAL OUTPUTS
NOTES:
1. The HF PDout and VHF PDout pins require different low-pass filters. See the Phase-Locked Loop – Low-Pass Filter Design page for
more information.
2. For optimum performance, bypass the VDD pin to VSS with a low-inductance capacitor.
3. The gain blocks can be simple one-transistor circuits. See Figures 28 and 29.
4. For the AM band, an R counter divide ratio of 1,025 is used for 10 kHz tuning resolution. The FM band uses an R counter ratio of 205 for
50 kHz tuning resolution.
5. I.F. (intermediate frequency) signals are fed to pins 10 and 11 only if seek or scan feature is included in radio.
6. Diode string is used to limit voltage swing at pin 23; additional or fewer diodes may be used. For full rail-to-rail swing, tie R1 to VSS
(GND) and delete the diodes and the RBIAS resistor. Caution: this large signal swing may cause a high level of EMI (electromagnetic
interference).
7. Pull-up voltage must be at the same potential as the VDD pin or less. Pull-up device other than a resistor may be used.
8. A 10.25 MHz crystal facilitates design of the AM upconversion scheme shown. This results in double conversion for the AM receiver. Optionally, single-conversion designs may be used which offer more flexibility on reference crystal values. For example, a 10.0 MHz crystal
could be used which would allow higher-performance 200 kHz tuning resolution for FM.
Figure 26. AM-FM Broadcast Receiver Subsystem — USA
MC145173
28
MOTOROLA
10.35 MHz
NOTE 8
R1
NOTE
6
MC145173
+5V
1 OSC
in
2 ENB
3
MCU
4
5
GENERAL–PURPOSE
DIGITAL INPUT
SPECIAL DIGITAL
INPUT WITH
SWITCHPOINT AT
33% OF VDD
ANALOG INPUTS
(SIGNAL LEVEL, ETC.)
AM SECOND I.F. (450 kHz)
6
7
8
9
10
NOTE 5
11
FM I.F. (10.8 MHz)
12
+5V
Din
CLK
Dout
INPUT D
INPUT C
INPUT B
OSCout 24
REFout 23
22
OUTPUT D
21
VHF PDout
20
Rx
19
Vss
18
HF PDout
VDD 17
VHF IFin
HFin 16
VHFin 15
OUTPUT C 14
OUTPUT A
OUTPUT B
INPUT A
HF IFin
10.35 MHz
BUFFERED
OUTPUT
(AM SECOND L.O.)
+5V
RBIAS
GENERAL–PURPOSE
DIGITAL OUTPUT
OPTIONAL
GAIN
BLOCK
LOW-PASS
FILTER
0.1 µF
NOTE 3
+5V
15 kΩ
LOW–PASS
FILTER
+5V
13
NOTE 7
NOTE 3
OPTIONAL GAIN BLOCK
HF
VCO
AM FIRST L.O.
VHF
VCO
FM L.O.
GENERAL PURPOSE DIGITAL OUTPUTS
NOTES:
1. The HF PDout and VHF PDout pins require different low–pass filters. See the Phase–Locked Loop – Low–Pass Filter Design page for
more information.
2. For optimum performance, bypass the VDD pin to VSS with a low–inductance capacitor.
3. The gain blocks can be simple one–transistor circuits. See Figures 28 and 29.
4. For the AM band, an R counter divide ratio of 1,150 is is used for 9 kHz tuning resolution. The FM band uses an R counter ratio of 207
for 50 kHz tuning resolution.
5. I.F. (intermediate frequency) signals are fed to pins 10 and 11 only if seek or scan feature is included in radio.
6. Diode string is used to limit voltage swing at pin 23; additional or fewer diodes may be used. For full rail–to–rail swing, tie R1 to VSS
(GND) and delete the diodes and the RBIAS resistor. Caution: this large signal swing may cause a high level of EMI (electromagnetic
interference).
7. Pull–up voltage must be at the same potential as the VDD pin or less. Pull–up device other than a resistor may be used.
8. A 10.35 MHz crystal facilitates design of the AM upconversion scheme shown. This results in double conversion for the AM receiver.
Optionally, single–conversion designs may be used which offer more flexibility on reference crystal values. For example, a 10.0 MHz
crystal could be used which would allow higher–performance 100 kHz tuning resolution for FM.
Figure 27. AM–FM Broadcast Receiver Subsystem — Europe
MOTOROLA
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PHASE–LOCKED LOOP — LOW PASS FILTER DESIGN
HF PDout
VCO
R1
Kφ KVCO
NC(R1 + R2)
ωn =
R2
ζ = 0.5 ωn
C
VHF PDout
R2C +
F(s) =
R2sC + 1
(R1 + R2)sC + 1
ωn =
Kφ KVCO
NC
VCO
N
KφKVCO
R
ζ =
C
Z(s) =
R
2
Kφ KVCOC
N
=
ωnRC
2
1 + sRC
sC
NOTE:
For VHF PDout, using Kφ in amps per radian with the filter’s impedance transfer function, Z(s), maintains units of volts per radian for the
detector/ filter combination. Additional sideband filtering can be accomplished by adding a capacitor C′ across R. The corner ωc = 1/RC′
should be chosen such that ωn is not significantly affected.
DEFINITIONS:
N = Total Division Ratio in Feedback Loop
Kφ (Phase Detector Gain) = VDD / 4π volts per radian for HF PDout
Kφ (Phase Detector Gain) = I PDout / 2π amps per radian for VHF PD out
KVCO (VCO Gain) =
2π∆fVCO
radians per volt
∆VVCO
For a nominal design starting point, the user might consider a damping factor ζ≈0.7 and a natural loop frequency ωn ≈ (2πfR/50) where fR is the
frequency at the phase detector input. Larger ωn values result in faster loop lock times and, for similar sideband filtering, higher fR–related
VCO sidebands.
The filters shown above are frequently followed by additional sideband filtering to further attenuate fR–related VCO sidebands. This additional filtering may be active or passive.
RECOMMENDED READING:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley–Interscience, 1980.
Blanchard, Alain, Phase–Locked Loops: Application to Coherent Receiver Design. New York, Wiley–Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley–Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice–Hall, 1983.
Berlin, Howard M., Design of Phase–Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
Seidman, Arthur H., Integrated Circuits Applications Handbook, Chapter 17, pp. 538–586. New York, John Wiley & Sons.
Fadrhons, Jan, “Design and Analyze PLLs on a Programmable Calculator,” EDN. March 5, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design
1987.
MC145173
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MOTOROLA
+10 V
RBIAS
R2
R3
VCO
C2
C1
2N7002
Q1
R1
HF PDout
NOTES:
1. R1, C1, and R2 form the main filter (determine the loop bandwidth).
2. R3 and C2 are extra filtering; set above loop bandwidth.
3. R1/C1/R2 and R3/C2 are isolated due to Q1. Therefore, there should be minimal
interaction.
Figure 28. Active Low–Pass Filter with Gain for HF PDout
+10 V
RBIAS
R1
R2
VCO
C2
C1
VHF PDout
2N7002
Q1
NOTES:
1. R1 and C1 form the main filter (determine the loop bandwidth).
2. R2 and C2 are extra filtering; set above loop bandwidth.
3. R1/C1 and R2/C2 are isolated due to Q1. Therefore, there should be
minimal interaction.
4. This filter configuration is a concept and has not been examined in the
laboratory.
Figure 29. Active Low–Pass Filter with Gain for VHF PDout
MOTOROLA
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PACKAGE DIMENSIONS
DW SUFFIX
SOG (SMALL–OUTLINE GULL–WING) PACKAGE
CASE 751E–04
-A-
24
13
-B-
P 12 PL
0.010 (0.25)
1
M
B
M
12
D
24 PL
J
0.010 (0.25)
M
T A
S
B
S
F
R X 45°
C
-TSEATING
PLANE
MC145173
32
G
22 PL
K
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
15.25 15.54
7.60
7.40
2.65
2.35
0.49
0.35
0.90
0.41
1.27 BSC
0.32
0.23
0.29
0.13
8°
0°
10.05 10.55
0.25
0.75
INCHES
MIN
MAX
0.601 0.612
0.292 0.299
0.093 0.104
0.014 0.019
0.016 0.035
0.050 BSC
0.009 0.013
0.005 0.011
0°
8°
0.395 0.415
0.010 0.029
MOTOROLA
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Literature Distribution Centers:
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EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England.
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ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MOTOROLA
◊
*MC145173/D*
MC145173/D
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