MOTOROLA MC33091AD

Order this document by MC33091A/D
The MC33091A is a High–Side TMOS Driver designed for use in harsh
automotive switching applications requiring the capability of handling high
voltages attributed to load and field dump transients, as well as reverse and
double battery conditions. Few external components are required to drive a
wide variety of N–Channel TMOS devices. The MC33091A, driving an
appropriate TMOS device, offers economical system solutions for high–side
switching large currents. The MC33091A has CMOS compatible input
control, charge pump to drive the TMOS power transistor, basic fault
detection circuit, VDS monitoring circuit used to detect a shorted TMOS load,
and overcurrent protection timer with associated current squaring circuitry.
Short circuit protection is made possible by having a unique VDS voltage
to current converter drive an externally programmable integrator circuit. This
circuit affords fast detection of a shorted load while allowing difficult loads,
such as lamps having high in–rush currents, additional time to turn on.
The Fault output is comprised of an open collector NPN transistor
requiring a single pull–up resistor for operation. A fault is reported whenever
the MOSFET on–current exceeds an externally programmed set level.
The MC33091A is available in the plastic 8–Pin DIP package as well as
the plastic 8–Pin surface mount package.
• Designed for Automotive High–Side Driver Applications
•
•
•
•
•
•
•
•
•
HIGH–SIDE
TMOS DRIVER
SEMICONDUCTOR
TECHNICAL DATA
8
1
P SUFFIX
PLASTIC PACKAGE
CASE 626
Works with a Wide Variety of N–Channel Power MOSFETs
Drives Inductive Loads with No External Clamp Circuitry Required
CMOS Logic Compatible Input Control
8
1
On–Board Charge Pump with No External Components Required
Shorted Load Detection and Protection
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
Forward Overvoltage and Reverse Battery Protection
Load and Field Dump Protection
Extended Operating Temperature Range
Fault Output to Report a MOSFET Overcurrent Condition
Simplified Block Diagram
PIN CONNECTIONS
+VS
RS
RX
2
MC33091A
5
VCC
Overvoltage
Shutdown
Input
7
CS
DRN
Charge
Pump
+
Gate
Current
Squaring
Circuit
ISQ
Fault
8
RT
VT
DRN
2
7
Input
Gnd
3
6
Fault
Gate
4
5
VCC
(Top View)
1
+
Load
Gnd
8
SRC
+
3
1
4
+
QS
QR
6
SRC
ORDERING INFORMATION
Device
VT
CT
This device contains 54 active transistors.
MC33091AD
MC33091AP
Operating
Temperature Range
TA = – 40° to +125°C
 Motorola, Inc. 1996
MOTOROLA ANALOG IC DEVICE DATA
Package
SO–8
Plastic DIP
Rev 0
1
MC33091A
MAXIMUM RATINGS
Symbol
Value
Unit
Supply Voltage (Pin 5) (Note 1)
Continuous (Without Activating Clamp)
Rating
VCC
–0.7 to 28
7.0 to 28
V
Continuous Supply Clamp Current (Pin 5)
DIP Package (Case 626)
SO–8 Package (Case 751)
IC
Input Control Voltage Range (Pin 7)
Continuous
Vin
Fault Pull–Up Voltage Range (Pin 6)
Continuous
Vout
Minimum ESD Voltage Capability (Note 2)
ESD
2000
V
TJ
150
°C
Tstg
–65 to +150
°C
TA
–40 to +125
°C
mA
10
1.0
V
–0.7 to 28
V
–0.7 to 28
Operating Junction Temperature
Storage Temperature
Operating Ambient Temperature Range
°C/W
RθJA
Thermal Resistance, Junction–to–Ambient
DIP Package (Case 626)
SO–8 Package (Case 751)
100
145
NOTES: 1. An internal zener diode is incorporated to protect the device from overvoltage transients in excess
of 30 V.
2. ESD testing performed in accordance with Human Body Model (C = 100 pF, R = 1500 Ω).
Figure 1. Typical Application
+VS
RS = 200
RX = 75 k
0.1
2
DRN
MC33091A
Overvoltage
Shutdown
Input
7
5
VCC
30 V
Charge
Pump
+
2.6 V
40 V
+5.0 V
Gate
Current
Squaring
Circuit
ISQ
9.1 k
Fault
6
+
QS
QR
40 V
+
3
Gnd
8
RT
2
4
14 V
SRC
1
VTH
4.3 V
1.0 k
+ R
1.0 V
Load
VTL
0.95 V
VT
CT
MOTOROLA ANALOG IC DEVICE DATA
MC33091A
ELECTRICAL CHARACTERISTICS (Values are noted under conditions of 7.0 V ≤ VCC ≤ 24 V, –40°C ≤ TA ≤ +125°C, unless otherwise
noted. Typical values reflect approximate mean at TA = 25°C at time of device characterization.)
Characteristics
Symbol
Min
Typ
Max
Unit
–
–
160
2.5
300
6.0
µA
mA
Supply Current (Note 1)
Vin = 0 V
Vin = 5.0 V (RX = 100 k)
ICC
Supply Clamp Voltage (Note 2)
VZ
29
–
35
V
VGS
8.0
12
15
V
30
–
400
VG(sat)
0
1.2
1.4
V
IGC
6.4
7.0
7.7
V
VIL
VIH
–
3.5
2.7
2.7
1.5
–
Input Control Current (Pin 7) (Vin = 5.0 V)
Iin
–
100
250
Timer Current Constant (Pin 8)
(RX = 100 k, VT = 0, VDS = 1.0 V) (Note 3)
K
0.7
1.1
1.5
Gate–to–Source Voltage Range (Pin 4)
Gate Current (Pin 4)
VG = VCC
µA
IG
Gate Saturation Voltage (IG = 10 µA)
Short Circuit Gate Voltage (Note 4)
Input Control Threshold Voltage (Pin 7)
V
µA
µA/V2
Timer (Pin 8)
Lower Threshold Voltage
Upper Threshold Voltage
VTL
VTH
0.4
4.3
0.95
4.6
1.2
5.2
V
Fault Sink Current (Pin 6)
VF = 5.0 V
VF = 0
IOL
IOH
500
–
–
2.0
–
100
µA
nA
Fault Saturation Voltage (Pin 6) (IF = 500 µA)
VOL
–
0.2
0.8
V
NOTES: 1. The total supply current into Pin 2 and Pin 5 with RX = 100 k (from Pin 2 to supply) and 45 k pull–up resistor from Pin 6 to supply.
2. An internal zener clamp is provided to protect the device from overvoltage transients on the supply line.
3. The timer current constant is the proportionality constant of the voltage to current converter used to monitor the VDS voltage developed across the
FET (from Pin 1 to the supply).
4. The gate voltage will be clamped at approximately 7.0 V above the source voltage whenever the source voltage is less than approximately 1.0 V
above ground.
Figure 2. Supply Current versus Supply Voltage
Figure 3. Operating Current versus Supply Voltage
500
6.0
Vin = 0 V (Gate “off”)
VDS = 2.0 V
I CC , OPERATING CURRENT (mA)
ICC , SUPPLY CURRENT (µ A)
600
TA = –40°C
400
300
200
TA = 25°C
100
0
6.0
TA = 125°C
12
18
24
VCC, SUPPLY VOLTAGE (V)
MOTOROLA ANALOG IC DEVICE DATA
30
Vin = 5.0 V (Gate “on”)
TA = –40°C
5.0
4.0
TA = 25°C
3.0
TA = 125°C
2.0
1.0
6.0
12
18
24
30
VCC, SUPPLY VOLTAGE (V)
3
MC33091A
Figure 4. Input Control Current
versus Input Control Voltage
Figure 5. Input Control Current
versus Supply Voltage
200
I in , INPUT CONTROL CURRENT ( µA)
VCC = 14 V
TA = 25°C
140
120
100
80
60
40
20
0
0
1.0
2.0
3.0
4.0
5.0
VFault , FAULT VOLTAGE (V)
TA = 125°C
TA = 25°C
0.6
0.4
TA = –40°C
0.2
1.0
2.0
3.0
4.0
5.0
18
24
30
1.30
TA = 125°C
RX = 100 k
VDS = 2.0 V
1.25
1.20
TA = –40°C
1.15
1.10
TA = 25°C
1.05
1.00
0.95
6.0
12
18
24
30
Figure 9. Timer Current versus
Drain–to–Source Voltage Squared
600
VCC = 14 V
Vin = 5.0 V
RX = 75 k
TA = 125°C
TA = 25°C
ISQ , TIMER CURRENT (µA)
ISQ , TIMER CURRENT (µ A)
12
Figure 8. Timer Current versus
Drain–to–Source Voltage Squared
TA = –40°C
150
100
50
50
100
150
VDS2, DRAIN–TO–SOURCE VOLTAGE SQUARED (V2)
4
6.0
VCC, SUPPLY VOLTAGE (V)
200
0.1
0.1
TA = 125°C
80
IFault, FAULT SINK CURRENT (mA)
350
250
100
Figure 7. Squaring Constant “K”
versus Supply Voltage
0.8
300
TA = 25°C
120
Figure 6. Fault Voltage versus
Fault Sink Current
VCC = 14 V
TA = 25°C
0
140
VCC, SUPPLY VOLTAGE (V)
1.0
0
TA = –40°C
160
Vin, INPUT CONTROL VOLTAGE (V)
1.4
1.2
Vin = 5.0 V
180
60
6.0
K , CURRENT SQUARING CONSTANT (µ A/V 2 )
I in , INPUT CONTROL CURRENT ( µ A)
160
200
VCC = 14 V
Vin = 5.0 V
TA = 25°C
500
RX = 50 k
400
300
RX = 75 k
200
RX = 100 k
100
0.1
0
50
100
150
200
VDS2, DRAIN–TO–SOURCE VOLTAGE SQUARED (V2)
MOTOROLA ANALOG IC DEVICE DATA
Figure 10. Timer Upper Threshold Voltage
versus Temperature
4.64
VCC = 7.0 V
4.62
4.60
VCC = 14 V
4.58
4.56
Vin = 5.0 V
VTH = Increasing VT
causing Gate turn–off
VCC = 28 V
4.54
4.52
4.50
–50
0
50
100
150
VTH, TIMER UPPER THRESHOLD VOLTAGE (V)
VTH, TIMER UPPER THRESHOLD VOLTAGE (V)
MC33091A
Figure 11. Timer Upper Threshold Voltage
versus Supply Voltage
4.64
4.62
4.60
TA = –40°C
4.58
Vin = 5.0 V
VTH = Increasing VT
causing Gate turn–off
4.56
4.52
TA = 125°C
4.50
6.0
12
Figure 12. Timer Lower Threshold Voltage
versus Temperature
1.10
7.0 V ≤ VCC ≤ 28 V
Vin = 5.0 V
VTL = Decreasing VT
causing Gate turn–on
1.00
0.95
0.90
0.85
0.80
0.75
–50
0
50
100
150
TA = –40°C
1.1
1.0
TA = 25°C
0.9
0.8
TA = 125°C
0.7
Vin = 5.0 V
VTL = Decreasing VT
causing Gate turn–on
0.6
0.5
6.0
12
18
24
30
VCC, SUPPLY VOLTAGE (V)
Figure 15. Gate Voltage versus
Supply Voltage
30
45
25
40
VG , GATE VOLTAGE (V)
VG , GATE VOLTAGE (V)
30
1.2
Figure 14. Gate Voltage versus
Input Control Voltage
VCC = 14 V
TA = 25°C
15
10
5.0
–40°C ≤ TA ≤ 125°C
Vin = 5.0 V (Gate “on”)
IG ≤ 5.0 µA
35
30
25
20
0
–5.0
2.0
24
Figure 13. Timer Lower Threshold Voltage
versus Supply Voltage
TA, AMBIENT TEMPERATUE (°C)
20
18
VCC, SUPPLY VOLTAGE (V)
V TL, TIMER LOWER THRESHOLD VOLTAGE (V)
V TL, TIMER LOWER THRESHOLD VOLTAGE (V)
TA, AMBIENT TEMPERATUE (°C)
1.05
TA = 25°C
4.54
2.2
2.4
2.6
Vin, INPUT CONTROL VOLTAGE (V)
MOTOROLA ANALOG IC DEVICE DATA
2.8
3.0
15
6.0
12
18
24
30
VCC, SUPPLY VOLTAGE (V)
5
MC33091A
Figure 16. Gate Voltage versus Supply Voltage
Figure 17. Gate Voltage verus Gate Current
50
1.10
TA = –40°C
1.05
TA = 25°C
VCC = 28 V
1.00
Vin = 0 V (Gate “off”)
0.95
0.90
0.85
40
VG , GATE VOLTAGE (V)
VG , GATE VOLTAGE (V)
1.15
125°C
12
–40°C
125°C
25°C
20
VCC = 14 V
25°C
–40°C
10
0
30
0
–50
–100
VCC, SUPPLY VOLTAGE (V)
Vin = 5.0 V
VG = VCC
350
12
I G, GATE CURRENT ( µA)
VGS, GATE–TO–SOURCE VOLTAGE (V)
–250
–300
400
TA = 125°C
TA = 25°C
10
TA = –40°C
8.0
VCC = 14 V
Load Shorted
6.0
0.5
1.0
1.5
2.0
TA = –40°C
300
TA = 25°C
250
200
TA = 125°C
150
100
50
0
6.0
2.5
12
18
24
30
VSRC, SOURCE VOLTAGE (V)
VCC, SUPPLY VOLTAGE (V)
Figure 20. Gate Saturation Voltage
versus Gate Current
Figure 21. Gate Saturation Voltage
versus Gate Current (Expanded Scale)
2.25
VG(sat) , GATE SATURATION VOLTAGE (V)
2.5
VG , GATE SATURATION VOLTAGE (V)
–200
Figure 19. Gate Current versus Supply Voltage
14
TA = –40°C
2.0
TA = 25°C
1.5
TA = 125°C
1.0
1.80
TA = –40°C
1.35
TA = 25°C
0.90
TA = 125°C
0.45
0.5
0
0.2
0.4
0.6
IG, GATE CURRENT (mA)
6
–150
IG, GATE CURRENT (µA)
Figure 18. Gate–to–Source Voltage
versus Source Voltage
0
VCC = 7.0 V
125°C
24
18
–40°C
30
TA = 125°C
0.80
6.0
25°C
0.8
1.0
0
0
20
40
60
80
100
IG, GATE CURRENT (µA)
MOTOROLA ANALOG IC DEVICE DATA
MC33091A
7.0
VDS(min) = [(VTHRX2IQ)/RT]1/2
VTH = 4.6 V
IQ 100 µA
RX = 100 k
6.0
t(min), MINIMUM TIMER RESPONSE TIME (s)
VDS(min), DRAIN–TO–SOURCE VOLTGE (V)
Figure 22. Drain–to–Source Voltage
versus External RT Timer Resistor
Figure 23. Timer Response versus
VDS(min)/S Ratio
100
RTCT = 1.0
10–1
5.0
RTCT = 0.1
10–2
4.0
3.0
RTCT = 0.01
10–3
RX = 75 k
10–4
2.0
RX = 50 k
1.0
0
100
200
t(min) = –RTCT In[1 – (VDS(min)/VS2]
10–5
300
400
500
600
800
700
900
1000
10–6
0.05
0.10
Figure 24. FET Comparison Gate Response
0.20
0.25
MTP8N10
Ciss = 500 pF
0.40
0.45
0.50
VG , GATE VOLTAGE (V)
25
MTP50N06
Ciss = 3000 pF
10
MTP25N06
Ciss = 1000 pF
5.0
Input = 5.0 V Step
VCC = 7.0 V
TA = 25°C
0
100
200
300
400
500
600
700
800
MTP50N06
Ciss = 3000 pF
20
MTP25N06
Ciss = 1000 pF
15
10
MTP8N10
Ciss = 500 pF
5.0
0
0
900 1000
0
100
200
300
Input = 5.0 V Step
VCC = 14 V
TA = 25°C
400
Figure 26. FET Comparison Gate Response
VG , GATE VOLTAGE (V)
MTP50N06
Ciss = 3000 pF
MTP25N06
Ciss = 1000 pF
20
700
800
900
1000
VCC = 28 V
TA = 25°C
30
600
Figure 27. MTP25N06 Gate Response
50
50
40
500
t, TIME (µs)
t, TIME (µs)
VG , GATE VOLTAGE (V)
0.35
30
15
MTP8N10
Ciss = 500 pF
Input = 5.0 V Step
VCC = 28 V
TA = 25°C
10
0
0.30
Figure 25. FET Comparison Gate Response
20
VG , GATE VOLTAGE (V)
0.15
VDS(min)/VS, DRAIN–TO–SOURCE VOLTAGE
TO SUPPLY VOLTAGE RATIO
RT, EXTERNAL TIMER RESISTOR (kΩ)
40
30
VCC = 14 V
20
VCC = 7.0 V
10
MTP25N06
Ciss = 1000 pF
Input = 5.0 V Step
0
0
100
200
300
400
500
600
t, TIME (µs)
MOTOROLA ANALOG IC DEVICE DATA
700
800
0
100
200
300
400
500
600
700
800
900
1000
t, TIME (µs)
7
MC33091A
Figure 28. Descriptive Waveform Diagram
<30 V
VZ
+VCC
(Pin 5)
0V
5.0 V
Input
(Pin 7)
0V
VSRC + 14 V
VGC ≈ 7.0 V
Gate
(Pin 4)
0V
VTH
VT
(Pin 8)
VTL
0V
VPU
Fault
(Pin 6)
0V
<VS
SRC
(Pin 1)
0V
VDS
DRN
(Pin 2)
VSRC
0V
Normal Operation
8
Shorted FET Load
Normal Operation
Overvoltage
MOTOROLA ANALOG IC DEVICE DATA
MC33091A
FUNCTIONAL DESCRIPTION
Introduction
The MC33091A is designed to drive a wide variety of
N–channel TMOS transistors in high–side configured, low
frequency switching applications. The MC33091A has an
internal charge pump to fully enhance the on–state of the
TMOS device. The MC33091A protects the TMOS device
from shorts to ground and provides a Fault output to report
the presence of an overcurrent condition. The few additional
external components required allow tailoring of the
application’s protection level. The protection scheme of the
MC33091A uses an externally programmable, nonlinear
timer that disables the TMOS device in the event the drain to
source voltage exceeds a specified value for a specified
duration. Both the value and duration are externally
programmable allowing for flexibility in applications.
Description of Pins
Figure 1 shows a typical application as well as the internal
functional blocks of the MC33091A. The discussion to follow
references this figure.
Input (Pin 7): The logic levels of the Input are compatible
with CMOS logic families. The Input enables the protection
and charge pump circuitry. With the Input in a logic low state
the MC33091A draws only leakage current of less than
300 µA and in this condition the associated TMOS device
will be in the “off” state. When the Input is in a logic high state,
the Gate voltage (Pin 4) rise is limited to a maximum of 14 V
above SRC (Pin 1), due to an internal clamp diode being
used and the TMOS device is enhanced full on.
Fault (Pin 6): The Fault output is comprised of an open
collector NPN transistor capable of sinking at least 500 µA
when the TMOS gate is disabled due to an overcurrent
condition. When the TMOS device experiences an
overcurrent condition, the Fault pin is pulled low.
SRC (Pin 1): The SRC pin senses the TMOS source
voltage and is the input to the VDS buffer used in conjunction
with the DRN pin in monitoring the drain to source voltage
developed across the TMOS device. The purpose of the
1.0 k resistor connected to this pin is to protect the SRC input
from overvoltage as a result of flyback voltage produced
when the TMOS device is used to switch large inductive
loads. This resistor can be eliminated when switching
noninductive loads.
DRN (Pin 2): The DRN is used in conjunction with the SRC
pin and together constitute a VDS monitor of the TMOS drain
to source voltage. Feedback from the SRC pin will maintain a
voltage across the resistor, RX, equal to the VDS voltage
developed across the TMOS device. The series resistor, RX,
connected between the drain of the TMOS device and DRN
of the MC33091A is used in conjunction with the feedback
buffer and associated PNP transistor to establish a current
proportional to the drain to source voltage, VDS, of the TMOS
device. This proportional current, acted upon by the current
squaring circuit of the MC33091A, is an important part of the
TMOS protection scheme.
VCC (Pin 5): The VCC pin supplies operational power to the
MC33091A. An internal 30 V zener clamp connected to this
MOTOROLA ANALOG IC DEVICE DATA
pin provides overvoltage protection of the MC33091A. When
the zener is activated, the MC33091A disables the TMOS
device only for the duration of the overvoltage but the Fault
output (Pin 6) does not change logic states. The Fault pin
does not go to a logic low state during the overvoltage
duration since this is not an MC33091A device fault, but an
external system fault.
Gate (Pin 4): The Gate pin of the MC33091A is the output
of the internal charge pump which controls the TMOS device.
The charge pump is a voltage tripler and requires no
additional external components for operation. When the Input
is at a logic low state, the charge pump will be turned off.
When the Input is pulled to a logic high state, with no load
fault existing, the charge pump turns on and pumps the
TMOS gate voltage to at least 8.0 V, typically 10 to 14 V,
above VCC. An internal zener clamp is incorporated to limit
the Gate to approximately 14 V above the source and
prevent rupture of the TMOS gate.
VT (Pin 8): The Timer pin (VT) is both an input to the timer
window comparators and an output of the current squaring
circuit. An external resistor (RT) and capacitor (CT) are tied to
this node so as to afford programing the characteristics
necessary for protection of the TMOS device.
Overcurrent Protection Timer
The MC33091A protection scheme is based on the ability
of the MC33091A to constantly sense the voltage drop
developed across the TMOS device. A low voltage drop is
indicative of normal TMOS “on” operation while a large
voltage drop represents the existence of an overcurrent
condition. By monitoring the TMOS drain to source voltage
(VDS) the MC33091A is able to detect a shorted load and
react to disable the TMOS device. The circuit protection
scheme is essentially based on a timer whose rate is
dependent on the magnitude of VDS. If the drain to source
voltage is large (i.e. VDS = VCC), the timer will disable the gate
drive very quickly. If VDS is only slightly above the normal
operating level, the timer will take much longer to disable the
gate drive.
Since the power dissipated in the TMOS device is
proportional to VDS2, low VDS conditions can be tolerated for
a longer time than high VDS conditions. To enhance the
system application, the timer time–out of the MC33091A is
inversely proportional to VDS2. This approach maximizes the
TMOS operating range. The timer parameters are completely
user programmable through the use of external components
affording application usage of a wide variety of TMOS
devices. This is intended to model the generation and
dissipation of heat within the TMOS device.
The external components RX, RT and CT determine the
timer characteristics. Once enabled, the MC33091A will
source a current, ISQ, from the timer pin that is proportional to
VDS2 such that:
ISQ = KVDS2
(1)
where: K = 1/(RX2IQ)
9
MC33091A
With the Input (Pin 7) in a logic high state and no
overcurrent condition exists, the TMOS device will be in the
“on” state. If the TMOS device experiences an overcurrent
condition, ISQ flowing through RT will increase causing CT to
charge up, in turn causing the timer voltage, VT, to exceed the
threshold, VTH, of the upper comparator. This sets the latch
causing the Q output of the latch to go high (and the Q output
to go low), causing the TMOS gate and Fault output (Pin 6) to
be pulled low, disabling the TMOS device. Both the current
squaring circuit (ISQ) and the charge pump are disabled
whenever the Q output of the latch goes low. Using Equation
2, the fault time response for an overcurrent condition can be
written as:
t = –RTCT ln(1–VTH/ISQRT)
(3)
Using Equation 1 and substituting for ISQ in Equation 3:
(4)
t = –RTCT ln[1–(VTHRX2IQ)/(VDS2RT)]
When the timer current (ISQ) is disabled, the attained VTH
voltage at Pin 8 decays according to the RTCT time constant
until the VTL threshold of the lower comparator is reached.
At this point the latch is reset and the TMOS gate, charge
pump and the current squaring circuit are again enabled,
again turning on the TMOS device. The MC33091A will
repeatedly duty cycle the TMOS gate in this manner so long
as the overcurrent condition exists and the input control
signal remains in a high logic state. The Fault output (Pin 6)
will likewise duty cycle.
Consider the case where in Equation 4 the term
(VTHRX2IQ) / (VDS2RT) ≥ 1 such that the time period is
undefined. Solving for VDS for this case yields the minimum
drain to source voltage necessary which will not allow VT to
charge to the VTH threshold of the upper comparator. In other
words, whenever the TMOS on–time period is infinite, no
TMOS overcurrent condition exists. The minimum drain to
source voltage required for uninterrupted continuous TMOS
operation is:
VDS(min) = [(VTHRX2IQ)/RT]1/2 = (VTH/KRT)1/2
(5)
Under normal operating steady state TMOS “on”
conditions; the values chosen for RX and RT should be such
that the upper comparator threshold voltage is never
reached. This insures the TMOS device will always be in
operation so long as the VDS(min) is not exceeded.
The minimum time required for the capacitor CT to charge
up to upper comparator threshold voltage occurs when the
TMOS device experiences maximum current (Imax). This will
10
occur when the load, and in turn the source, are shorted to
ground resulting in the full battery voltage (VS) to appear
directly across the TMOS device. This condition causes
maximum ISQ current to be produced by the current squaring
circuit. The maximum ISQ current experienced is:
(6)
ISQ(max) = KVS2 = (VS/RX)2/IQ
An expression for the minimum time–out is obtained by
substituting IQ of Equation 6 into Equation 3:
t(min) = –RTCT ln[1–VTH/(ISQ(max)RT)]
(7)
Equation 4 is shown graphically along with the asymptotic
limits imposed by Equations 5 and 7 in Figure 29.
100
Figure 29. Theoretical Fault Time versus VDS
RX = 75 k
RT = 200 k
CT = 0.02 µF
VTH = 4.6 V
IQ = 100 mA
I(max) = Select
10–1
VDS(min) = [(VTHRX2IQ) / RT]1/2
t, TIME (s)
IQ is an internal current source parameter of the
MC33091A that has a nominal value of 100 µA and RX is the
external resistor in series with the drain of the TMOS device
that establishes the value of the voltage to current
proportionality constant. Since the parallel combination of RT
and CT appear at the timer pin (VT), the timer pin voltage, VT,
can be written as:
VT(t) = ISQRT[1–e–t/(RTCT)]
(2)
10–2
t = –RTCT In(1 – VTHRX2IQ / VDS2RT)
10–3
10–4
2.0
t(min) = –RTCT In(1 – VTH / I(max)RT)
4.0
6.0
8.0
10
12
14
16
VDS, DRAIN–TO–SOURCE VOLTAGE (V)
When driving incandescent lamp loads, the minimum timer
time–out (time required for the VT voltage to reach VTH
threshold of the upper comparator) should be set long
enough so as to not allow the in–rush current of incandescent
lamp to cause a false trigger, yet short enough to afford the
TMOS device survival protection against direct shorts under
worst case supply and temperature conditions.
TMOS Driver Power Dissipation
Under load short conditions, the MC33091A will duty cycle
the TMOS gate. The power dissipation in this mode can be
significant. For this reason proper heatsinking of the TMOS
device is essential as is the selection of compatible external
components so as to protect the TMOS device from
destruction. In most cases, the heatsink required to handle
the TMOS power dissipation under normal operating
conditions will be adequate to insure the device survives a
short circuit for an indefinite time under worst case conditions.
The MC33091A can protect the TMOS device under a
direct load short condition. If the source voltage is less than
about 1.5 V above ground, which will normally be the case in
the event of a dead short, the MC33091A will clamp the gate
to source voltage at 7.0 V. This action will limit the TMOS
current and power dissipated under a direct load short
condition.
MOTOROLA ANALOG IC DEVICE DATA
MC33091A
The data sheet for the particular TMOS device being used
will normally reveal the current value, IDS(max), to be
expected under a dead short condition. TMOS data sheets
normally depict graphs of drain current versus drain to source
voltage for various gate to source voltages from which the
drain current at 7.0 V VGS, IDS(max), can reasonably be
approximated. Using this information, the peak TMOS power
dissipation under a dead short condition is approximated
to be:
the same time, ISQ is switched off, allowing CT to discharge
through resistor RT to VTL, at which time the TMOS device is
again switched on. This action is repeated so long as the
overload condition exists. The VTL and VTH thresholds are
internally set to approximately 0.95 V and 4.6 V respectively.
The charge time (tc) of CT can be shown as:
PD(peak) = VS(max)IDS(max)
td = –RTCT ln(VTL/VTH)
(8)
tc = –RTCT ln[1–(VTH–VTL)/(ISQRT–VTL)]
(10)
The discharge time (td) of CT can be shown as:
(11)
The average power is equal to the peak power dissipation
multiplied by the duty cycle (DC):
The duty cycle is defined as charge time divided by the
charge plus discharge time and represented by:
PD(avg) = PD(peak)DC
DC = tc/(tc+td)
(9)
As long as the average power, in Equation 9, is less than
the maximum power dissipation of the TMOS device under
normal conditions, the short circuit protection scheme of the
MC33091A will adequately protect the TMOS device. The
duty cycle at which the MC33091A controls the gate can be
determined by using Figure 30.
Figure 30. MC33091A Duty Cycle
versus VDS / VDS(min)
DC, DUTY CYCLE (%)
10
VTH = 4.6 V
VTL = 0.95 V
β = VDS/VDS(min)
8.0
6.0
1
In(VTL/VTH)
1+
(VTH – β2 VTH)
In
(VTL – β2 VTH)
DC =
4.0
2.0
0
2.0
4.0
6.0
8.0
10
12
VDS/VDS(min)
As previously discussed, ISQ is externally dependant on
the sensed VDS voltage developed across the TMOS device
and RX in accordance with Equations 1 and 2. At the onset of
an overload condition, the voltage across CT will be less than
the VTH threshold voltage of the upper comparator with the
TMOS device in an “on” state. ISQ current will increase
dramatically and the timing capacitor CT charges toward VTH.
When the voltage on CT reaches the VTH threshold voltage of
the upper comparator, the upper comparator output goes
high setting the latch output (Q) high, turning on the open
collector NPN transistor and pulling the Fault output low. At
MOTOROLA ANALOG IC DEVICE DATA
(12)
Substituting Equations 10 and 11 into 12:
DC = 1/1+ln(VTL/VTH)/ln{(VTH–β2VTH)/(VTL–β2VTH)} (13)
where: β = VDS/VDS(min)
Notice the duty cycle is dependent only on the ratio of the
drain to source voltage, VDS, of the TMOS device to the
minimum drain to source voltage, VDS(min), allowing
uninterrupted continuous TMOS operation as calculated in
Equation 5. A graph of Equation 13 is shown in Figure 30 and
is valid for any ratio of VDS to VDS(min). Knowing this ratio, the
duty cycle can be determined by using Figure 30 or Equation
13 and knowing the duty cycle, the average power
dissipation can be calculated by using Equation 9.
If the TMOS device experiences a hard load short to
ground a minimum duty cycle will be experienced which can
be calculated. When this condition exists, the TMOS device
experiences a VDS voltage of VS which is sensed by the
MC33091A. The MC33091A very rapidly charges the timing
capacitor CT to VTH shutting down the TMOS device. This
condition produces the minimum duty cycle for the specific
system conditions. The minimum duty cycle can be
calculated for any valid VS voltage by substituting the value of
VS used for VDS in Equation 13 and solving for the duty cycle.
Knowing the duty cycle and peak power allows
determination of the average power as was pointed out in
Equation 9. TMOS data sheets specify the maximum
allowable junction temperature and thermal resistance,
junction–to–case, at which the device may be operated.
Knowing the average power and the device thermal
information, proper heatsinking of the TMOS device can
be determined.
The duty cycle graph (Figure 30) reveals lower values of
VDS(min) produce shorter duty cycles, for given VDS voltages.
The minimum duty cycle, being limited to the case where
VDS = VS, increases as higher values of VS are used.
11
MC33091A
APPLICATION
The following design approach will simplify application of
the MC33091A and will insure the components chosen to be
optimal for a specific application.
1. Characterize the load impedance and determine
the maximum load current possible for the load supply
voltage used.
2. Select a TMOS device capable of handling the
maximum load current. Though the MC33091A will equally
drive our competitors products, it is hoped you will select one
of the many TMOS devices listed in Motorola’s Power
MOSFET Transistor Data Book.
3. Determine the maximum steady state VDS voltage the
TMOS device will experience under normal operating
conditions. Typically, this is the maximum load current
multiplied by the specified RDS(on) of the TMOS device.
Junction temperature considerations should be taken into
account for the RDS(on) value since it is significantly
temperature dependent. Normally, TMOS data sheets depict
the effect of junction temperature on RDS(on) and an RDS(on)
value at some considered maximum junction temperature
should be used. Various graphs relating to RDS(on) are
depicted in Motorola TMOS data sheets. Though Motorola
TMOS devices typically specify a maximum allowable
junction temperature of 150°C, in a practical sense, the user
should strive to keep junction temperature as low as possible
so as to enhance the applications long term reliability. The
maximum steady state VDS voltage the TMOS device will
experience under normal operating conditions is thus:
VDS(norm) = IL(max)RDS(on)
(14)
4. Calculate the maximum power dissipation of the TMOS
device under normal operating conditions:
PD(max) = VDS(on)IL(max)
(15)
5. The calculated maximum power dissipation of the
TMOS device dictates the required thermal impedance for
the application. Knowing this, the selection of an appropriate
heatsink to maintain the junction temperature below the
maximum specified by the TMOS manufacture for operation
can be made. The required overall thermal impedance is:
TRJA = (TJ(max) – TA(max))/PD(max)
(16)
Where T J(max) , the maximum allowable junction
temperature, is found on the TMOS data sheet and TA(max),
the maximum ambient temperature, is dictated by the
application itself.
6. The thermal resistance, TRJA, represents the maximum
overall or total thermal resistance, from junction to the
surrounding ambient, allowable to insure the TMOS
manufactures maximum junction temperature will not be
exceeded. In general, this overall thermal resistance can be
considered as being made up of several separate minor
thermal resistance interfaces comprised of TRJC, TRCS and
TRSA such that:
TRJA = TRJC + TRCS + TRSA
(17)
Where TRJC, TRCS and TRSA represent the junction–to–
case, case–to–heatsink and heatsink–to–ambient thermal
resistances respectively. TRCS and TRSA are the only
parameters the device user can influence.
12
The case–to–heatsink thermal resistance, TRCS, is
material dependent and can be expressed as:
TRCS = ρ
t/A
(18)
Where “ρ” is the thermal resistivity of the heatsink material
(expressed in °C/Watt/Unit Thickness), “t” is the thickness of
heatsink material, and “A” is the contact area of the
case–to–heatsink. Heatsink manufactures specify the value
of TRCS for standard heatsinks. For nonstandard heatsinks,
the user is required to calculate TRCS using some form of the
basic Equation 18.
The required heatsink–to–ambient thermal resistance,
TRSA, can easily be calculated once the terms of Equation 17
are known. Substituting TRJA of Equation 16 into Equation 17
and solving for TRSA produces:
TRSA = (TJ(max)–TA(max))/PD(max)–(TRJC+TRCS) (19)
Consulting the heatsink manufactures catalog will provide
TRCS information for various heatsinks under various
mounting conditions so as to allow easy calculation of TRSA
in units of °C/W (or when multiplied by the power dissipation
produces the heatsink mounting surface temperature rise).
Furthermore, heatsink manufactures typically specify for
various heatsinks, heatsink efficiency in the form of mounting
surface temperature rise above the ambient conditions for
various power dissipation levels. The user should insure that
the heatsink selected will provide a surface temperature rise
somewhat less than the maximum capability of the heatsink
so that the device junction temperature will not be exceeded.
The user should consult the heatsink manufacturers catalog
for this information.
7. Set the value of VDS(min) to something greater than the
normal operating drain to source voltage, VDS(norm), the
TMOS device will experience as calculated in Step 3 above
(Equation 14). From a practical standpoint, a value two or
three times VDS(norm) expected under normal operation will
prove to be a good starting point for VDS(min).
8. Select a value of RT less than 1.0 MΩ for minimal timing
error whose value is compatible with RX (RX will be selected
in Step 9 below). A recommended starting value to use for RT
would be 470 k. The consideration here is that the input
impedance of the threshold comparators are approximately
10 MΩ and if RT values greater than 1.0 MΩ are used,
significant timing errors may be experienced as a result of
input bias current variations of the threshold comparators.
9. Select a value of RX which is compatible with RT. The
value of RX should be between 50 k and 100 k. Recall in
Equation 5 that VDS(min) was determined by the combined
selection of RX and RT. Low values of RX will give large
values for K (K = 4.0 µA/V2 for RX = 50 k) causing ISQ to be
very sensitive to VDS variations (see Equation 1). This is
desirable if a minimum VDS trip point is needed in the 1.0 V
range since small VDS values will generate measurable
currents. However, at high VDS values, TMOS device
currents become excessively large and the current squaring
function begins to deviate slightly from the predicted value
due to high level injection effects occurring in the output PNP
of the current squaring circuit. These effects can be seen
when ISQ exceeds several hundred microamps. See
Figure 22 for graphical aid in the selection of RT and RX.
MOTOROLA ANALOG IC DEVICE DATA
MC33091A
10. Calculate the shorted load average power dissipation
for the application using Equations 8 and 9. This involves
determining the peak shorted load power dissipation of the
TMOS device and gate duty cycle. The duty cycle is based
on VDS(min), the value of VDS under shorted conditions (i.e.
VS(max)).
11. The calculated shorted load average power dissipation
of Step 10 should be less than the maximum power
dissipation under normal operating conditions calculated in
Step 4. If this is not the case, there are two options.
Option one is to reduce the thermal resistance of the
TMOS device heatsink, in other words, use a larger or better
heatsink. This though, is not always practical to do
particularly if restricted by size.
Option two is to set VDS(min) to the lowest practical value.
If for instance VDS(min) is set to 4.0 V when only 2.0 V are
needed, the short circuit duty cycle will be over twice as large,
resulting in double the TMOS device power dissipated.
Keeping VDS(min) to a minimum, reduces the shorted load
average power.
12. Choose a value of CT. The value of CT can be
determined either by trial and error or by characterizing the
VDS waveform for the load and selecting a capacitor value
that generates a minimum fault time curve (see Equation 4)
that encompasses the VDS versus time waveform. The value
of CT has no effect on the duty cycle itself as was pointed out
earlier. See Figure 23 for a graphical selection of CT.
Inductive Loads
The TMOS device is turned off by pulling the gate to near
ground potential. Turning off an inductive load will cause
the source of the TMOS device to go below ground due to
flyback voltage to the point where the TMOS device may
become biased on again allowing the inductive energy to be
dissipated through the load. An internal 14 V zener diode
clamp from the gate to source pin limits how far the source pin
can be pulled below ground. For high inductive loads, it may
be necessary to have an external 10 k current limiting resistor
in series with the source pin to limit the clamp current in the
event the source pin is pulled more than 14 V below ground.
Transient Faults
The MC33091A is not able to withstand automotive
voltage transients directly. By correctly sizing resistor RS and
capacitor CS, the MC33091A can withstand load dump and
other automotive type transients. The VCC voltage is clamped
at approximately 30 V through the use of an internal zener
diode.
Under reverse battery conditions, the load will be
energized in reverse due to the parasitic body diode inherent
in the TMOS device. Under this condition, the drain is
grounded and the MC33091A clamps the gate at 0.7 V below
the battery potential. This turns the TMOS device on in
reverse and minimizes the voltage across the TMOS device
resulting in minimal power dissipation. Neither the
MC33091A nor the TMOS device will be damaged under
such a condition. In addition, if the load can tolerate a reverse
MOTOROLA ANALOG IC DEVICE DATA
polarity, the load will not be damaged. Caution; some
sensitive applications may not tolerate a reverse polarity load
condition with reverse battery polarity.
There is no protection of the TMOS device during a
reverse battery condition if the load itself is already shorted to
ground. The MC33091A will not incur damage under this
specialized reverse battery condition but the TMOS
device may be damaged since there could be significant
energy available from the battery to be dissipated in the
TMOS device.
The MC33091A will withstand a maximum VCC voltage of
28 V and with the proper TMOS device used, the system can
withstand a double battery condition.
Figure 36 depicts a method of protecting the FET from
positive transient voltages in excess of the rated FET
breakdown voltage. The zener voltage, in this case, should
be less than the FET breakdown voltage. The diode, D, is
necessary where reverse battery protection of the gate of the
FET is required.
EMI Concern
The gate capacitance and thus the size of the TMOS
device used will determine the turn–on and turn–off times
experienced. In a practical sense, smaller TMOS devices
have smaller gate capacitances and give rise to higher slew
rates. By way of example, the turn–on of an MPT50N06
TMOS device might be of the order of 80 µs while that of an
MPT8N10 might be 10 µs (see Figure 25). The speed of
turn–on or turn–off can be calculated by assuming the charge
pump to supply approximately 100 µA over the time the gate
capacitance will transition a VGS voltage of 0 V to 10 V. In
reality, the VGS voltage will be greater than 10 V, but the
additional increase in TMOS drain current will be minimal for
VGS voltages greater than 10 V.
The charge pump current is sized so that turn–on time
need not be of concern in all but the most critical of
applications. Where limiting of EMI is of concern, the charge
pump of the MC33091A may be slew rate limited by adding
an external feedback capacitor from the gate–to–source of
the TMOS device for slow down adjustment of both turn–on
and turn–off times (see Figure 33). Figures 31 through 35
depict various methods of modifying the turn–on or turn–off
times.
Figure 35 depicts a method of using only six external
components to decrease turn–off time and clamp the flyback
voltage associated with switching inductive loads. VGS(th)
used in the critical component selection criteria refers to the
gate–to–source threshold voltage of the FET used in the
application.
Caution should be exercised when slowing down the
switching transition time since doing so can greatly increase
the average power dissipation of the TMOS device. The
resulting increase in power dissipation should be taken into
account when selecting the RTCT time constant values
in order to protect the TMOS device from any overcurrent
condition.
13
MC33091A
Figure 31. Slow Down FET Turn–On
Charge
Pump
Figure 32. Slow Down FET Turn–Off
+VS
Charge
Pump
+VS
R
R
Gate
4
Gate
4
D
SRC
D
SRC
1
1
+
+
Load
Load
Figure 33. Slow Down Turn–On and Turn–Off of FET
Charge
Pump
+VS
Figure 34. Independent Slow Down Adjustment
of FET Turn–On and Turn–Off
Charge
Pump
+VS
R(on)
Gate
Gate
4
4
C
R(off)
SRC
SRC
1
1
+
+
Load
Load
Figure 35. Decreased FET Turn–Off Time with
Inductive Flyback Voltage Clamp
Charge
Pump
VTR1
R2 >
VZ – VS
+VS
Charge
Pump
Z
Gate R1
4
+VS
Figure 36. Overvoltage Protection of FET
Gate
10 k
4
Z
D
R1
R2
SRC
1
30 k
10 k
1
+
+
10 k
14
SRC R2
200
Load
Load
MOTOROLA ANALOG IC DEVICE DATA
MC33091A
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
–B–
1
4
DIM
A
B
C
D
F
G
H
J
K
L
M
N
F
–A–
NOTE 2
L
C
J
–T–
N
SEATING
PLANE
D
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
–––
10_
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
–––
10_
0.030
0.040
M
K
G
H
0.13 (0.005)
M
T A
B
M
D SUFFIX
PLASTIC PACKAGE
CASE 751–05
(SO–8)
ISSUE N
–A–
8
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
5
–B–
1
4X
P
0.25 (0.010)
4
M
B
M
G
R
C
–T–
8X
K
D
0.25 (0.010)
M
T B
SEATING
PLANE
S
A
M_
S
MOTOROLA ANALOG IC DEVICE DATA
X 45 _
F
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.18
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.189
0.196
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.007
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
15
MC33091A
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
How to reach us:
USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
MFAX: [email protected] – TOUCHTONE 602–244–6609
INTERNET: http://Design–NET.com
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
16
◊
*MC33091A/D*
MOTOROLA ANALOG IC DEVICE
DATA
MC33091A/D