MOTOROLA MLD1N06CL

MOTOROLA
Order this document
by MLD1N06CL/D
SEMICONDUCTOR TECHNICAL DATA
 SMARTDISCRETES 
Internally Clamped, Current Limited
N–Channel Logic Level Power MOSFET
The MLD1N06CL is designed for applications that require a rugged power switching
device with short circuit protection that can be directly interfaced to a microcontrol unit
(MCU). Ideal applications include automotive fuel injector driver, incandescent lamp
driver or other applications where a high in–rush current or a shorted load condition could
occur.
This logic level power MOSFET features current limiting for short circuit protection,
integrated Gate–Source clamping for ESD protection and integral Gate–Drain clamping
for over–voltage protection and Sensefet technology for low on–resistance. No additional
gate series resistance is required when interfacing to the output of a MCU, but a 40 kΩ
gate pulldown resistor is recommended to avoid a floating gate condition.
The internal Gate–Source and Gate–Drain clamps allow the device to be applied
without use of external transient suppression components. The Gate–Source clamp
protects the MOSFET input from electrostatic voltage stress up to 2.0 kV. The
Gate–Drain clamp protects the MOSFET drain from the avalanche stress that occurs
with inductive loads. Their unique design provides voltage clamping that is essentially
independent of operating temperature.
The MLD1N06CL is fabricated using Motorola’s SMARTDISCRETES technology which
combines the advantages of a power MOSFET output device with the on–chip protective
circuitry that can be obtained from a standard MOSFET process. This approach offers an
economical means of providing protection to power MOSFETs from harsh automotive and
industrial environments. SMARTDISCRETES devices are specified over a wide temperature range from –50°C to 150°C.
MLD1N06CL
Motorola Preferred Device
VOLTAGE CLAMPED
CURRENT LIMITING
MOSFET
62 VOLTS (CLAMPED)
RDS(on) = 0.75 OHMS
D
R1
G
R2
S
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
Clamped
Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
VDGR
Clamped
Vdc
Gate–to–Source Voltage — Continuous
VGS
±10
Vdc
Drain Current — Continuous
— Single Pulse
ID
IDM
Self–limited
1.8
Adc
Apk
Total Power Dissipation
Operating and Storage Temperature Range
Electrostatic Discharge Voltage (Human Model)
PD
40
Watts
TJ, Tstg
–50 to 150
°C
ESD
2.0
kV
RθJC
RθJA
RθJA
3.12
100
71.4
°C/W
TL
260
°C
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
— Junction to Ambient
— Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes,
1/8″ from case for 5 sec.
CASE 369A–13, Style 2
DPAK Surface Mount
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS
Single Pulse Drain–to–Source Avalanche Energy
Starting TJ = 25°C
EAS
80
mJ
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
SMARTDISCRETES is a trademark of Motorola, Inc.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Preferred devices are Motorola recommended choices for future use and best overall value.
TMOS
Motorola
Motorola, Inc.
1996 Power MOSFET Transistor Device Data
1
MLD1N06CL
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
Unit
59
59
62
62
65
65
—
—
0.6
6.0
5.0
20
—
—
0.5
1.0
5.0
20
1.0
0.6
1.5
—
2.0
1.6
—
—
—
—
0.63
0.59
1.1
1.0
0.75
0.75
1.9
1.8
—
1.1
1.5
2.0
1.1
2.3
1.3
2.75
1.8
gFS
1.0
1.4
—
mhos
td(on)
—
1.2
2.0
ns
tr
—
4.0
6.0
td(off)
—
4.0
6.0
tf
—
3.0
5.0
—
4.5
—
—
7.5
—
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Internally Clamped)
(ID = 20 mAdc, VGS = 0 Vdc)
(ID = 20 mAdc, VGS = 0 Vdc, TJ = 150°C)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 45 Vdc, VGS = 0 Vdc)
(VDS = 45 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate–Source Leakage Current
(VG = 5.0 Vdc, VDS = 0 Vdc)
(VG = 5.0 Vdc, VDS = 0 Vdc, TJ = 150°C)
IGSS
Vdc
µAdc
µAdc
ON CHARACTERISTICS(1)
Gate Threshold Voltage
(ID = 250 µAdc, VDS = VGS)
(ID = 250 µAdc, VDS = VGS, TJ = 150°C)
VGS(th)
Static Drain–to–Source On–Resistance
(ID = 1.0 Adc, VGS = 4.0 Vdc)
(ID = 1.0 Adc, VGS = 5.0 Vdc)
(ID = 1.0 Adc, VGS = 4.0 Vdc, TJ = 150°C)
(ID = 1.0 Adc, VGS = 5.0 Vdc, TJ = 150°C)
RDS(on)
Static Source–to–Drain Diode Voltage (IS = 1.0 Adc, VGS = 0 Vdc)
Vdc
Ohms
VSD
Static Drain Current Limit
(VGS = 5.0 Vdc, VDS = 10 Vdc)
(VGS = 5.0 Vdc, VDS = 10 Vdc, TJ = 150°C)
Vdc
ID(lim)
Forward Transconductance (ID = 1.0 Adc, VDS = 10 Vdc)
Adc
RESISTIVE SWITCHING CHARACTERISTICS(2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 25 Vdc, ID = 1.0 Adc,
VGS(on) = 5.0 Vdc, RGS = 50 Ohms)
Fall Time
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from drain lead 0.25” from package to center of die)
LD
Internal Source Inductance
(Measured from the source lead 0.25” from package to source bond pad)
LS
nH
nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
TJ = 25°C
3
10 V
6V
8V
4V
2
VGS = 3 V
1
0
–50°C
3
25°C
2
TJ = 150°C
1
0
0
2
4
6
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. Output Characteristics
2
VDS ≥ 7.5 V
4
ID , DRAIN CURRENT (AMPS)
ID , DRAIN CURRENT (AMPS)
4
8
0
2
4
6
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
8
Figure 2. Transfer Function
Motorola TMOS Power MOSFET Transistor Device Data
MLD1N06CL
Motorola TMOS Power MOSFET Transistor Device Data
ID(lim) , DRAIN CURRENT (AMPS)
4
VGS = 5 V
VDS = 7.5 V
3
2
1
0
–50
0
50
100
TJ, JUNCTION TEMPERATURE (°C)
150
Figure 3. ID(lim) Variation
With Temperature
R DS(on), ON–RESISTANCE (OHMS)
4
ID = 1 A
3
2
25°C
150°C
TJ = –50°C
1
0
0
2
4
6
8
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
10
Figure 4. RDS(on) Variation With
Gate–To–Source Voltage
1.25
ID = 1 A
RDS(on), ON–RESISTANCE (OHMS)
THE SMARTDISCRETES CONCEPT
From a standard power MOSFET process, several active
and passive elements can be obtained that provide on–chip
protection to the basic power device. Such elements require
only a small increase in silicon area and/or the addition of one
masking layer to the process. The resulting device exhibits
significant improvements in ruggedness and reliability as well
as system cost reduction. The SMARTDISCRETES device
functions can now provide an economical alternative to smart
power ICs for power applications requiring low on–resistance,
high voltage and high current.
These devices are designed for applications that require a
rugged power switching device with short circuit protection
that can be directly interfaced to a microcontroller unit (MCU).
Ideal applications include automotive fuel injector driver,
incandescent lamp driver or other applications where a high
in–rush current or a shorted load condition could occur.
OPERATION IN THE CURRENT LIMIT MODE
The amount of time that an unprotected device can withstand the current stress resulting from a shorted load before
its maximum junction temperature is exceeded is dependent
upon a number of factors that include the amount
of heatsinking that is provided, the size or rating of the device,
its initial junction temperature, and the supply voltage. Without
some form of current limiting, a shorted load can raise a device’s junction temperature beyond the maximum rated operating temperature in only a few milliseconds.
Even with no heatsink, the MLD1N06CL can withstand a
shorted load powered by an automotive battery (10 to 14
Volts) for almost a second if its initial operating temperature is
under 100°C. For longer periods of operation in the current–
limited mode, device heatsinking can extend operation from
several seconds to indefinitely depending on the amount of
heatsinking provided.
SHORT CIRCUIT PROTECTION AND THE EFFECT OF
TEMPERATURE
The on–chip circuitry of the MLD1N06CL offers an integrated
means of protecting the MOSFET component from high in–rush
current or a shorted load. As shown in the schematic diagram,
the current limiting feature is provided by an NPN transistor and
integral resistors R1 and R2. R2 senses the current through the
MOSFET and forward biases the NPN transistor’s base as the
current increases. As the NPN turns on, it begins to pull gate
drive current through R1, dropping the gate drive voltage across
it, and thus lowering the voltage across the gate–to–source of
the power MOSFET and limiting the current. The current limit is
temperature dependent as shown in Figure 3, and decreases
from about 2.3 Amps at 25°C to about 1.3 Amps at 150°C.
Since the MLD1N06CL continues to conduct current and dissipate power during a shorted load condition, it is important to
provide sufficient heatsinking to limit the device junction temperature to a maximum of 150°C.
The metal current sense resistor R2 adds about 0.4 ohms to
the power MOSFET’s on–resistance, but the effect of temperature on the combination is less than on a standard MOSFET due
to the lower temperature coefficient of R2. The on–resistance
variation with temperature for gate voltages of 4 and 5 Volts is
shown in Figure 5.
Back–to–back polysilicon diodes between gate and source
provide ESD protection to greater than 2 kV, HBM. This on–chip
protection feature eliminates the need for an external Zener
diode for systems with potentially heavy line transients.
1
VGS = 4 V
0.75
VGS = 5 V
0.5
0.25
–50
0
50
100
TJ, JUNCTION TEMPERATURE (°C)
150
Figure 5. On–Resistance Variation With
Temperature
3
100
80
60
40
20
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
150
BV(DSS) , DRAIN–SOURCE SUSTAINING VOLTAGE (VOLTS)
WAS , SINGLE PULSE AVALANCHE ENERGY (mJ)
MLD1N06CL
64
63
62
61
60
–50
Figure 6. Single Pulse Avalanche Energy
versus Junction Temperature
MAXIMUM DC VOLTAGE CONSIDERATIONS
The maximum drain–to–source voltage that can be continuously applied across the MLD1N06CL when it is in current
limit is a function of the power that must be dissipated. This
power is determined by the maximum current limit at maximum rated operating temperature (1.8 A at 150°C) and not
the RDS(on). The maximum voltage can be calculated by the
following equation:
(150 – TA)
Vsupply =
ID(lim) (RθJC + RθCA)
where the value of RθCA is determined by the heatsink that is
being used in the application.
4
150
Figure 7. Drain–Source Sustaining
Voltage Variation With Temperature
DUTY CYCLE OPERATION
When operating in the duty cycle mode, the maximum
drain voltage can be increased. The maximum operating
temperature is related to the duty cycle (DC) by the following
equation:
TC = (VDS x ID x DC x RθCA) + TA
The maximum value of VDS applied when operating in a
duty cycle mode can be approximated by:
VDS =
150 – TC
ID(lim) x DC x RθJC
10
ID , DRAIN CURRENT (AMPS)
FORWARD BIASED SAFE OPERATING AREA
The FBSOA curves define the maximum drain–to–source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25°C and a maximum junction temperature of 150°C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, “Transient Thermal Resistance — General
Data and Its Use” provides detailed instructions.
0
50
100
TJ, JUNCTION TEMPERATURE (°C)
VGS = 10 V
SINGLE PULSE
TC = 25°C
10 µs
100 µs
1.0
1 ms
10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
dc
1.0
10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
100
Figure 8. Maximum Rated Forward Bias
Safe Operating Area (MLD1N06CL)
Motorola TMOS Power MOSFET Transistor Device Data
MLD1N06CL
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1.0
D = 0.5
0.2
0.1
P(pk)
0.1 0.05
0.02
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
1.0E – 05
1.0E – 04
1.0E – 03
1.0E – 02
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) RθJC(t)
1.0E – 01
1.0E+00
1.0E+01
t, TIME (s)
Figure 9. Thermal Response (MLD1N06CL)
RL
Vin
PULSE GENERATOR
Rgen
Vout
toff
ton
VDD
td(on)
tr
90%
td(off)
tf
90%
DUT
OUTPUT, Vout
INVERTED
z = 50 Ω
10%
50Ω
90%
50 Ω
50%
INPUT, Vin
Figure 10. Switching Test Circuit
ACTIVE CLAMPING
SMARTDISCRETES technology can provide on–chip realization of the popular gate–to–source and gate–to–drain
Zener diode clamp elements. Until recently, such features
have been implemented only with discrete components
which consume board space and add system cost. The
SMARTDISCRETES technology approach economically
melds these features and the power chip with only a slight
increase in chip area.
In practice, back–to–back diode elements are formed in a
polysilicon region monolithicly integrated with, but electrically
isolated from, the main device structure. Each back–to–back
diode element provides a temperature compensated voltage
element of about 7.2 volts. As the polysilicon region is
formed on top of silicon dioxide, the diode elements are free
from direct interaction with the conduction regions of the
power device, thus eliminating parasitic electrical effects
while maintaining excellent thermal coupling.
To achieve high gate–to–drain clamp voltages, several
voltage elements are strung together; the MLD1N06CL uses
8 such elements. Customarily, two voltage elements are
used to provide a 14.4 volt gate–to–source voltage clamp.
For the MLD1N06CL, the integrated gate–to–source voltage
Motorola TMOS Power MOSFET Transistor Device Data
50%
PULSE WIDTH
10%
Figure 11. Switching Waveforms
elements provide greater than 2.0 kV electrostatic voltage
protection.
The avalanche voltage of the gate–to–drain voltage clamp
is set less than that of the power MOSFET device. As soon
as the drain–to–source voltage exceeds this avalanche voltage, the resulting gate–to–drain Zener current builds a gate
voltage across the gate–to–source impedance, turning on
the power device which then conducts the current. Since virtually all of the current is carried by the power device, the
gate–to–drain voltage clamp element may be small in size.
This technique of establishing a temperature compensated
drain–to–source sustaining voltage (Figure 7) effectively removes the possibility of drain–to–source avalanche in the
power device.
The gate–to–drain voltage clamp technique is particularly
useful for snubbing loads where the inductive energy would
otherwise avalanche the power device. An improvement in
ruggedness of at least four times has been observed when
inductive energy is dissipated in the gate–to–drain clamped
conduction mode rather than in the more stressful gate–to–
source avalanche mode.
5
MLD1N06CL
TYPICAL APPLICATIONS: INJECTOR DRIVER, SOLENOIDS, LAMPS, RELAY COILS
The MLD1N06CL has been designed to allow direct interface to the output of a microcontrol unit to control an isolated
load. No additional series gate resistance is required, but a
40 kΩ gate pulldown resistor is recommended to avoid a
floating gate condition in the event of an MCU failure. The internal clamps allow the device to be used without any external transistent suppressing components.
VBAT
VDD
D
G
MCU
MLD1N06CL
S
PACKAGE DIMENSIONS
–T–
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
4
Z
A
S
1
2
3
U
K
F
J
L
D
G
STYLE 2:
PIN 1.
2.
3.
4.
H
2 PL
0.13 (0.005)
M
GATE
DRAIN
SOURCE
DRAIN
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
INCHES
MIN
MAX
0.235
0.250
0.250
0.265
0.086
0.094
0.027
0.035
0.033
0.040
0.037
0.047
0.180 BSC
0.034
0.040
0.018
0.023
0.102
0.114
0.090 BSC
0.175
0.215
0.020
0.050
0.020
–––
0.030
0.050
0.138
–––
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.84
1.01
0.94
1.19
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.45
5.46
0.51
1.27
0.51
–––
0.77
1.27
3.51
–––
T
CASE 369A–13
ISSUE W
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
USA / EUROPE: Motorola Literature Distribution;
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,
6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315
MFAX: [email protected] – TOUCHTONE (602) 244–6609
INTERNET: http://Design–NET.com
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
6
◊
*MLD1N06CL/D*
Motorola TMOS Power MOSFET Transistor
Device Data
MLD1N06CL/D