FAIRCHILD FAN50FC3

FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase
FastvCore™ Buck Controller
Features
Description
ƒ
FastvCore™ nonlinear control for fast transient and
to minimizes the number of output caps required
ƒ
Selectable 2- or 3-phase operation at up to
1MHz per phase
ƒ
±7.7mV worst-case differential sensing error over
temperature
ƒ
ƒ
Active current balancing between output phases
ƒ
ƒ
ƒ
0.5V to 1.6V output
The FAN50FC3 device is a multi-phase buck switching
regulator controller optimized to convert a 12V input
supply to the processor core voltage required by highperformance Intel® processors. It has an internal, 8-bit
DAC that converts a digital voltage identification (VID)
code sent from the processor, to set the output voltage
between 0.5V and 1.6V in 6.25mV steps. It outputs
PWM signals to external MOSFET drivers that drive the
switching power MOSFETs. The switching frequency of
the design is programmable by a single resistor value
and the number of phases can be programmed to
support 2- or 3-phase applications.
ƒ
ƒ
Programmable soft-start ramp
Power Good and Crowbar blanking supports
on-the-fly VID code changes
Usable for Intel® VR10 and VR11 designs
Selectable VR10 extended (7-bit) and VR11 (8-bit)
VID tables
Programmable short-circuit protection and latch-off
delay
Applications
ƒ
Desktop PC/Server processor power supplies for
existing and next-generation Intel® processors
ƒ
VRM modules
The FAN50FC3 also includes programmable no-load
offset and droop functions to adjust the output voltage
as a function of the load current, as required by the
Intel® specifications. The FAN50FC3 also provides an
accurate and reliable short-circuit protection function
with an adjustable over-current set point.
FastvCore™ technology greatly improves the fast
transient response required by today’s high-performance
processors. This allows fewer output capacitors to be
used in the application.
The FAN50FC3 is specified over the commercial
temperature range of 0°C to +85°C and is available in a
32-lead MLP package.
Related Applications Notes
ƒ
AN-6052 — Instructions for the Multi-Phase VR11
®
MathCad Design Tool
Ordering Information
Part Number
Pb-Free
Operating
Temperature Range
Package
Packing Method
FAN50FC3MPX
Yes
0 to 85°C
32-Lead, Molded Leadless
Package (MLP)
Tape and Reel
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
www.fairchildsemi.com
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
June 2007
VCC
RT
UVLO
SHUT DOWN
& BIAS
RAMPADJ
OSCILLATOR
OD
SET
GND
EN
RESET
PWM1
RESET
PWM2
RESET
2/3 PHASE
LOGIC
PWM3
Threshold
CURRENT
BALANCE
CIRCUIT
EN
DAC + OVP
CSREF
DAC - UVP
PWRGD
CURR ENT
LIMIT
CROWBAR
DELAY
SW1
SW2
SW3
VOSADJ
ILIMIT
CSCOMP
CURRENT
LIMIT
CIRCUIT
DELAY
CSREF
CSSUM
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
Block Diagram
Z
+
+
-
COMP
PRECISION
REFERENCE
-
FB
FBRTN
START UP
CONTROL
+
BOOT CONTROL
DAC
BUFF
VID DAC
VIDSEL
SS
VID7 VID6 VID5 VID4 VID3
VID2 VID1 VID0
Figure 1. Block Diagram
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
www.fairchildsemi.com
2 of 21
VID6
25
VID5
26
VID4
27
VID3
28
VID2
29
VCC
PWM1
PWM2
PWM3
SW1
SW2
SW3
23
22
21
20
19
18
17
VID7
24
Exposed Paddle on
Bottom of Package
FAN50FC3
16
VOSADJ
15
OD#
14
GND
13
CSCOMP
12
CSSUM
CSREF
7
8
ILIMIT
6
SS
DELAY
5
RT
COMP
9
4
32
FB
VIDSEL
3
RAMPADJ
2
10
FBRTN
31
PWRGD
VID0
1
30
EN
VID1
11
Figure 2. Pin Assignments
Pin Definitions
Pin #
Name
Description
1
EN
2
PWRGD
Power Good Output. Open-drain output that pulls to GND when the output voltage is
outside the proper operating range.
3
FBRTN
Feedback Return. VID DAC and error amplifier reference for remote sensing output
voltage.
4
FB
Feedback Input. Error amplifier input for remote sensing output voltage. A positive
internal current source is connected to this pin to allow the output voltage to be offset
lower than the DAC voltage.
5
COMP
6
SS
Soft-Start Input. An external capacitor connected between this pin and GND sets the
soft-start ramp-up time.
7
DELAY
Delay Timer Input. An external capacitor connected between this pin and GND sets
the over-current latch-off delay time, BOOT voltage hold time, EN delay time, and
PWRGD delay time.
8
ILIMIT
Current Limit Set. An external resistor from this pin to GND sets the current limit
threshold of the converter.
9
RT
10
RAMPADJ
11
CSREF
Current-Sense Amplifier Positive Input. The voltage on this pin is used as the
reference for the current-sense amplifier. The Power Good and Crowbar functions are
internally connected to this pin.
12
CSSUM
Current-Sense Amplifier Negative Input.
13
CSCOMP
Power Supply Enable Input. Analog comparator input with hysteresis. If the input
voltage is higher than the internal threshold, the controller is enabled; if lower, the
controller is disabled.
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
Pin Assignments
Error Amplifier Output. For loop compensation.
Frequency Set Input. An external resistor connected between this pin and GND sets
the oscillator frequency of the device.
PWM Ramp Set Input. An external resistor connected between this pin and the
converter input voltage sets the internal PWM ramp.
Current-Sense Amplifier Compensation Output.
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
www.fairchildsemi.com
3 of 21
14
GND
Ground. Biasing and logic output signals of the device are referenced to this ground.
15
OD#
Output Disable. This pin is actively pulled LOW when the EN input is low or when VCC
is below the UVLO threshold, to disable the external MOSFET drivers.
16
VOSADJ
17 to 19
SW3 to
SW1
Switching Node Current Balance Inputs. Sense the switching side of the inductor
and used to measure the current level in each phase. The SW pins of unused phases
should be left open.
20 to 22
PWM3 to
PWM1
PWM Outputs. Each output is connected to the input of an external MOSFET driver,
such as the FAN5109. Connecting the PWM3 output to VCC disables that phase,
allowing the FAN50FC3 to operate as a 2-phase controller.
23
VCC
24 to 31
VID7 to
VID0
Voltage Identification Code Inputs. These digital inputs are connected to the internal
DAC and used to program the output voltage. These pins have 1µA internal pull-down;
if they are left open, the input state is decoded as logic LOW.
32
VIDSEL
VID Table Select Input. A logic LOW selects the extended VR10 DAC table and a logic
HIGH selects the VR11 DAC table. This pin has a 1µA internal pull-down; if left open,
the input state is decoded as logic LOW.
Exposed
Paddle
Internally Connected to Die Ground. May be connected to ground or left floating.
Connect to ground for lowest package thermal resistance.
FastvCore™ VOS Adjustment Input. This signal is used as a control input for the
FastvCore™ circuit.
Supply Voltage.
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
Pin Definitions (Continued)
www.fairchildsemi.com
4 of 21
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
Supply Voltage, VCC
-0.3
+15
V
FBRTN
-0.3
+0.3
V
RAMPADJ, PWM3
-0.3
VCC +0.3
V
SW1 – SW3
-10
+25
V
All Other Inputs and Outputs
-0.3
+5.5
V
0
+125
°C
-65
+150
°C
°C
Operating Junction Temperature
TJ
TSTG
Storage Temperature
TLS
Lead Soldering Temperature (10 Seconds)
300
TLI
Lead Infrared Temperature (15 Seconds)
260
°C
θJA
Thermal Resistance, Junction-to-Ambient
45
°C/W
(1)
Note:
1. Junction-to-ambient thermal resistance, θJA, is a strong function of PCB material, board thickness, thickness and
number of copper planes, number of via used, diameter of via used, available copper surface, and attached heat
sink characteristics.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
VCC
Supply Voltage
TA
Ambient Temperature
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
Conditions
VCC to GND
Min.
Typ.
Max.
Unit
9.6
12.0
14.4
V
+85
°C
0
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
Absolute Maximum Ratings
www.fairchildsemi.com
5 of 21
VCC = 12V, FBRTN = GND, and TA = +25°C. The • denotes specifications which apply over the full operating
temperature range.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
Error Amplifier
VCOMP
VFB
• 0.5
Output Voltage Range
Accuracy
VFB(BOOT) Accuracy
Load Line Droop Accuracy
Relative to nominal DAC output, referenced to
FBRTN. (see Figure 3)
•
VRM11 VID Range: 1.00625V to 1.60000V
During Start-up
•
CSREF-CSCOMP= 80mV (see Figure 5)
• -78
•
Differential Non-Linearity
ΔVFB
Line Regulation
4.0
-7.7
+7.7 mV
1.092 1.1001.108
-80
-1
VCC =10V to 14V
V
V
-82
mV
+1
LSB
0.05
%
Input Bias Current
• 13.5
15
16.5
µA
IFBRTN
FBRTN Current
•
70
95
µA
IO(ERR)
Output Current
IFB
GBW(ERR) Gain Bandwidth Product
Slew Rate
VCSCOMP CSCOMP Voltage Range
tBOOT
BOOT Voltage Hold Time
FB forced to VOUT -3%
500
µA
(3)
COMP = FB
20
MHz
COMP = FB(3)
25
V/µs
• -250
Relative to CSREF
CDELAY = 10nF
+250 mV
2
ms
VID Inputs and VIDSEL
VIL(VID)
Input Low Voltage
VIDx, VIDSEL
•
0.4
V
VIH(VID)
Input High Voltage
VIDx, VIDSEL
• 0.8
3.3
V
VIL(VID)
Select VR10 Table
VIDSEL Logic LOW
0.4
V
VIH(VID)
Select VR11 Table
VIDSEL Logic HIGH
IIN(VID)
Input Current, VID Low
0.8
3.3
-1
V
µA
tDLY(VID)
VID Transition Delay Time
VID code change to FB change(3)
• 200
ns
tDLY(CPU)
No CPU Detection Turn-off
Delay Time
VID code change to off state to PWM going
LOW(3)
• 200
ns
Oscillator
fOSC
fPHASE
VRT
Frequency Variation
TA = 25C, RT= 200K, 3-phase
Output Voltage
RT =100kΩ to GND
VRAMPADJ RAMPADJ Output Voltage
IRAMPADJ
• 0.25
Frequency
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
Electrical Characteristics
4.50 MHz
-20% 400 20% kHz
• 1.9
2.0
VRAMPADJ = VDAC + 2kΩ * (VCC – VDAC) / (RRAMPADJ
• -50
+ 2KΩ)
RAMPADJ Input Current
Range
1
2.1
V
+50
mV
50
µA
Current-Sense Amplifier
VOS(CSA)
IBIAS(CSSUM)
Offset Voltage
Input Bias Current (for
CSSUM)
IBIAS(CSREF) Input Current (for CSREF)
GBW(CSA) Gain Bandwidth Product
VCSACM
CSSUM – CSREF (see Figure 4)
Current drawn by CSREF Pin
+1.0 mV
• -50
+50
nA
•
+3
µA
-3
(3)
CSSUM = CSCOMP
10
(3)
Slew Rate
CCSCOMP = 10pF
Input Common-Mode Range
CSSUM and CSREF
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
• -1.0
MHz
10
•
0
V/µs
3.2
V
www.fairchildsemi.com
6 of 21
VCC = 12V, FBRTN = GND, and TA = +25°C. The • denotes specifications which apply over the full operating
temperature range.
Symbol
Parameter
Conditions
Min. Typ. Max.
Unit
Current-Sense Amplifier (Continued)
• 0.05
Output Voltage Range
ICSCOMP
Output Current
3.20
1
V
mA
Current Balance Circuit
VSW(x)CM
Common Mode Range(3)
• -600
+200
mV
RSW(x)
Input Resistance
SW(x) = 0V
•
35
50
65
kΩ
ISW(x)
Input Current
SW(x) = 0V
•
1.6
3.3
5.0
µA
Input Current Matching
SW(x) = 0V
•
-5
+5
%
Output Voltage
RILIMT = 143kΩ
•
1.6
1.8
V
Output Current
RILIMT = 143kΩ
•
60
ΔISW(x)
Current Limit Comparator
VILIMIT
IILIMIT
Maximum Output Current
VCL
Current Limit Threshold Voltage
VCSREF − VCSCOMP, RILIMT = 143kΩ
Current Limit Setting Ratio
VCL / IILIMT
1.7
12
• 100
µA
µA
120
140
10
mV
mV/µA
Delay Timer
Normal Mode Output Current
•
IDELAY(CL)
Output Current in Current Limit
• 3.00 3.75 4.50
µA
VDELAY(TH)
Threshold Voltage
IDELAY
12
15
18
µA
•
1.6
1.7
1.8
V
•
12
15
18
µA
Soft-Start
I(SS)
Output Current
During Start-up
Enable Input
VTH(EN)
Threshold Voltage
• 800
850
900
mV
VHYS(EN)
Threshold Hysteresis
•
100
130
mV
IIN(EN)
Enable Input Current
Turn-On Delay
Start-up sequence, EN>950mV,
CDELAY = 10nF
VOL(ODB)
Output Voltage LOW
IPWM(SINK) = 400μA
•
VOH(ODB)
Output Voltage HIGH
IPWM(SOURCE) = 400μA
•
tDELAY(EN)
80
1
µA
2
ms
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
Electrical Characteristics (Continued)
#OD Output
160
4
400
5
mV
V
Power-Good Comparator
VPWRGD(UV)
Under-Voltage Threshold
Relative to Nominal DAC Output
• -300 -250 -200
mV
VPWRGD(OV)
Over-Voltage Threshold
Relative to Nominal DAC Output
• 100
150
200
mV
VOL(PWRGD)
Output Low Voltage
IPWRGD(SINK) = -4mA
•
200
300
mV
t1PG(DLY)
Power Good Delay Time 1
Start-up Sequence; CDELAY = 10nF;
Power Good Blanking Time
•
2
ms
t2PG(DLY)
Power Good Delay Time 2
VID Code Changing; CDELAY = 10nF;
• 100
Power Good Blanking Time
250
µs
t3PG(DLY)
Power Good Delay Time 3
VID Code Static; CDELAY = 10nF;
Power Good Blanking Time
200
ns
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
(3)
• 100
www.fairchildsemi.com
7 of 21
VCC = 12V, FBRTN = GND, and TA = +25°C. The • denotes specifications which apply over the full operating
temperature range.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
Power-Good Comparator (Continued)
Crowbar Trip Point
Relative to Nominal DAC Output
•
100
150
200
mV
Crowbar Reset Point
Relative to FBRTN
•
250
300
350
mV
t1CROWBAR
Crowbar Delay Time 1
VID Code Change
Over-Voltage to PWM Going LOW •
Crowbar Blanking Time
100
250
µs
t2CROWBAR
Crowbar Delay Time 2
VID Code Static
Over-Voltage to PWM going LOW •
Crowbar Blanking Time
400
ns
VOL(VRTM)
Output Voltage Low
IPWM(SINK) = 400µA
•
160
VOH(VRTM)
Output Voltage High
IPWM(SOURCE) = 400µA
•
Phase Disable Voltage
Applicable to PWM3 pins only.
Connect this pin to VCC to disable • VCC -.1
the phase.(4)
DC Supply Current
EN = Logic HIGH
•
VUVLO
UVLO Threshold
VCC Rising
•
6.5
6.9
7.3
V
VUVLO_HYS
UVLO Hysteresis
•
0.7
0.9
1.1
V
VCROWBAR
VCR_RST
PWM Outputs
VDIS
4
400
mV
5
V
V
Input Supply
IDC
8
12
mA
Notes:
2. Limits at operating temperature extremes are guaranteed by design, characterization, and statistical quality control.
3. AC specifications are guaranteed by design and characterization; not production tested.
4. To operate the FAN50FC3 with fewer than three phases, PWM3 should be connected to VCC to disable this
phase. See the Theory of Operation section for details.
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
Electrical Characteristics (Continued)
www.fairchildsemi.com
8 of 21
12 V
1.25 V
VCC
VID0
VIDSEL
VID1
EN
VID2
CSCOMP
VID3
CSSUM
VID4
CSREF
VID5
20k
100nF
12 V
1k
250k
10nF
10nF
VID7
COMP
SW1
ILIMIT
SW2
SS
SW3
VCC
100nF
8
8 Bit
Code
13
CSCOMP
39k
12
VID6
FB
23
CSSUM
-
CSREF
+
1k
CSA
11
+
V
1V
-
14
GND
DELAY
GND
FBRTN
Figure 3. Closed-Loop Output Voltage Accuracy
Figure 4. Current-Sense Amplifier VOS
Rt as a function of Oscillator Frequency
62
8
1000
COMP
4
FB
8
20
1
17
0
14
7
12
9
11
5
10
4
94
86
79
72
67
62
58
54
51
48
45
43
40
38
5
24
30
41
4
23 VCC
Rt (kΩ)
10k
100
13 CSCOMP
V
dV
+
3
12 V
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
Test Diagrams
11 CSREF
+
V
V
-
14 GND
10
0
1000
2000
3000
4000
5000
Oscillator Frequency (kHz)
Figure 5. Droop Voltage Accuracy
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
Figure 6. RT Required to Set Oscillator Frequency
www.fairchildsemi.com
9 of 21
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
Output Voltage Programming Codes (extended VR10); 0 = logic LOW; 1 = logic HIGH.
VID3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
VID2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
VID1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
VID0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
VID5
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VOUT (V)
OFF
OFF
OFF
OFF
1.09375
1.10000
1.10625
1.11250
1.11875
1.12500
1.13125
1.13750
1.14375
1.15000
1.15625
1.16250
1.16875
1.17500
1.18125
1.18750
1.19375
1.20000
1.20625
1.21250
1.21875
1.22500
1.23125
1.23750
1.24375
1.25000
1.25625
1.26250
1.26875
1.27500
1.28125
1.28750
1.29375
1.30000
1.30625
1.31250
1.31875
1.32500
1.33125
1.33750
1.34375
1.35000
1.35625
1.36250
1.36875
1.37500
1.38125
1.38750
1.39375
1.40000
1.40625
1.41250
1.41875
1.42500
1.43125
1.43750
1.44375
1.45000
1.45625
1.46250
1.46875
1.47500
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
Table 1.
www.fairchildsemi.com
10 of 21
VID3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
VID2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
VID0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VOUT (V)
1.48125
1.48750
1.49375
1.50000
1.50625
1.51250
1.51875
1.52500
1.53125
1.53750
1.54375
1.55000
1.55625
1.56250
1.56875
1.57500
1.58125
1.58750
1.59375
1.60000
0.83125
0.83750
0.84375
0.85000
0.85625
0.86250
0.86875
0.87500
0.88125
0.88750
0.89375
0.90000
0.90625
0.91250
0.91875
0.92500
0.93125
0.93750
0.94375
0.95000
0.95625
0.96250
0.96875
0.97500
0.98125
0.98750
0.99375
1.00000
1.00625
1.01250
1.01875
1.02500
1.03125
1.03750
1.04375
1.05000
1.05625
1.06250
1.06875
1.07500
1.08125
1.08750
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
www.fairchildsemi.com
11 of 21
HEX
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Output Voltage Programming Codes (8 Bit) 0 = logic LOW; 1 = logic HIGH. (MSB: VID7, LSB: VID0;
11110001b = F1h)
Voltage
OFF
OFF
1.60000
1.59375
1.58750
1.58125
1.57500
1.56875
1.56250
1.55625
1.55000
1.54375
1.53750
1.53125
1.52500
1.51875
1.51250
1.50625
1.50000
1.49375
1.48750
1.48125
1.47500
1.46875
1.46250
1.45625
1.45000
1.44375
1.43750
1.43125
1.42500
1.41875
1.41250
1.40625
1.40000
1.39375
1.38750
1.38125
1.37500
1.36875
1.36250
1.35625
1.35000
1.34375
1.33750
1.33125
1.32500
1.31875
1.31250
1.30625
1.30000
1.29375
1.28750
1.28125
1.27500
1.26875
1.26250
1.25625
1.25000
1.24375
1.23750
1.23125
1.22500
1.21875
Tolerance
+-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 -
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
HEX
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Voltage
1.21250
1.20625
1.20000
1.19375
1.18750
1.18125
1.17500
1.16875
1.16250
1.15625
1.15000
1.14375
1.13750
1.13125
1.12500
1.11875
1.11250
1.10625
1.10000
1.09375
1.08750
1.08125
1.07500
1.06875
1.06250
1.05625
1.05000
1.04375
1.03750
1.03125
1.02500
1.01875
1.01250
1.00625
1.00000
0.99375
0.98750
0.98125
0.97500
0.96875
0.96250
0.95625
0.95000
0.94375
0.93750
0.93125
0.92500
0.91875
0.91250
0.90625
0.90000
0.89375
0.88750
0.88125
0.87500
0.86875
0.86250
0.85625
0.85000
0.84375
0.83750
0.83125
0.82500
0.81875
Tolerance
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
+-15mV LL (0 - 110A)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
Monotonic DAC (6.25 mV)
HEX
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
Voltage
0.81250
0.80625
0.8
0.79375
0.7875
0.78125
0.775
0.76875
0.7625
0.75625
0.75
0.74375
0.7375
0.73125
0.725
0.71875
0.7125
0.70625
0.7
0.69375
0.6875
0.68125
0.675
0.66875
0.6625
0.65625
0.65
0.64375
0.6375
0.63125
0.625
0.61875
0.6125
0.60625
0.6
0.59375
0.5875
0.58125
0.575
0.56875
0.5625
0.55625
0.55
0.54375
0.5375
0.53125
0.525
0.51875
0.5125
0.50625
0.5
0.49375
0.4875
0.48125
0.475
0.46875
0.4625
0.45625
0.45
0.44375
0.4375
0.43125
0.425
0.41875
Tolerance
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Monotonic
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
HEX
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Voltage
0.4125
0.40625
0.40000
0.39375
0.38750
0.38125
0.37500
0.36875
0.36250
0.35625
0.35000
0.34375
0.33750
0.33125
0.32500
0.31875
0.31250
0.30625
0.30000
0.29375
0.28750
0.28125
0.27500
0.26875
0.26250
0.25625
0.25000
0.24375
0.23750
0.23125
0.22500
0.21875
0.21250
0.20625
0.20000
0.19375
0.18750
0.18125
0.17500
0.16875
0.16250
0.15625
0.15000
0.14375
0.13750
0.13125
0.12500
0.11875
0.11250
0.10625
0.10000
0.09375
0.08750
0.08125
0.07500
0.06875
0.06250
0.05625
0.05000
0.04375
0.03750
0.03125
OFF
OFF
Tolerance
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
Table 2.
www.fairchildsemi.com
12 of 21
VR_VCCee
VCORE
VR_VCCdie
VR_VCCse
VR_VSSse
VR_VSSdie
VR_VSSee
R5
0
R8
0
R7
R2A
Optional
R4
10
0
R3
Optional
0
10
R2
R6
Optional
R1
R1A
Optional
AGND
VSNS_B
VCORE
R11
FBRTN
0
D5
MMSD4148
SOD-123
NOTES :
1. Optional parts are not populated unless otherwise specified.
GND
MMSZ4678
D1
Q1
BCW33
R10
2.2
VR
C19
Optional
R13
1.21K
R12
R15
3K
D7
Optional
GREEN
C20
4.7uF
VIN
VTTA
Optional
470pF
C21
C22
PWRGD
Optional
R129
30.1K
R19
33pF
20
19
18
17
16
15
14
13
12
11
0
DIP20
S1
R20
COMP
C24
18nF
R21
680
C23
0.1uF
VRHOT
R137
Optional
1
2
3
4
5
6
7
8
9
10
SS
D16
RED
R128
3K
1K
R22
VIN
C26
18nF
DELAY
C25
0.1uF
VID0
R24
680
VID1
R25
680
VID2
R27
680
VID3
R28
680
R138
TTSNS
1nF
C27
VID4
R30
680
0
VID5
R32
680
R35
680
EN
R38
110K
ILIMIT
C145
18nF
VID7
RT4
Optional
THERMISTOR 5%
VID6
R34
680
10
9
8
7
6
5
4
3
2
1
TTSENSE
VRHOT
VCORE
DELAY
SS
COMP
FB
FBRTN
PWRGD
EN
1nF(X7R)
R39
182K
PSI#
C175
39
R20A
EN_B
R9
10K
VIN
VTT
VCC
37
38
C29
6.8nF
R40
200K
34
35
FAN50FC4
U10
33
CSCOMP
32
IOUT
31
VCC
ODB1
40
PSI#
ILIMIT
11
VID0
RT
12
VID1
RAMPADJ
13
VID2
LLSET
14
36
VID3
CSREF
15
VID4
CSSUM
16
VID5
CSCOMP
17
VID6
GND
18
VID7
IOUT
19
13 of 21
20
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
R153
Optional
R184
0
R154
0
ODB1
C33
1800pF
VOSADJ
ODB2
SW4
SW3
SW2
SW1
PWM4
PWM3
PWM2
PWM1
21
R44
C174
330nF
IMON
0
R43
C35
1500pF
CSREF
0
Optional
R169
RT2
53.6K
R46
0
R45
100K
THERMISTOR 5%
ODB1
0
R51
23
ODB2
R49
24
22
R48
25
PWM2
R47
R173
PWM1
26
27
28
29
30
C37
1uF/16V
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
CSREFA
ODB2
10
10
10
10
PWM3
VCC
R57
102K
R58
102K
Optional
R50
102K
R69
Optional
60.4K
R53
R55
102K
PWM4
Optional
R68
R59
Optional
R52
10
R56
VIN
SW4
SW3
SW2
SW1
PWM4
PWM3
PWM2
PWM1
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
Typical Applications
Figure 7. Typical Three-Phase Design, Controller
Note: Contact a Fairchild representative for the latest VR11 reference designs.
www.fairchildsemi.com
C1
C7
PWM4
ODB2
4.7uF/16V
PWM3
ODB2
4.7uF/16V
PWM1
ODB1
4.7uF/16V
C2
VIN
VIN
VIN
2
3
6
4
2
3
6
4
9
2
3
6
4
9
14 of 21
9
LDRV
FAN5109
PWM
SW
HDRV
BOOT
U5
SOD123
MMSD4148
OD
PGND
VCC
LDRV
FAN5109
PWM
SW
HDRV
BOOT
D6
U4
SOD123
MMSD4148
OD
PGND
VCC
LDRV
FAN5109
PWM
SW
HDRV
BOOT
D2
U2
SOD123
MMSD4148
OD
PGND
VCC
D3
5
1
7
8
5
1
7
8
5
1
7
8
R77
10K
0.1uF
C8
R73
10K
0.1uF
C3
R71
10K
0.1uF
C4
R18
2.2
R16
2.2
R17
2.2
SW4
SW3
SW1
R76
10K
R72
10K
R70
10K
Q12
FDD8796
SW4
Q2
FDD8796
SW3
Q3
FDD8796
SW1
Q11
FDD8780
Q4
FDD8780
Q5
FDD8780
Q13
FDD8796
Q6
FDD8796
Q7
FDD8796
R42
2.2
Q11B
FDD8780
C5
1000pf
2.2
R26
Q4B
FDD8780
R29
2.2
Q5B
FDD8780
C9
1000pf
C6
1000pf
0.6uF/27A
L4
C64
560uF
10
R33
C106
22uF/16V
+
0.6uH/27A
L3
C65
560uF
10
R36
C103
22uF/16V
+
0.6uF/27A
L1
C100
22uF/16V
TP_L4
TP_L3
TP_L1
+
+
10
R37
C107
22uF/16V
C66
560uF
C104
22uF/16V
C67
560uF
C101
22uF/16V
VCORE
CSREFA
CSREFA
VCORE
+
+
CSREFA
C108
0.1uF
C68
560uF
VCORE
C105
0.1uF
C69
560uF
C102
0.1uF
+
C70
560uF
PWM2
ODB2
C87
22uF/6.3V
C51
22uF/6.3V
C30
22uF/6.3V
C13
4.7uF
VIN
COM
COM
COM
COM
MOLEX_8B
J3
VCORE
C88
22uF/6.3V
C50
22uF/6.3V
C31
22uF/6.3V
1
2
3
4
2
3
6
4
9
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
1
1
GND
P4
VCORE
P3
C89
22uF/6.3V
C49
22uF/6.3V
C32
22uF/6.3V
+12V
+12V
+12V
+12V
LDRV
C90
22uF/6.3V
C48
22uF/6.3V
C34
22uF/6.3V
8
7
6
5
FAN5109
PWM
SW
HDRV
BOOT
U3
SOD123
MMSD4148
OD
PGND
VCC
D4
GND
C91
22uF/6.3V
C47
22uF/6.3V
C36
22uF/6.3V
+12V
5
1
7
8
Outside Socket
Optional
C92
22uF/6.3V
SW2
C93
22uF/6.3V
C43
22uF/6.3V
C40
22uF/6.3V
+
R54
2.2
C72
1200uF/16V
R75
10K
Inside Socket
C46
22uF/6.3V
C39
22uF/6.3V
0.1uF
C14
R74
10K
+
C94
22uF/6.3V
C44
22uF/6.3V
C41
22uF/6.3V
C73
1200uF/16V
C95
22uF/6.3V
C45
22uF/6.3V
C42
22uF/6.3V
C74
1200uF/16V
+
Q8
FDD8796
SW2
Q9
FDD8780
C96
22uF/6.3V
C81
22uF/6.3V
C58
22uF/6.3V
Q9B
FDD8780
VIN
C82
22uF/6.3V
C59
22uF/6.3V
Q10
FDD8796
C83
22uF/6.3V
C60
22uF/6.3V
R63
2.2
L2
C84
22uF/6.3V
+
300nH/30A
C61
22uF/6.3V
Bottom Side Socket
Optional
C15
1000pf
C16
22uF/16V
TP_L2
C85
22uF/6.3V
C62
22uF/6.3V
C75
560uF
10
R67
C17
22uF/16V
+
C86
22uF/6.3V
C63
22uF/6.3V
C76
560uF
C18
0.1uF
CSREFA
VCORE
C77
560uF
C56
22uF/6.3V
C52
22uF/6.3V
+
C57
22uF/6.3V
C53
22uF/6.3V
C38
22uF/6.3V
C54
22uF/6.3V
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
Typical Applications (Continued)
Figure 8. Typical Three-Phase Design, Drivers
Note: Contact a Fairchild representative for the latest VR11 reference designs.
www.fairchildsemi.com
Note: The values shown in this section are for reference
only. See the parametric tables for actual values.
The FAN50FC3 is a fixed-frequency PWM control with
multi-phase logic outputs for use in 2- and 3-phase
synchronous buck CPU power supplies. It has an
internal VID DAC designed to interface directly with 8-bit
VRD/VRM 11 and 7-bit VRD/VRM 10.x compatible
CPUs. Multiphase operation is required for the high
currents and low voltages of today’s microprocessors
that can require up to 150A of current.
The integrated features of the FAN50FC3 ensure a
stable, high-performance topology for:
ƒ
ƒ
ƒ
ƒ
the pin is tied to VIN, the pin voltage is above 3V and
that phase is disabled and put in a tri-state mode.
Otherwise, the internal 100µA current source pulls PWM
pin below the 3V threshold. After channel detection, the
current source is removed.
Shorting PWM3 to VCC configures the system into 2phase operation.
12V VIN
UVLO Threshold
0.85V
VTT
DELAY Threshold
DELAY
Balanced currents and thermals between phases
Tight load line regulation and accuracy
High current output by allowing up to 3-phase
designs
VIDs
Reduced output ripple due to multiphase operation
ƒ
2- to 3-phase operation allows optimizing designs
for cost/performance and support a wide range of
applications.
Vcore = VID
TD1
TD3
TD2
TD4
TD5
50µs
Invalid
Valid
Figure 9. Start-Up Sequence Timing
After detection time is complete, the PWM outputs not
sensed as “pulled HIGH” function as normal PWM
outputs. PWM outputs sensed as “pulled HIGH” are put
into a high-impedance state.
Good PC board layout noise immunity
Easily settable and adjustable design parameters
with simple component selection
The PWM signals are logic-level outputs intended for
driving external gate drivers, such as the FAN5109. Since
each phase is monitored independently; operation
approaching 100% duty cycle is possible. More than one
output can be on at the same time to allow phase overlap.
Start-Up Sequence
The start-up sequence is shown in Figure 9. Once the
EN and UVLO conditions are met, the DELAY pin goes
through one cycle (TD1), after which, the internal
oscillator starts. The first two clock cycles are used for
phase detection. The soft-start ramp is then enabled
(TD2), raising the output voltage up to the boot voltage
of 1.1V. The boot hold time (TD3) allows the processor
VID pins to settle to the programmed VID code. After
TD3 timing is finished, the output soft starts, either up or
down, to the final VID voltage (during TD4). TD5 is the
time between the output reaching the VID voltage and
the PWRGD being presented to the system.
Phase-Detection Sequence
During start-up, the number of operational phases and
their phase relationship is determined by the internal
circuitry that monitors the PWM outputs. Normally, the
FAN50FC3 operates as a 3-phase PWM controller. For
2-phase operation, connect the PWM3 pin to VCC.
The PWM logic, which is driven by the master oscillator,
directs the phase sequencer and channel detectors.
Channel detection is carried out during the first two clock
cycles after the chip is enabled. During the detection
period, PWM3 is connected to a 100µA sinking current
source and two internal voltage comparators check the
pin voltage of PWM3 versus a threshold of 3V typical. If
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
Vboot =1.1V
Vcore = Vboot
VCC (Core)
VReady
ƒ
ƒ
ƒ
1.0V
SS
High-speed response at the lowest possible
switching frequency and output decoupling
capacitors
Master Clock Frequency
The clock frequency is set with an external resistor
connected from the RT pin to ground. The frequency-toresistor relationship is shown in the graph in Figure 6.
To determine the frequency per phase, divide the clock
by the number of enabled phases.
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
Theory of Operation
Output Current Sensing
The FAN50FC3 provides a dedicated current-sense
amplifier (CSA) to monitor the output current for proper
voltage positioning and for current limit detection (see
Figure 1). It differentially senses the voltage drop across
the DCR of the inductors to give the total average current
being delivered to the load. This method is inherently
more accurate than peak current detection or sampling
the voltage across the low-side MOSFETs. The CSA
implementation can be configured for the objectives of the
system. It can use output inductor DCR sensing without a
thermistor for lowest cost or output inductor DCR sensing
with a thermistor for improved accuracy with tracking of
inductor temperature.
www.fairchildsemi.com
15 of 21
a few hundred ohms can make a noticeable increase in
current, so use small steps.
The gain of the CSA is set by connecting an external
feedback resistor between the CSA’s CSCOMP and
CSSUM pins. A capacitor, connected across the
resistor, is used to create a low-pass filter to remove
high frequency switching effects and create a RC pole to
cancel the zero created by the L/DCR of the inductor.
The end result is that the voltage between the CSCOMP
and CSREF pins is inversely proportional to the output
current (CSCOMP goes negative relative to CSREF as
current increases) and the CSA gain sets the ratio of the
CSA output voltage change as a function of output
current change. This difference in voltage is used by the
current limit comparator and by the droop amplifier to
create the output load line.
The FAN50FC3 uses differential sensing in conjunction
with a high-accuracy DAC and a low-offset error
amplifier to maintain a worst-case specification of
±7.7mV differential sensing accuracy over its specified
operating range.
The CSA is designed to have a low offset input voltage.
The sensing gain is determined by external resistors, so
it can be made extremely accurate.
Load Line Impedance Control
The FAN50FC3 has an internal “Droop Amp” that
effectively subtracts the voltage applied between the
CSCOMP and CSREF pins from the FB pin voltage of
the error amplifier, allowing the output voltage to be
varied independent of the DAC setting. A positive
voltage on CSCOMP (relative to CSREF) increases the
output voltage and a negative voltage decreases it.
Since the voltage between the CSA’s CSCOMP and
CSREF pins is inversely proportional to the output,
current causes the output voltage to decrease an
amount directly proportional to the increase in output
current creating a droop or load line. The ratio of output
voltage decrease to output current increase is the
effective Ro of the power supply and is set by the DC
gain of the CSA.
Current Control Mode & Thermal Balance
The FAN50FC3 has individual SW inputs for each phase.
They are used to measure the voltage drop across the
bottom FETs to determine the current in each phase. This
information is combined with an internal ramp to create a
current balancing feedback system. This gives good
current balance accuracy that takes into account, not only
the current, but also the thermal balance between the
bottom FETs in each phase.
External resistors RSW1 through RSW3 can be placed in
series with individual SW inputs to create an intentional
current imbalance, such as in cases where one phase
may have better cooling and can support higher
currents. It is best to have the ability to add these
resistors in the initial design, to ensure that placeholders
are provided in the layout. To increase the current in a
phase, increase RSW for that phase. Adding a resistor of
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
The amplitude of the internal ramp is set by a resistor
connected between the input voltage and the RAMPADJ
pin. This method also implements the voltage
feedforward function.
Output Voltage Differential Sensing
A high gain-bandwidth error amplifier is used for the
voltage control loop. The voltage on the FB pin is
compared to the DAC voltage to control the output
voltage. The FB voltage is also effectively offset by the
CSA output voltage for accurately positioning the output
voltage as a function of current. The output of the error
amplifier is the COMP pin, which is compared to the
internal PWM ramps to create the PWM pulse widths.
The negative input (FB) is tied to the output sense
location with a resistor RB and is used for sensing and
controlling the output voltage at this point. Additionally a
current source is connected internally to the FB pin,
which causes a fixed DC current to flow through RB. This
current creates a fixed voltage drop (offset voltage)
across RB. The offset voltage adds to the sensed output
voltage, which causes the error amplifier to regulate the
actual output voltage lower than the programmed VID
voltage by this amount. The main loop compensation is
incorporated into the feedback by an external network
connected between FB and COMP.
Delay Timer
The delay times for the start-up timing sequence are set
with a capacitor from the DELAY pin to ground, as
stated in the Start-Up Sequence section. In UVLO or
when EN is logic LOW, the DELAY pin is held at ground.
Once the UVLO and EN are asserted, a 15µA current
flows out of the DELAY pin to charge CDLY. A
comparator, with a threshold of 1.7V, monitors the
DELAY pin voltage. The delay time is therefore set by
the 15µA charging the delay capacitor from 0V to 1.7V.
This DELAY pin is used for multiple delay timings (TD1,
TD3, and TD5) during start-up. DELAY is also used for
timing the current-limit latch-off, as explained in the
Current Limit section.
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
To measure the differential voltage across the output
inductors, the positive input of the CSA (CSREF pin) is
connected, using equal value resistors, to the output
capacitor side of the inductors. The negative input of the
CSA (CSSUM pin) is connected, using equal value
resistors, to the MOSFET side of the inductors. The
CSA’s output (CSCOMP) is a voltage equal to the voltage
dropped across the inductors, times the gain of the CSA,
and is inversely proportional to the output current.
Soft-Start
The soft-start times for the output voltage are set with a
capacitor from the SS pin to ground. After TD1 and the
phase-detection cycle are complete, the SS time (TD2 in
Figure 9) starts. The SS pin is disconnected from GND
and the capacitor is charged up to the 1.1V boot voltage
by the SS amplifier, which has a limited output current of
15µA. The voltage at the FB pin follows the ramping
voltage on the SS pin, limiting the inrush current during
start-up. The soft-start time depends on the value of the
boot voltage and CSS.
www.fairchildsemi.com
16 of 21
The latch-off function can be reset by cycling the supply
voltage to the FAN50FC3 or by toggling the EN pin
LOW for a short time. To disable the short-circuit latchoff function, an external resistor can be placed in parallel
with CDLY to prevent the DELAY capacitor from charging
up to the 1.7V threshold. The addition of this resistor
causes a slight increase in the delay times.
During start-up, when the output voltage is below
200mV, a secondary current limit is active. This
secondary current limit clamps the internal COMP
voltage at the PWM comparators to 1.5V. Typical overcurrent latch-off waveforms are shown in Figure 11.
If either EN is taken LOW or VCC drops below UVLO,
DELAY and SS are reset to ground to be ready for
another soft-start cycle. Figure 10 shows typical start-up
waveforms for the FAN50FC3.
Vcore
VOD#
VDELAY
Vcore
VPHASE1
VVRREADY
VEN
Figure 11. Over-Current Latch-off Waveforms
VDELAY
FastvCore™ Operation
Figure 10. Start-up Waveforms
Current-Limit, Short-Circuit, and Latch-Off
Protections
The FAN50FC3 compares a programmable current-limit
set point to the voltage from the output of the current
sense amplifier. The current-limit level is set with the
resistor from the ILIMIT pin to ground. During operation,
the voltage on ILIMIT is 1.7V. The current through the
external resistor is internally scaled to give a current limit
threshold of 10mV/µA. If the voltage between CSREF
and CSCOMP rises above the current-limit threshold,
the internal current-limit amplifier controls the internal
COMP voltage to maintain the average output current at
the limit.
After TD5 has completed, an over-current (OC) event
starts a latch-off delay timer. The delay timer uses the
DELAY pin timing capacitor. During current limit, the
DELAY pin current is reduced to 3.75µA. When the
voltage on the delay pin reaches 1.7V, the controller
shuts down and latches off. The current limit latch-off
delay time is therefore set by the current of 3.75µA
charging the delay capacitor 1.7V. This delay is four
times longer than the delay time during the start-up
sequence. If there is a current limit during start-up, the
FAN50FC3 goes through TD1 to TD5 in current limit,
then starts the latch-off timer. Because the controller
continues to operate during the latch-off delay time, if
the OC is removed before the 1.7V threshold is reached,
the controller returns to normal operation and the
DELAY capacitor is reset to GND.
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
FastvCore™ improves the transient response for a load
step-up change. Normally a controller has to wait till the
next clock cycle if a load step-up happens during
between PWM signals. With FastvCore™, the controller
is able to immediately respond to the load step change,
so that the inductor current increases to the new load
current in a shorter period of time.
FastvCore™ is adjusted by connecting a resistor
(RSETOS) between pin 16 (VOSADJ) and AGND to set
the threshold where FastvCore™ is initiated.
RSETOS = (VOS+LLTOB) • RT • 10
where:
RT =
VOS =
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
Once the SS voltage is within 100mV of the boot
voltage, the boot voltage delay time (TD3) is started.
The end of the boot voltage delay time signals the
beginning of the second soft-start time (TD4). The SS
voltage changes from the boot voltage to the
programmed VID DAC voltage (either higher or lower)
using the SS amplifier with the limited output current of
15µA. The voltage of the FB pin follows the ramping
voltage of the SS pin, limiting the inrush current during
the transition from the boot voltage to the final DAC
voltage. The second soft-start time depends on the boot
voltage, the programmed VID DAC voltage, and CSS.
EQ. 1
the frequency set resistor
the target FastvCore™ detection threshold that
is the voltage difference between the output
voltage starting point and the voltage when the
FastvCore™ starts to respond to a load stepup change
LLTOB= the socket load line tolerance band
FastvCore™ design example:
If:
RT = 267kohm
VOS = 35mV
LLTOB = +/-19mV
Then:
RSETOS
= (VOS+LLTOB) • RT • 10
= (35mV+19mV) • 267kohm • 10
= 144.2kohm
www.fairchildsemi.com
17 of 21
When a VID input changes state, the FAN50FC3
detects the change and ignores the DAC inputs for a
minimum of 200ns. This time prevents a false code due
to logic skew while the eight VID inputs are changing.
Additionally, the first VID change initiates the PWRGD
and CROWBAR blanking functions for a minimum of
100µs to prevent a false PWRGD or CROWBAR event.
Each VID change resets the internal timer.
Power Good Monitoring
The power good comparator monitors the output voltage
via the CSREF pin. The PWRGD pin is an open-drain
output whose high level (when connected to a pull-up
resistor) indicates that the output voltage is within the
nominal limits specified based on the VID voltage
setting. PWRGD goes low if the output voltage is
outside of this specified range, if the VID DAC inputs are
in no CPU mode, or whenever the EN pin is pulled low.
PWRGD is blanked during a VID OTF event for a period
of ~200µs to prevent false signals during the time the
output is changing.
The PWRGD circuitry also incorporates an initial turn-on
delay time (TD5) based on the DELAY timer. Prior to the
SS voltage reaching the programmed VID DAC voltage,
100mV, the PWRGD pin is held low. Once the SS pin is
within 100mV of the programmed DAC voltage, the
capacitor on the DELAY pin begins to charge up. A
comparator monitors the DELAY voltage and enables
PWRGD when the voltage reaches 1.7V. The PWRGD
delay time is therefore set by a current of 15µA charging
a capacitor from 0V to 1.7V.
Output Enable and UVLO
For the FAN50FC3 to begin switching, the input supply
(VCC) to the controller must be higher than the UVLO
threshold and the EN pin must be higher than its 0.85V
threshold. This initiates a system start-up sequence. If
either UVLO or EN is less than their respective
thresholds, the FAN50FC3 is disabled; which holds the
PWM outputs low, discharges the DELAY and SS
capacitors, and forces PWRGD and OD# signals low.
In the application circuit, the OD# pin should be
connected to the OD# inputs of the FAN5009 or
FAN5109 drivers. Pulling OD# LOW disables the drivers
such that both DRVH and DRVL are driven low. This
turns off the bottom MOSFETs to prevent them from
discharging the output capacitors through the output
inductors. If the bottom MOSFETs were left on, the
output capacitors could ring with the output inductors
and produce a negative output voltage to the processor.
NTC Resistance versus Temperature
Normalized to 25C
1.0
0.8
Resistance (25C = 1)
The FAN50FC3 has the ability to dynamically change
the VID inputs while the controller is running. This allows
the output voltage to change while the supply is running
and supplying current to the load. This is commonly
referred to as VID on-the-fly (OTF). A VID OTF can
occur under light or heavy load conditions. The
processor signals the controller by changing the VID
inputs in multiple steps from the start code to the finish
code. This change can be positive or negative.
output over-voltage is due to a short in the high-side
MOSFET, this action current-limits the input supply,
protecting the microprocessor.
0.6
0.4
0.2
0.0
25
50
75
Temperature (C)
100
125
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
Dynamic VID
Figure 12. Typical NTC Resistance vs. Temperature
Output Crowbar
Applications and Component Selection
As part of the protection for the load and output
components of the supply, the PWM outputs are driven
low (turning on the low-side MOSFETs) when the output
voltage exceeds the upper crowbar threshold. This
crowbar action stops once the output voltage falls below
the release threshold of approximately 300mV.
Please consult Fairchild Application Note:
AN-6052 — Instructions for the Multi-Phase VR11
MathCad® Design Tool
Turning on the low-side MOSFETs pulls down the output
as the reverse current builds up in the inductors. If the
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
www.fairchildsemi.com
18 of 21
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
General Recommendations
For good results, a PCB with at least four layers is
recommended. This should allow the needed versatility
for control circuitry interconnections with optimal
placement, power planes for ground, input and output
power, and wide interconnection traces in the remainder
of the power delivery current paths. Keep in mind that
each square unit of one-ounce copper trace has a
resistance of ~0.53mΩ at room temperature.
Whenever high currents must be routed between PCB
layers, vias should be used liberally to create several
parallel current paths so that the resistance and
inductance introduced by these current paths is
minimized and the via current rating is not exceeded.
If critical signal lines (including the output voltage sense
lines of the FAN50FC3) must cross through power
circuitry, it is best if a signal ground plane can be
interposed between those signal lines and the traces of
the power circuitry. This serves as a shield to minimize
noise injection into the signals at the expense of making
signal ground a bit noisier.
An analog ground plane should be around and under the
FAN50FC3 as a reference for the components
associated with the controller. This plane should be tied
to the nearest output decoupling capacitor ground and
should not be tied to any other power circuitry to prevent
power currents from flowing in it.
The components around the FAN50FC3 should be
located close to the controller with short traces. The
most important traces to keep short and away from
other traces are the FB and CSSUM pins. The output
capacitors should be connected as close as possible to
the load (or connector); for example, a microprocessor
core that receives the power. If the load is distributed,
the capacitors should be distributed and generally be in
proportion to where the load tends to be more dynamic.
Avoid crossing any signal lines over the switching power
path loop described in the following section.
Power Circuitry Recommendations
The switching power path should be routed
to encompass the shortest possible length
radiated switching noise energy (i.e.,
conduction losses in the board. Failure to
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
precautions can result in EMI problems for the entire PC
system as well as noise-related operational problems in
the power converter control circuitry. The switching
power path is the loop formed by the current path
through the input capacitors and the power MOSFETs,
including all interconnecting PCB traces and planes.
Using short and wide interconnection traces is especially
critical in this path for two reasons: it minimizes the
inductance in the switching loop, which can cause high
energy ringing, and it accommodates the high-current
demand with minimal voltage loss.
Whenever a power dissipating component, for example,
a power MOSFET, is soldered to a PCB, the liberal use
of vias, both directly on the mounting pad and
immediately surrounding it, is recommended. Two
important reasons for this are improved current rating
through the vias and improved thermal performance
from vias extended to the opposite side of the PCB,
where a plane can more readily transfer the heat to the
air. Make a mirror image of any pad being used to
heatsink the MOSFETs on the opposite side of the PCB
to achieve the best thermal dissipation to the air around
the board. To further improve thermal performance, use
the largest possible pad area.
The output power path should also be routed to
encompass a short distance. The output power path is
formed by the current path through the inductor, the
output capacitors, and the load.
For best EMI containment, a solid power ground plane
should be used as one of the inner layers, extending
fully under all the power components.
Signal Circuitry Recommendations
The output voltage is sensed and regulated between the
FB pin and the FBRTN pin, which connect to the signal
ground at the load. To avoid differential mode noise
pickup in the sensed signal, the loop area should be
small. Thus, the FB and FBRTN traces should be routed
adjacent to each other on top of the power ground plane
back to the controller.
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
Layout and Component Placement
The feedback traces from the switch nodes should be
connected as close as possible to the inductor. The
CSREF signal should be connected to the output
voltage at the nearest inductor to the controller.
on the PCB
to minimize
EMI) and
take proper
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Dimensions are in millimeters (inches) unless otherwise noted.
FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
Physical Dimensions
Figure 13. 32-Pin, Molded Leadless Package (MLP), JEDEC MO-220, 5mm Square
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
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FAN50FC3 — 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
www.fairchildsemi.com
21 of 21