MC54/74F568 MC54/74F569 4-BIT BIDIRECTIONAL COUNTERS (WITH 3-STATE OUTPUTS) The MC54/ 74F568 and MC54/74F569 are fully synchronous, reversible counters with 3-state outputs. The F568 is a BCD decade counter; the F569 is a binary counter. They feature preset capability for programmable operation, carry lookahead for easy cascading, and a U/D input to control the direction of counting. For maximum flexibility there are both synchronous and master asynchronous reset inputs as well as both Clocked Carry (CC) and Terminal Count (TC) outputs. All state changes except Master Reset are initiated by the rising edge of the clock. A HIGH signal on the Output Enable (OE) input forces the output buffers into the high impedance state but does not prevent counting, resetting or parallel loading. 4-BIT BIDIRECTIONAL COUNTERS (WITH 3-STATE OUTPUTS) FAST SCHOTTKY TTL • 4-Bit Bidirectional Counting • • • • • • F568 Decade Counter F569 Binary Counter Synchronous Counting and Loading Lookahead Carry Capability for Easy Cascading Preset Capability for Programmable Operation 3-State Outputs for Bus Organized Systems Master Reset (MR) Overrides All Other Inputs Synchronous Reset (SR) Overrides Counting and Parallel Loading J SUFFIX CERAMIC CASE 732-03 20 1 N SUFFIX PLASTIC CASE 738-03 20 1 CONNECTION DIAGRAM VCC TC 20 19 CC OE 18 17 O0 16 O1 15 O2 14 DW SUFFIX SOIC CASE 751D-03 20 O3 CET 13 12 1 PE 11 ORDERING INFORMATION MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC 1 U/D 2 CP 3 P0 4 P1 5 P2 6 P3 8 7 CEP MR 9 10 SR GND LOGIC SYMBOL 11 3 4 5 6 PE P0 P1 P2 1 U/D 7 CEP 12 CET 2 CP 17 OE MR SR 8 FAST AND LS TTL DATA 4-220 9 P3 CC 18 TC 19 O0 O1 O2 O3 16 15 14 13 MC54/74F568 • MC54/74F569 Symbol Parameter Min Typ Max Unit 54, 74 4.5 5.0 5.5 V 54 – 55 25 125 74 0 25 70 VCC Supply Voltage TA Operating Ambient Temperature Range IOH IOL Output Current — High 54, 74 – 3.0 mA Output Current — Low 54, 74 24 mA °C FUNCTIONAL DESCRIPTION The F568 counts modulo-10 in the BCD (8421) sequence. From state 9 (HLLH) it will increment to 0 (LLLL) in the Up mode; in Down mode it will decrement from 0 to 9.The F569 counts in the modulo-16 binary sequence. From state 15 it will increment to state 0 in the Up mode; in the Down mode it will decrement from 0 to 15. The clock inputs of all flip-flops are driven in parallel through a clock buffer. All state changes (except due to Master Reset) occur synchronously with the LOWto-HIGH transition of the Clock Pulse (CP) input signal. The circuits have five fundamental modes of operation, in order of precedence: asynchronous reset, synchronous reset, parallel load, count and hold. Five control inputs — Master Reset (MR), Synchronous Reset (SR), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) — plus the Up/Down (U/D) input, determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces the flip-flop Q outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows the Q outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With MR, SR and PE HIGH, CEP and CET permit counting when both are LOW. Conversely, a HIGH signal on either CEP or CET inhibits counting. The F568 and F569 use edge-triggered flip-flops and changing the SR, PE, CEP , CET or U/D inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally HIGH and goes LOW providing CET is LOW, when the counter reaches zero in the Down mode, or reaches maximum (9 for the F568,15 for the F569) in the Up mode. TC will then remain LOW until a state change occurs, whether by counting or presetting, or until U/D or CET is changed. To implement synchronous multistage counters, the connections between the TC output and the CEP and CET inputs can provide either slow or fast carry propagation. Figure A shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure B are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle takes 10 (F568) or 16 (F569) clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock peri- od is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. For such applications, the Clocked Carry (CC) output is provided. The CC output is normally HIGH. When CEP, CET, and TC are LOW, the CC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again, as shown in the CC Truth Table. When the Output Enable (OE) is LOW, the parallel data outputs O0–O3 are active and follow the flip-flop Q outputs. A HIGH signal on OE forces O0–O3 to the High Z state but does not prevent counting, loading or resetting. LOGIC EQUATIONS: Count Enable = CEP⋅CET⋅PE Up (’F568): TC = Q0⋅Q1⋅Q2⋅Q3⋅(Up)⋅CET (’F569): TC = Q0⋅Q1⋅Q2⋅Q3⋅(Up)⋅CET Down (Both): TC = Q0⋅Q1⋅Q2⋅Q3⋅(Down)⋅CET CC TRUTH TABLE Inputs Output SR PE CEP CET TC* CP CC L X X X X H X L X X X H X X H X X L X X X H X L X X X X H L X X X X X H H H H H * = TC is generated internally L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care = Low Pulse FUNCTION TABLE Inputs Operating Mode MR SR PE CEP CET U/D CP L X X X X X X Asynchronous reset h l X X X X ↑ Synchronous reset h h l X X X ↑ Parallel load h h h l l h ↑ Count up (increment) h h h l l l ↑ Count down (decrement) h H H H X X X h H H X H X X Hold (do nothing) H = HIGH voltage level h = HIGH voltage level one setup prior to the Low-to-High Clock transition L = LOW voltage level l = LOW voltage level one setup prior to the Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition FAST AND LS TTL DATA 4-221 FAST AND LS TTL DATA 4-222 OE MR SR CP U/D CET CEP PE Q J DETAIL A CP SR DN UP T CP LD O0 ENF AT AF Q CD K CD Q P0 CP U/D UP T J CP LD K CD Q CD ENF AT AF P1 DETAIL A O1 DN CP ENF CD Q SR UP O2 Q DETAIL A CP O0 Q O1 DN CP ENF CD Q SR UP DETAIL A Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. O3 OE MR SR CP SR DN BF CC TC CET CEP PE P0 BF DETAIL A P3 LD T BT DETAIL A P2 O2 DETAIL A P2 MC54/74F569 LD T BT P1 MC54/74F568 LOGIC DIAGRAMS O3 DETAIL A P3 CP CC TC MC54/74F568 • MC54/74F569 MC54/74F568 • MC54/74F569 Figure A. Multistage Counter with Ripple Carry COUNT CET TC CP CP CET TC CET TC CET TC CET TO ALL STAGES Figure B. Multistage Counter with Lookahead Carry COUNT CET TC L CP CP CEP CET TC CEP CET TC CEP CET TC CEP CET TO ALL STAGES DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IOZH Typ Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs 0.8 V Guaranteed Input LOW Voltage for All Inputs – 1.2 V VCC = MIN, IIN = – 18 mA V IOH = – 3.0 mA VCC = 4.5 V Max 2.0 54, 74 2.4 3.3 74 2.7 3.3 V IOH = – 3.0 mA VCC = 4.75 V 0.5 V IOL = 24 mA VCC = MIN Output OFF Current — HIGH 50 µA VOUT = 2.7 V VCC = MAX IOZL Output OFF Current — LOW – 50 µA VOUT = 0.5 V VCC = MAX IIH Input HIGH Current IIL Input LOW Current PE, CET Others IOS Output Short Circuit Current (Note 2) ICC Power Supply Current (ALL Outputs OFF) 0.3 20 100 – 60 µA VIN = 2.7 V VIN = 7.0 V VCC = MAX –1.2 –0.6 mA VCC = MAX, VIN = 0.5 V –150 mA VOUT = 0 V 67 mA VCC = MAX VCC = MAX NOTES: 1. For conditions such as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-223 MC54/74F568 • MC54/74F569 STATE DIAGRAMS MC54/74F569 MC54/74F568 0 1 2 10 15 4 9 11 8 3 0 13 1 2 3 4 15 5 14 6 13 7 14 7 6 5 12 12 COUNT DOWN COUNT UP 11 10 9 8 COUNT DOWN COUNT UP AC CHARACTERISTICS Symbol Parameter 54 / 74F 54F 74F TA = + 25°C VCC = + 5.0 V CL = 50 pF TA = – 55 to + 125°C VCC = 5.0 V ± 10% CL = 50 pF TA = 0 to + 70°C VCC = 5.0 V ± 10% CL = 50 pF Min Max Min Max 60 Min Max fmax Maximum Clock Frequency 100 tPLH tPHL Propagation Delay CP to On (PE HIGH or LOW) 3.0 4.0 8.5 11.5 3.0 4.0 10.5 14 3.0 4.0 9.5 13 ns tPLH tPHL Propagation Delay CP to TC 5.5 4.0 15.5 11 5.5 4.0 18.5 13.5 5.5 4.0 17.5 12.5 ns tPLH tPHL Propagation Delay CET to TC 2.5 2.5 6.0 8.0 2.5 2.5 8.0 10 2.5 2.5 7.0 9.0 ns tPLH tPHL Propagation Delay U/D to TC (′F568) 3.5 4.0 11 16 3.5 4.0 13.5 19 3.5 4.0 12.5 18 ns tPLH tPHL Propagation Delay U/D to TC (′F569) 3.5 4.0 11 10.5 3.5 4.0 13.5 13 3.5 4.0 12.5 12 ns tPLH tPHL Propagation Delay CP to CC 2.5 2.0 7.0 6.0 2.5 2.0 9.0 8.0 2.5 2.0 8.0 7.0 ns tPLH tPHL Propagation Delay CEP, CET to CC 2.5 4.0 6.5 11 2.5 4.0 8.5 13.5 2.5 4.0 7.5 12.5 ns tPHL Propagation Delay MR to On 5.0 13 5.0 15.5 5.0 14.5 ns tPZH tPZL Output Enable Time OE to On 2.5 3.0 7.0 8.0 2.5 3.0 9.0 10 2.5 3.0 8.0 9.0 ns tPHZ tPLZ Output Disable Time OE to On 1.5 2.0 6.5 6.0 1.5 2.0 8.5 8.0 1.5 2.0 7.5 7.0 ns FAST AND LS TTL DATA 4-224 85 Unit MHz MC54/74F568 • MC54/74F569 AC OPERATING REQUIREMENTS Symbol Parameter 54 / 74F 54F 74F TA = + 25°C VCC = + 5.0 V TA = – 55°C to + 125°C VCC = 5.0 V ± 10% TA = 0°C to + 70°C VCC = 5.0 V ± 10% Min Max Min Max Min Max Unit ts(H) ts(L) Setup Time, HIGH or LOW Pn to CP 4.0 4.0 5.5 5.5 4.5 4.5 th(H) th(L) Hold Time, HIGH or LOW Pn to CP 3.0 3.0 3.5 3.5 3.5 3.5 ts(H) ts(L) Setup Time, HIGH or LOW CEP or CET to CP 5.0 5.0 7.0 7.0 6.0 6.0 th(H) th(L) Hold Time, HIGH or LOW CEP or CET to CP 0 0 0 0 0 0 ts(H) ts(L) Setup Time, HIGH or LOW PE to CP 8.0 8.0 10 10 9.0 9.0 th(H) th(L) Hold Time, HIGH or LOW PE to CP 0 0 0 0 0 0 ts(H) ts(L) Setup Time, HIGH or LOW U/D to CP (F568) 11 16.5 13.5 18.5 12.5 17.5 ns ts(H) ts(L) Setup Time, HIGH or LOW U/D to CP (F569) 11 7.0 13.5 10 12.5 8.0 ns th(H) th(L) Hold Time, HIGH or LOW U/D to CP 0 0 0 0 0 0 ns ts(H) ts(L) Setup Time, HIGH or LOW SR to CP 10 8.0 12 10.5 11 9.5 th(H) th(L) Hold Time, HIGH or LOW SR to CP 0 0 0 0 0 0 tw(H) tw(L) CP Pulse Width HIGH or LOW 4.0 6.0 6.0 8.0 4.5 6.5 ns tw(L) MR Pulse Width, LOW 4.5 6.0 5.0 ns trec MR Recovery Time 6.0 8.0 7.0 ns ns ns ns ns FAST AND LS TTL DATA 4-225