Revised July 1999 74F160A • 74F162A Synchronous Presettable BCD Decade Counter General Description Features The 74F160A and 74F162A are high-speed synchronous decade counters operating in the BCD (8421) sequence. They are synchronously presettable for applications in programmable dividers. There are two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The F160A has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. The F162A has a Synchronous Reset input that overrides counting and parallel loading and allows all outputs to be simultaneously reset on the rising edge of the clock. The F160A and F162A are high speed versions of the F160 and F162. ■ Synchronous counting and loading ■ High-speed synchronous expansion ■ Typical count rate of 120 MHz Ordering Code: Order Number Package Number Package Description 74F160ASC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F160ASJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F160APC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74F162ASC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F162APC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 74F160A © 1999 Fairchild Semiconductor Corporation 74F162A DS009485 www.fairchildsemi.com 74F160A • 74F162A Synchronous Presettable BCD Decade Counter April 1988 74F160A • 74F162A Logic Symbols 74F162A 74F160A IEEE/IEC 74F162A 74F160A Unit Loading/Fan Out U.L. Pin Names Description Input IIH/IIL HIGH/LOW Output IOH/IOL CEP Count Enable Parallel Input 1.0/1.0 20 µA/−0.6 mA CET Count Enable Trickle Input 1.0/2.0 20 µA/−1.2 mA CP Clock Pulse Input (Active Rising Edge) MR (74F160A) Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA 1.0/1.0 20 µA/−0.6 mA SR (74F162A) Synchronous Reset Input (Active LOW) 1.0/2.0 20 µA/−1.2 mA P0–P3 Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA PE Parallel Enable Input (Active LOW) 1.0/2.0 20 µA/−1.2 mA Q0–Q3 Flip-Flop Outputs 50/33.3 −1 mA/20 mA TC Terminal Count Output 50/33.3 −1 mA/20 mA www.fairchildsemi.com 2 The 74F160A and 74F162A count modulo-10 in the BCD (8421) sequence. From state 9 (HLLH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the (F160A) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset (F160A), synchronous reset (F162A), parallel load, count-up and hold. Five control inputs—Master Reset (MR, F160A), Synchronous Reset (SR, F162A), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)—determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR (F160A) or SR (F162A) HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The F160A and F162A use D-type edge-triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. Mode Select Table State Diagram *SR PE L X CET CEP X The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 9. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Please refer to the F568 data sheet. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. In the F160A and F162A decade counters, the TC output is fully decoded and can only be HIGH in state 9. If a decade counter is preset to an illegal state, or assumes an illegal state when power is applied, it will return to the normal sequence within two counts, as shown in the State Diagram. Logic Equations: Count Enable = CEP × CET × PE TC = Q0 × Q 1× Q 2 × Q3 × CET Action on the Rising Clock Edge ( X Reset (Clear) Load (Pn → Qn) H L X X H H H H Count (Increment) H H L X No Change (Hold) H H X L No Change (Hold) ) *For 74’F162A only H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74F160A • 74F162A Functional Description 74F160A • 74F162A Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output Note 2: Either voltage limit or current limit is sufficient to protect inputs. twice the rated IOL (mA) in LOW State (Max) ESD Last Passing Voltage (Min) 4000V DC Electrical Characteristics Symbol Parameter Min Typ Max 2.0 Units VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH Output HIGH 10% VCC 2.5 5% VCC 2.7 Voltage VOL Output LOW 10% VCC Voltage IIH Input HIGH Current IBVI Input HIGH Current Breakdown Test ICEX Output HIGH Leakage Current VID Input Leakage Test IOD Output Leakage Input LOW Current IOS Output Short-Circuit Current ICC Power Supply Current www.fairchildsemi.com −60 37 4 Conditions Recognized as a HIGH Signal Recognized as a LOW Signal Min IIN = −18 mA IOH = −1 mA V Min 0.5 V Min IOL = 20 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V (CP, CEP,Pn, MR (F160A)) 4.75 Circuit Current IIL VCC V IOH = −1 mA IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded −1.2 mA Max VIN = 0.5V (CET, SR (F162A), PE) −150 mA Max VOUT = 0V 55 mA Max VO = HIGH Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Count Frequency 90 120 Max Min Max Min tPLH Propagation Delay, Count 3.5 5.5 7.5 3.5 9.0 3.5 8.5 tPHL CP to Qn (PE Input HIGH) 3.5 7.5 10.0 3.5 11.5 3.5 11.0 75 Units Max 80 MHz tPLH Propagation Delay, Load 4.0 6.0 8.5 4.0 10.0 4.0 9.5 tPHL CP to Qn (PE Input LOW) 4.0 6.0 8.5 4.0 10.0 4.0 9.5 tPLH Propagation Delay 5.0 10.0 14.0 5.0 16.5 5.0 15.0 tPHL CP to TC 5.0 10.0 14.0 5.0 15.5 5.0 15.0 ns ns ns tPLH Propagation Delay 2.5 4.5 7.5 2.5 9.0 2.5 8.5 tPHL CET to TC 2.5 4.5 7.5 2.5 9.0 2.5 8.5 tPHL Propagation Delay 5.5 9.0 12.0 5.5 14.0 5.5 13.0 ns 4.5 8.0 10.5 4.5 12.5 4.5 11.5 ns ns MR to Qn (74F160A) tPHL Propagation Delay MR to TC (74F160A) AC Operating Requirements Symbol Parameter TA = +25°C TA = −55°C to +125°C VCC = +5.0V VCC = +5.0V Min Max Min Max TA = 0°C to +70°C VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 4.0 5.5 4.0 tS(L) Pn to CP (74F160A) 5.0 5.5 5.0 tS(H) Setup Time, HIGH or LOW 5.0 5.0 tS(L) Pn to CP (74F162A) 5.0 5.0 tH(H) Hold Time, HIGH or LOW 2.0 2.5 2.0 tH(L) Pn to CP 2.0 2.5 2.0 tS(H) Setup Time, HIGH or LOW 11.0 13.5 11.5 tS(L) PE or SR to CP 8.5 10.5 9.5 tH(H) Hold Time, HIGH or LOW 2.0 2.0 2.0 0 0 0 tH(L) PE or SR to CP tS(H) Setup Time, HIGH or LOW 11.0 13.0 11.5 tS(L) CEP or CET to CP 5.0 6.0 5.0 tH(H) Hold Time, HIGH or LOW 0 0 0 tH(L) CEP or CET to CP 0 0 0 tW(H) Clock Pulse Width (Load) 5.0 5.0 5.0 tW(L) HIGH or LOW 5.0 5.0 5.0 tW(H) Clock Pulse Width (Count) 4.0 5.0 4.0 tW(L) HIGH or LOW 6.0 8.0 7.0 tW(L) MR Pulse Width, LOW 5.0 5.0 5.0 6.0 6.0 6.0 Units Max ns ns ns ns ns ns (74F160A) tREC Recovery Time ns MR to CP (74F160A) 5 www.fairchildsemi.com 74F160A • 74F162A AC Electrical Characteristics 74F160A • 74F162A Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 6 74F160A • 74F162A Synchronous Presettable BCD Decade Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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