MOTOROLA Order this document by MCM36F8/D SEMICONDUCTOR TECHNICAL DATA Advance Information 1MB and 2MB Synchronous Fast Static RAM Module The MCM36F8 (1MB) is configured as 256K x 36 bits and the MCM36F9 (2MB) is configured as 512K x 36 bits. Both are packaged in a 144–pin dual–in–line memory module (DIMM). Each module uses Motorola’s 3.3 V 256K x 18 bit flow– through BurstRAMs. Address (A), data inputs (DQ, DP), and all control signals except output enable (G) are clock (K) controlled through positive–edge–triggered noninverting registers. Write cycles are internally self–timed and initiated by the rising edge of the clock (K) input. This feature provides increased timing flexibility for incoming signals. Synchronous byte write (BWx) and global byte write (WE) allows writes to either individual bytes or to both bytes. • • • • • • • MCM36F8 MCM36F9 144–LEAD DIMM CASE 1154–01 TOP VIEW Single 3.3 V + 10%, – 5% Power Supply Multiple Clock Pins for Reduced Loading All Inputs and Outputs are LVTTL Compatible Byte Write and Global Write Capability Fast SRAM Access Times: 10 ns Berg Connector, Part Number: 61178–31844 144–Pin DIMM Module 143 61 59 1 This document contains information on a new product. Specifications and information herein are subject to change without notice. 2/10/98 Motorola, Inc. 1998 MOTOROLA FAST SRAM MCM36F8•MCM36F9 1 MCM36F8 BLOCK DIAGRAM E0 G0 A0 – A17 ADSP BW0 BW1 K0 VDD WE VSS DQ0 – DQ7 DP0 DQ8 – DQ15 DP1 MCM36F8•MCM36F9 2 256K x 18 SE1 G A0 – A17 ADSC SBa SBb K SE2 ADV ADSP SGW SW LBO SE3 DQa0 – DQa7 DQa8 DQb0 – DQb7 DQb8 BW2 BW3 K1 256K x 18 SE1 G A0 – A17 ADSC SBa SBb K SE2 ADV ADSP SGW SW LBO SE3 DQa0 – DQa7 DQa8 DQb0 – DQb7 DQb8 PD1 = GND PD0 = GND DQ16 – DQ23 DP2 DQ24 – DQ31 DP3 MOTOROLA FAST SRAM MCM36F9 BLOCK DIAGRAM K0 E0 G0 A0 – A17 ADSP BW0 BW1 WE VDD VSS DQ0 – DQ7 DP0 DQ8 – DQ15 DP1 VDD VSS K2 E1 G1 MOTOROLA FAST SRAM 256K x 18 K SE1 G A0 – A17 ADSC SBa SBb SGW DQa0 – DQa7 DQa8 DQb0 – DQb7 DQb8 SE2 ADV ADSP SW LBO SE3 K1 BW2 BW3 256K x 18 K SE1 G A0 – A17 ADSC SBa SBb SGW DQa0 – DQa7 DQa8 DQb0 – DQb7 DQb8 SE2 ADV ADSP SW LBO SE3 PD1 = NC PD0 = GND DQ16 – DQ23 DP2 DQ24 – DQ31 DP3 256K x 18 256K x 18 A0 – A17 ADSC SBa SBb SGW DQb8 DQb0 – DQb7 DQa8 DQa0 – DQa7 SE2 ADV ADSP SW LBO SE3 K SE1 G A0 – A17 ADSC SBa SBb SGW DQb8 DQb0 – DQb7 DQa8 DQa0 – DQa7 SE2 ADV ADSP SW LBO SE3 K SE1 G K3 MCM36F8•MCM36F9 3 PIN ASSIGNMENT 144–LEAD DIMM TOP VIEW MCM36F8•MCM36F9 4 VSS A0 A2 A4 VDD NC NC VSS A6 A8 A10 NC VDD A12 A14 A16 VSS PD0 VSS BW0 E0 VSS K1 VSS DQ0 VDD DQ2 DQ4 DQ6 VSS 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 VSS A1 A3 A5 VDD NC NC VSS A7 A9 A11 NC VDD A13 A15 A17 VSS PD1 VSS BW1 G0 VSS K0 VSS DQ1 VDD DQ3 DQ5 DQ7 VSS VDD DQ8 DQ10 VSS DQ12 DQ14 DP0 NC NC VSS WE NC VDD NC NC NC VDD NC NC NC VSS BW2 E1 VDD DQ16 DQ18 NC NC NC VSS K3 VSS DQ20 VSS DQ22 DQ24 DQ26 DQ28 VDD DQ30 DP2 VSS 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 VDD DQ9 DQ11 VSS DQ13 DQ15 DP1 NC NC VSS ADSP NC VDD NC NC NC VDD NC NC NC VSS BW3 G1 VDD DQ17 DQ19 NC NC NC VSS K2 VSS DQ21 VSS DQ23 DQ25 DQ27 DQ29 VDD DQ31 DP3 VSS MOTOROLA FAST SRAM PIN DESCRIPTIONS Pin Locations Symbol Type Description 3, 4, 5, 6, 7, 8, 17, 18, 19, 20, 21, 22, 27, 28, 29, 30, 31, 32 A0 – A17 Input Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. 82 ADSP Input Synchronous Addresss Status Controller: Initiates read, write, or chip deselect cycle. 39, 40, 103, 104 BW0 – BW3 Input Synchronous Byte Write Inputs: x refers to the byte being written (byte a, b, c, d). WE overrides BWx. 73, 74, 141, 142 DP0 – DP3 (a) 49, 50, 53, 54, 55, 56, 57, 58, (b) 63, 64, 65, 66, 69, 70, 71, 72 (c) 109, 110, 111, 112, 125, 126, 129, 130 (d) 131, 132, 133, 134, 135, 136, 139, 140 DQ0 – DQ31 I/O 41, 105 E0, E1 Input Synchronous Chip Enable: Active low to enable chip. Negated high — deselects chip when ADSP is asserted. 42, 106 G0, G1 Input Asynchronous Output Enable Input. 46, 45, 122, 121 K0 – K3 Input Clock: This signal registers the address, data in, and all control signals except G. 35, 36 PD0, PD1 Output 81 WE Input 9, 10, 25, 26, 51, 52, 61, 62, 85, 86, 93, 94, 107, 108, 137, 138 VDD Supply Power Supply: 3.3 V + 10%, – 5%. 1, 2, 15, 16, 33, 34, 37, 38, 43, 44, 47, 48, 59, 60, 67, 68, 79, 80, 101, 102, 119, 120, 123, 124, 127, 128, 143, 144 VSS Supply Ground. 11, 12, 13, 14, 23, 24, 75, 76, 77, 78, 83, 84, 87, 88, 89, 90, 91, 92, 95, 96, 97, 98, 99, 100, 113, 114, 115, 116, 117, 118 NC — MOTOROLA FAST SRAM Synchronous Parity Data Inputs/Outputs. Synchronous Data Inputs/Outputs. Presence Detect Bits. Synchronous Global Write: This signal writes all bytes regardless of the status of the BWx signals. If only byte write signals SBx are being used, tie this pin high. No Connection: There is no connection to the chip. MCM36F8•MCM36F9 5 TRUTH TABLE (See Notes 1 through 4) Next Cycle Address Used Ex ADSP Gx DQx WRITE2, 4 Deselect None 1 0 X High–Z X Begin Read External 0 0 0 DQ Read Read Current X 1 1 High–Z Read Read Current X 1 0 DQ Read Begin Write External 0 0 X High–Z Write Write Current X 1 X High–Z Write NOTES: 1. X = don’t care, 1 = logic high, 0 = logic low. 2. Write is defined as either any BWx or WE low. 3. Gx is an asynchronous signal and is not sampled by the clock K. Gx drives the bus immediately (tGLQX) following Gx going low. 4. On write cycles that follow read cycles, Gx must be negated prior to the start of the write cycle to ensure proper write data setup times. Gx must also remain negated at the completion of the write cycle to ensure proper write data hold times. ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V) Symbol Value Unit VDD – 0.5 to + 4.6 V Voltage Relative to VSS Vin, Vout – 0.5 to VDD + 0.5 V Output Current (per I/O) Iout ± 20 mA Temperature Under Bias Tbias – 10 to + 85 °C Tstg – 55 to + 125 °C Rating Power Supply Voltage Storage Temperature NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. MCM36F8•MCM36F9 6 This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High–Z at power up. MOTOROLA FAST SRAM DC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V) Parameter Symbol Min Typ Max Unit Supply Voltage VDD 3.135 3.3 3.6 V Input High Voltage VIH 2.0 — VDD + 0.5 V Input Low Voltage VIL – 0.5* — 0.8 V Symbol Min Max Unit Input Leakage Current (0 V ≤ Vin ≤ VDD) Ilkg(I) — ± 1.0 µA Output Leakage Current (0 V ≤ Vin ≤ VDD) Ilkg(O) — ± 1.0 µA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V * VIL ≥ – 2.0 V for t ≤ tKHKH/2. DC CHARACTERISTICS Parameter POWER SUPPLY CURRENTS Parameter Symbol Min Max Unit Notes MCM36F8DG10 MCM36F9DG10 IDDA — 550 860 mA 1, 2, 3 CMOS Standby Supply Current (Deselected, MCM36F8DG10 Clock (K) Cycle Time ≥ tKHKH, All Inputs Toggling MCM36F9DG10 at CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V) ISB1 — 310 620 mA Clock Running Supply Current (Deselected, Clock (K) Cycle Time ≥ tKHKH, All Other Inputs Held to Static CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V) ISB2 — 190 380 mA AC Supply Current (Device Selected, All Outputs Open, Cycle Time ≥ tKHKH min) MCM36F8DG10 MCM36F9DG10 4 NOTES: 1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V). 2. All addresses transition simultaneously low (LSB) and then high (HSB). 3. Data states are all zero. 4. Device in deselected mode as defined by the Truth Table. MCM36F8 CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70°C, Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance BWx, K Other Inputs I/O Capacitance Symbol Typ Max Unit Cin — — 10 15 pF CI/O — 13 pF MCM36F9 CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70 °C, Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance I/O Capacitance MOTOROLA FAST SRAM K Addr, ADSP, WE Other Inputs Symbol Typ Max Unit Cin — — — 10 25 15 pF CI/O — 21 pF MCM36F8•MCM36F9 7 AC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . 1.25 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20 to 80%) Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 V Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted DATA RAM READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4) MCM36F8 – 10 MCM36F9 – 10 Parameter P Symbol S b l Min Max Unit U i Cycle Time tKHKH 15 — ns Clock Access Time tKHQV — 10 ns Output Enable to Output Valid tGLQV — 3.5 ns Clock High to Output Active tKHQX1 0 — ns 5 Clock High to Output Change tKHQX2 2 — ns 5 Output Enable to Output Active tGLQX 0 — ns 5 Output Disable to Q High–Z tGHQZ — 3.5 ns 5, 6 Clock High to Q High–Z tKHQZ 2 3.5 ns 5, 6 Clock High Pulse Width tKHKL 4.5 — ns Clock Low Pulse Width tKLKH 4.5 — ns Address ADSP Data In Write Chip Enable tAVKH tADKH tDVKH tWVKH tEVKH 2 — ns Address ADSP, ADSC, ADV Data In Write Chip Enable tKHAX tKHADX tKHDX tKHWX tKHEX 0.5 — ns Setup Times: Hold Times: Notes N NOTES: 1. Write is defined as either any BWx and SW low or WE is low. 2. Chip Enable is defined as E0 low, SE2 high, and SE3 low whenever ADSP or ADSC is asserted. 3. All read and write cycle timings are referenced from K0 or G0. 4. G0 is a don’t care after write cycle begins. To prevent bus contention, G0 should be negated prior to start of write cycle. 5. This parameter is sampled and not 100% tested. 6. Measured at ± 200 mV from steady state. TIMING LIMITS Z0 = 50 Ω OUTPUT 50 Ω VL = 1.25 V The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. Figure 1. AC Test Load MCM36F8•MCM36F9 8 MOTOROLA FAST SRAM OUTPUT LOAD OUTPUT BUFFER TEST POINT UNLOADED RISE AND FALL TIME MEASUREMENT 2.0 INPUT WAVEFORM 2.0 0.5 0.5 2.0 OUTPUT WAVEFORM 2.0 0.5 0.5 tr NOTES: 1. Input waveform has a slew rate of 1 V/ns. 2. Rise time is measured from 0.5 to 2.0 V unloaded. 3. Fall time is measured from 2.0 to 0.5 V unloaded. tf Figure 2. Unloaded Rise and Fall Time Characterization 3.6 PULL–UP I (mA) MIN I (mA) MAX – 0.5 – 50 – 150 0 – 50 – 150 1.4 – 50 – 150 1.65 – 46 – 130 2.0 – 35 – 101 3.135 0 – 25 3.135 2.8 VOLTAGE (V) VOLTAGE (V) 1.65 1.4 0 0 (a) Pull–Up – 80 – 40 CURRENT (mA) – 120 VDD PULL–DOWN I (mA) MIN I (mA) MAX – 0.5 0 0 0 0 0 0.4 10 20 0.8 20 40 1.25 31 63 1.6 40 80 2.8 40 80 3.2 40 80 3.4 40 80 3.6 46 120 1.6 VOLTAGE (V) VOLTAGE (V) 1.25 TEST POINT 0.3 0 0 40 CURRENT (mA) 80 (b) Pull–Down Figure 3. Output Buffer Characteristics MOTOROLA FAST SRAM MCM36F8•MCM36F9 9 READ/WRITE CYCLES t KHKH t KHKL t KLKH K A Ax B C D E F G ADSP Ex BW Gx t KHQV DQx Q(n) t KHQZ DESELECTED t GHQZ t KHQX2 Q(A) Q(B) Q(C) D(D) t GLQV D(E) t KHQX1 D(F) Q(G) t GLQX READ WRITES READ ORDERING INFORMATION (Order by Full Part Number) MCM 36F X XX XX Motorola Memory Prefix Speed (10 = 10 ns) Part Number Package (DG = Gold Pad DIMM) Memory Size (8 = 1MB, 9 = 2MB) Full Part Numbers — MCM36F8DG10 MCM36F8•MCM36F9 10 MCM36F9DG10 MOTOROLA FAST SRAM PACKAGE DIMENSIONS 144–LEAD DIMM CASE 1154–01 67.75 67.45 0.1 M A B C CL OF MODULE 63.6 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 4.8 24.5 25.55 25.25 3.8 A (DATUM C) 2X R 3 MIN COMPONENT AREA (FRONT) 20 6 PIN 1 B 2X (3.3) VIEW B 4.6 23.2 2X 0.1 M 0.15 FULL R PIN 144 2.7 2.4 0.25 0.1 L 0.65 0.55 A B C 0.5 L A 2X 4.1 3.9 0.1 4.2 M A ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ 4 MIN MAX 0.8 (DATUM C) 4.1 3.9 MIN C B A 2.5 1.6 1.4 2X 2 MIN (DATUM C) MAX VIEW A–A 2.1 COMPONENT AREA (BACK) 5 M C B A VIEW C ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ MIN 1.1 0.9 1.95 1.65 OPTIONAL HOLES PIN 2 FULL R 3.2 A 32.8 4.6 (3.7) PIN 143 32.8 23.2 2X MAX C VIEW B NOTES: 1. DIMENSIONING AND TOLERANCING CONFORM TO ASME Y14.5M, 1994. 2. ALL DIMENSIONS ARE IN mm. 3. CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING AND/OR METALIZATION. VIEW C Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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