NCV7356 Advance Information Single Wire CAN Transceiver The NCV7356 is a physical layer device for a single wire data link capable of operating with various Carrier Sense Multiple Access with Collision Resolution (CSMA/CR) protocols such as the Bosch Controller Area Network (CAN) version 2.0. This serial data link network is intended for use in applications where high data rate is not required and a lower data rate can achieve cost reductions in both the physical media components and in the microprocessor and/or dedicated logic devices which use the network. The network shall be able to operate in either the normal data rate mode or a high−speed data download mode for assembly line and service data transfer operations. The high−speed mode is only intended to be operational when the bus is attached to an off−board service node. This node shall provide temporary bus electrical loads which facilitate higher speed operation. Such temporary loads should be removed when not performing download operations. The bit rate for normal communications is typically 33 kbit/s, for high−speed transmissions like described above a typical bit rate of 83 kbit/s is recommended. The NCV7356 is designed in accordance to the Single Wire CAN Physical Layer Specification GMW3089 V2.3 and supports many additional features like undervoltage lockout, timeout for faulty blocked input signals, output blanking time in case of bus ringing and a very low sleep mode current. Features • • • • • • • • • • • • • • • • • • • Fully Compatible with J2411 Single Wire CAN Specification 60 A (max) Sleep Mode Current Operating Voltage Range 5.0 to 27 V Up to 100 kbps High−Speed Transmission Mode Up to 40 kbps Bus Speed Selective BUS Wake−Up Logic Inputs Compatible with 3.3 V and 5 V Supply Systems Control Pin for External Voltage Regulators Standby to Sleep Mode Timeout Low RFI Due to Output Wave Shaping Fully Integrated Receiver Filter Bus Terminals Proof Against Short−Circuits and Transients Loss of Ground Protection Protection Against Load Dump, Jump Start Thermal Overload and Short Circuit Protection ESD Protection of 4.0 kV on CAN Pin (2.0 kV on Any Other Pin) Undervoltage Lock Out Bus Dominant Timeout Feature NCV Prefix for Automotive and Other Applications Requiring Site and Change Control http://onsemi.com MARKING DIAGRAM 14 SO−14 D SUFFIX CASE 751A 14 1 NCV7356 AWLYWW 1 A WL Y WW = Assembly Location = Wafer Lot = Year = Work Week PIN CONNECTIONS GND 1 14 GND TxD 2 13 NC MODE0 3 12 CANH MODE1 4 11 LOAD RxD 10 VBAT 5 NC 6 9 INH GND 7 8 GND (Top View) ORDERING INFORMATION Package Shipping† NCV7356D SOIC−14 55 Units / Rail NCV7356DR2 SOIC−14 1000 Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. This document contains information on a new product. Specifications and information herein are subject to change without notice. Semiconductor Components Industries, LLC, 2004 September, 2004 − Rev. P2 1 Publication Order Number: NCV7356/D NCV7356 VBAT INH NCV7356 5 V Supply and References Biasing and VBAT Monitor Reverse Current Protection RC−Osc Wave Shaping CAN Driver TxD CANH Time Out Feedback Loop Input Filter MODE0 LOAD MODE CONTROL MODE1 Receive Comparator Loss of Ground Detection RxD RxD Blanking Time Filter Reverse Current Protection GND Figure 1. Block Diagram http://onsemi.com 2 NCV7356 PACKAGE PIN DESCRIPTION Pin Symbol Description 1, 7, 8, 14 GND Ground 2 TXD Transmit data from microprocessor to CAN. 3 MODE0 Operating mode select input 0. 4 MODE1 Operating mode select input 1. 5 RXD 6, 13 NC No Connection 9 INH Control pin for external voltage regulator (high voltage high side switch) 10 VBAT Battery input voltage. 11 LOAD Resistor load (loss of ground detection low side switch). 12 CANH Single wire CAN bus pin. Receive data from CAN to microprocessor. Sleep Mode Functional Description Transceiver is in low power state, waiting for wake−up via high voltage signal or by mode pins change to any state other than 0,0. In this state, the CANH pin is not in the dominant state regardless of the state of the TxD pin. TxD Input Pin TxD Polarity • TxD = logic 1 (or floating) on this pin produces an undriven or recessive bus state (low bus voltage) • TxD = logic 0 on this pin produces either a bus normal or a bus high voltage dominant state depending on the transceiver mode state (high bus voltage) If the TxD pin is driven to a logic low state while the sleep mode (Mode 0 = 0 and Mode 1 = 0) is activated, the transceiver can not drive the CANH pin to the dominant state. The transceiver provides an internal pull up current on the TxD pin which will cause the transmitter to default to the bus recessive state when TxD is not driven. TxD input signals are standard CMOS logic levels. High−Speed Mode This mode allows high−speed download with bitrates up to 100 Kbit/s. The output waveshaping circuit is disabled in this mode. Bus transmitter drive circuits for those nodes which are required to communicate in high−speed mode are able to drive reduced bus resistance in this mode. High Voltage Wake−Up Mode This bus includes a selective node awake capability, which allows normal communication to take place among some nodes while leaving the other nodes in an undisturbed sleep state. This is accomplished by controlling the signal voltages such that all nodes must wake−up when they receive a higher voltage message signal waveform. The communication system communicates to the nodes information as to which nodes are to stay operational (awake) and which nodes are to put themselves into a non communicating low power “sleep” state. Communication at the lower, normal voltage levels shall not disturb the sleeping nodes. Timeout Feature In case of a faulty blocked dominant TxD input signal, the CANH output is switched off automatically after the specified TxD timeout reaction time to prevent a dominant bus. The transmission is continued by next TxD L to H transition without delay. MODE0 and MODE1 Pins Normal Mode The transceiver provides a weak internal pull down current on each of these pins which causes the transceiver to default to sleep mode when they are not driven. The mode input signals are standard CMOS logic level for 3.3V and 5V supply voltages. MODE0 MODE1 L L Sleep Mode H L High−Speed Mode L H High Voltage Wake−Up H H Normal Mode Transmission bit rate in normal communication is 33 Kbits/s. In normal transmission mode the NCV7356 supports controlled waveform rise and overshoot times. Waveform trailing edge control is required to assure that high frequency components are minimized at the beginning of the downward voltage slope. The remaining fall time occurs after the bus is inactive with drivers off and is determined by the RC time constant of the total bus load. Mode http://onsemi.com 3 NCV7356 RxD Output Pin CAN BUS Input/Output Pin Logic data as sensed on the single wire CAN bus. Wave Shaping in Normal and High Voltage Wake−Up Mode RxD Polarity • RxD = logic 1 on this pin indicates a bus recessive • Wave shaping is incorporated into the transmitter to minimize EMI radiated emissions. An important contributor to emissions is the rise and fall times during output transitions at the “corners” of the voltage waveform. The resultant waveform is one half of a sin wave of frequency 50−65 kHz at the rising waveform edge and one quarter of this sin wave at falling or trailing edge. state (low bus voltage) RxD = logic 0 on this pin indicates a bus normal or high voltage bus dominant state RxD in Sleep Mode RxD does not pass signals to the microprocessor while in sleep mode until a valid wake−up bus voltage level is received or the MODE0 and MODE 1 pins are not 0, 0 respectively. When the valid wake−up bus voltage signal awakens the transceiver, the RxD pin signals an interrupt (logic 0). If there is no mode change within 250 ms (typ), the transceiver re−enters the sleep mode. When not in sleep mode all valid bus signals will be sent out on the RxD pin. RxD will be placed in the undriven or off state when in sleep mode. Wave Shaping in High−Speed Mode Wave shaping control of the rising and falling waveform edges are disabled during high−speed mode. EMI emissions requirements are waived during this mode. The waveform rise time in this mode is less than 1.0 s. Short Circuits If the CAN BUS pin is shorted to ground for any duration of time, the current is limited as specified in the Electrical Characteristics Table until an overtemperature shutdown circuit disables the output high side drive source transistor preventing damage to the IC. RxD Typical Load Resistance: 2.7 k Capacitance: < 25 pF Loss of Ground In case of a valid loss of ground condition, the LOAD pin is switched into high impedance state. The CANH transmission is continued until the undervoltage lock out voltage threshold is detected. Bus LOAD Pin Resistor ground connection with internal open−on−loss− of−ground protection When the ECU experiences a loss of ground condition, this pin is switched to a high impedance state. The ground connection through this pin is not interrupted in any transceiver operating mode including the sleep mode. The ground connection only is interrupted when there is a valid loss of ground condition. This pin provides the bus load resistor with a path to ground which contributes less than 0.1 V to the bus offset voltage when sinking the maximum current through one load resistor. The transceiver’s maximum bus leakage current contribution to Vol from the LOAD pin when in a loss of ground state is 50 A over all operating temperatures and 3.5 < VBAT < 27 V. Loss of Battery In case of loss of battery (VBAT = 0 or open) the transceiver does not disturb bus communication. The maximum reverse current into the power supply system (VBAT) doesn’t exceed 500 A. INH Pin The INH pin is a high−voltage highside switch used to control the ECU’s regulated microcontroller power supply. After power−on, the transceiver automatically enters an intermediate standby mode, the INH output will go high (up to VBAT) turning on the external voltage regulator. The external regulator provides power to the ECU. If there is no mode change within 250 ms (typ), the transceiver re−enters the sleep mode and the INH output goes to logic 0 (floating). When the transceiver has detected a valid wake−up condition (bus HVWU traffic which exceeds the wake−up filter time delay) the INH output will become high (up to VBAT) again and the same procedure starts as described after power−on. In case of a mode change into any active mode, the sleep timer is stopped and INH stays high (up to VBAT). If the transceiver enters the sleep mode, INH goes to logic 0 (floating) after 250 ms (typ) when no wake−up signal is present VBAT Input Pin (Vehicle Battery Voltage) The transceiver is fully operational as described in the Electrical Characteristics Table over the range 6.0 V < VBAT < 18 V as measured between the GND pin and the VBAT pin. For 5.0 V < VBat < 6.0 V the bus operates in normal mode with reduced dominant output voltage and reduced receiver input voltage. High voltage wakeup is not possible (dominant output voltage is the same as in normal or high−speed mode). The transceiver operates in normal mode when 18 V > VBat > 27 V at 85°C for one minute. For 0 < VBAT < 4.0 V, the bus is passive (not driven dominant) and RxD is undriven (high), regardless of the state of the TxD pin (undervoltage lockout). http://onsemi.com 4 NCV7356 Electrical Specification All voltages are referenced to ground (GND). Positive currents flow into the IC. The maximum ratings given in the table below are limiting values that do not lead to a permanent damage of the device but exceeding any of these limits may do so. Long term exposure to limiting values may affect the reliability of the device. MAXIMUM RATINGS Rating Supply Voltage, Normal Operation Short−Term Supply Voltage, Transient Symbol Condition Min Max Unit VBAT − −0.3 18 V Load Dump; t < 500 ms − 40 V (peak) Jump Start; t < 1.0 min − 27 V VBAT.LD Transient Supply Voltage VBAT.TR1 ISO 7637/1 Pulse 1 (Note 1) −50 − V Transient Supply Voltage VBAT.TR2 ISO 7637/1 Pulses 2 (Note 1) − 100 V Transient Supply Voltage VBAT.TR3 ISO 7637/1 Pulses 3A, 3B −200 200 V VBAT < 27 V −20 VBAT = 0 V −40 CANH Voltage VCANH V 40 Transient Bus Voltage VCANHTR1 ISO 7637/1 Pulse 1 (Note 2) −50 − V Transient Bus Voltage VCANHTR2 ISO 7637/1 Pulses 2 (Note 2) − 100 V Transient Bus Voltage VCANHTR3 ISO 7637/1 Pulses 3A, 3B (Note 2) −200 200 V Via RT > 2.0 k −40 40 V DC Voltage on Pin LOAD DC Voltage on Pins TxD, MODE1, MODE0, RxD VLOAD VDC − −0.3 7.0 V VESDBUS Human Body Model Eq. to Discharge 100 pF with 1.5 k −4000 4000 V ESD Capability of Any Other Pins VESD Human Body Model Eq. to Discharge 100 pF with 1.5 k −2000 2000 V Maximum Latch−Up Free Current at Any Pin ILATCH − −500 500 mA − >400 (Note 3) mW ESD Capability of CANH Maximum Power Dissipation Ptot At TA = 125°C Thermal Impedance JA In Free Air − <70 °C/W Storage Temperature TSTG − −55 150 °C Junction Temperature TJ − −40 150 °C Lead Temperature Soldering Reflow: (SMD styles only) Tsld − 240 peak °C 60 second maximum above 183°C −5°C/+0°C allowable conditions 1. ISO 7637 test pulses are applied to VBAT via a reverse polarity diode and >1.0 F blocking capacitor. 2. ISO 7637 test pulses are applied to CANH via a coupling capacitance of 1.0 nF. 3. The application board shall be realized with a ground copper foil area > 150 mm2. http://onsemi.com 5 NCV7356 ELECTRICAL CHARACTERISTICS (VBAT = 5.0 to 27 V, TA = −40 to +125°C, unless otherwise specified.) Characteristic Symbol Condition Min Typ Max Unit VBATuv − 4.0 − 4.8 V VBAT = 18 V, TxD Open − 5.0 6.0 mA GENERAL Undervoltage Lock Out Supply Current, Recessive, All Active Modes IBATN Normal Mode Supply Current, Dominant IBATN (Note 4) VBAT = 27 V, MODE0 = MODE1 = H, TxD = L, Rload = 200 − 30 35 mA High−Speed Mode Supply Current, Dominant IBATN (Note 4) VBAT = 16 V, MODE0 = H, MODE1 = L, TxD = L, Rload = 75 − 70 75 mA Wake−Up Mode Supply Current, Dominant IBATW (Note 4) VBAT = 27 V, MODE0 = L, MODE1 = H, TxD = L, Rload = 200 − 60 75 mA VBAT = 18 V, TxD, RxD, MODE0, MODE1 Open − 30 60 A Sleep Mode Supply Current IBATS Thermal Shutdown (Note 4) TSD − 155 − 180 °C Thermal Recovery (Note 4) TREC − 126 − 150 °C CANH Bus Output Voltage Voh RL > 200 , Normal, 6.0 V < VBAT < 27 V 4.4 − 5.1 V Bus Output Voltage Low Battery Voh RL > 200 , Normal, High−Speed 5.0 V < VBAT < 6.0 V 3.4 − 5.1 V Bus Output Voltage High Battery Voh RL > 75 , High−Speed 8.0 V < VBAT < 16 V 4.2 − 5.1 V Fixed Wake−Up Output High Voltage VohWuFix Wake−Up Mode, RL > 200 , 11.2 V < VBAT < 27 V 9.9 − 12.5 V Offset Wake−Up Output High Voltage VohWuOffset Wake−Up Mode, RL > 200 , 5.5 V < VBAT < 11.2 V VBAT –1.5 − VBAT V −0.20 − 0.20 V VCANH = 0 V, VBAT = 27 V, TxD = 0 V 50 − 350 mA Recessive State Output Voltage Vol Recessive State or Sleep Mode, Rload = 6.5 k Bus Short Circuit Current −ICAN_SHORT Bus Leakage Current During Loss of Ground ILKN_CAN (Note 5) Loss of Ground, VCANH = 0 V −50 − 10 A Bus Leakage Current, Bus Positive ILKP_CAN TxD High −10 − 10 A Vih Normal, High−Speed Mode, 6.0 VBAT 27 V 2.0 2.1 2.2 V Vihlb Normal, 5.0 V < VBAT < 6.0 V 1.6 1.7 2.2 V Sleep Mode, VBAT > 11.2 V 6.6 − 7.9 V VBAT −4.3 − VBAT −3.25 V ILOAD = 5.0 mA − − 0.5 V − − 1.0 V RLOAD −10% − RLOAD +35% Bus Input Threshold Bus Input Threshold Low Battery Fixed Wake−Up Input High Voltage Threshold VihWuFix (Note 4) Offset Wake−Up Input High Voltage Threshold VihWuOffset (Note 4) Sleep Mode LOAD Voltage on Switched Ground Pin VLOAD Voltage on Switched Ground Pin VLOAD_LOB ILOAD = 7.0 mA, VBAT = 0 V Load Resistance During Loss of Battery RLOAD_LOB VBAT = 0 4. Thresholds not tested in production, guaranteed by design. 5. Leakage current in case of loss of ground is the summary of both currents ILKN_CAN and ILKN_LOAD. http://onsemi.com 6 NCV7356 ELECTRICAL CHARACTERISTICS (continued) (VBAT = 5.0 to 27 V, TA = −40 to +125°C, unless otherwise specified.) Characteristic Symbol Condition Min Typ Max Unit TXD, MODE0, MODE1 High Level Input Voltage Vih 5.0 < VBAT < 27 V 2.0 − − V Low Level Input Voltage Vil 5.0 < VBAT < 27 V − − 0.8 V TxD = L, MODE0 and 1 = H 5.0 < VBAT < 27 V 20 − 50 A 20 − 40 k TxD Pull Up Current MODE0 and 1 Pull Down Resistor −IIL_TXD RMODE_pd RXD Low Level Output Voltage Vol_rxd IRxD = 2.0 mA − − 0.4 V High Level Output Leakage Iih_rxd VRxD = 5.0 V −10 − 10 A Irxd VRxD = 5.0 V − − 70 mA VBAT −0.8 VBAT −0.5 − V −5.0 − 5.0 A RxD Output Current INH High Level Output Voltage Leakage Current Voh_INH IINH_lk IINH = −180 A MODE0 = MODE1 = L, INH = 0 V http://onsemi.com 7 NCV7356 TIMING MEASUREMENT LOAD CONDITIONS Normal and High Voltage Wake−Up Mode min load / min tau 3.3 kohm / 540 pF min load / max tau 3.3 kohm / 1.2 nF max load / min tau 200 ohm / 5.0 nF max load / max tau 200 ohm / 20 nF High−Speed Mode Additional 140 ohm tool resistance to ground in parallel Additional 120 ohm tool resistance to ground in parallel ELECTRICAL CHARACTERISTICS (5.0 V ≤ VBAT ≤ 27 V, −40°C ≤ TA ≤ 125°C, unless otherwise specified.) AC CHARACTERISTICS (See Figures 2, 3, and 4) Characteristic Symbol Condition Min Typ Max Unit tTr min and max loads per Page 9 2.0 − 6.3 s tTWUr min and max loads per Page 9 2.0 − 18 s tTf min and max loads per Page 9 1.8 − 10 s tTWU1f min and max loads per Page 9 3.0 − 13.7 s Transmit Delay in High−Speed Mode, Bus Rising Edge (Note 9) tTHSr min and max loads per Page 9 0.1 − 1.5 s Transmit Delay in High−Speed Mode, Bus Falling Edge (Note 10) tTHSf min and max loads per Page 9 0.1 − 3.0 s tDR CANH High to Low Transition 0.3 − 1.0 s Transmit Delay in Normal and Wake−Up Mode, Bus Rising Edge (Note 6) Transmit Delay in Wake−Up Mode to VihWU, Bus Rising Edge (Note 7) Transmit Delay in Normal Mode, Bus Falling Edge (Note 8) Transmit Delay in Wake−Up Mode, Bus Falling Edge (Note 8) Receive Delay, All Active Modes (Note 11) tRD CANH Low to High Transition 0.3 − 1.0 s Input Minimum Pulse Length, All Active Modes (Note 11) tmpDR tmpRD CANH High to Low Transition CANH Low to High Transition 0.15 0.15 − − 1.0 1.0 s Wake−Up Filter Time Delay tWUF See Figure 3 10 − 70 s Receive Blanking Time After TxD L−H Transition trb See Figure 4 0.5 − 6.0 s TxD Timeout Reaction Time ttout Normal and High−Speed Mode − 20 − ms TxD Timeout Reaction Time ttoutwu Receive Delay, All Active Modes (Note 11) Wake−Up Mode − 30 − ms Delay from Normal to High−Speed and High Voltage Wake−Up Mode tdnhs − − − 30 s Delay from High−Speed and High Voltage Wake−Up to Normal Mode tdhsn − − − 30 s tdsby VBAT = 6.0 V to 27 V − − 500 s Delay from Sleep to Normal Mode tdsnwu VBAT = 6.0 V to 27 V − − 50 s Delay from Standby to Sleep Mode tdsleep VBAT = 6.0 V to 27 V 100 250 1000 ms Delay from Normal to Standby Mode 6. The maximum signal delay time for a bus rising edge is measured from Vcmos_il on the TxD input pin to the VihMax + Vgoff max level on CANH at maximum network time constant, minimum signal delay time for a bus rising edge is measured from Vcmos_ih on the TxD input pin to 1 V on CANH at minimum network time constant. These definitions are valid in both normal and High Voltage Wake−Up (HVWU) mode. 7. The maximum signal delay time for a bus rising edge in HVWU mode is measured from Vcmos_il on the TxD input pin to the VihWuMax + Vgoff max level on CANH at maximum network time constant, minimum signal delay time for a bus rising edge is measured from Vcmos_ih on the TxD input pin to 1 V on CANH at minimum network time constant. 8. Maximum signal delay time for a bus falling edge is measured from Vcmos_ih on the TxD input pin to 1 V on CANH at maximum network time constant, minimum signal delay time for a bus falling edge is measured from Vcmos_ih on the TxD input pin to the VihMax + Vgoff max level on CANH. These definitions are valid in both normal and HVWU mode. 9. The signal delay time in high−speed mode for a bus rising edge is measured from Vcmos_il on the TxD input pin to the VihMax + Vgoff max level on CANH at maximum high−speed network time constant. 10. The signal delay time in high−speed mode for a bus falling edge is measured from Vcmos_ih on the TxD input pin to 1 V on CANH at maximum high−speed network time constant. 11. Receive delay time is measured from the rising / falling edge crossing of the nominal Vih value on CANH to the falling (Vcmos_il_max) / rising (Vcmos_ih_min) edge of RxD. This parameter is tested by applying a square wave signal to CANH. The minimum slew rate for the bus rising and falling edges is 50 V/s. The low level on bus is always 0V. For normal mode and high−speed mode testing the high level on bus is 4 V. For HVWU mode testing the high level on bus is VBAT − 2 V. http://onsemi.com 8 NCV7356 BUS LOADING REQUIREMENTS Characteristic Symbol Min Typ Max Unit − 2 − 32 − Bus Length − − 60 m Node Series Inductor Resistance (If required) Rind − − 6.0 Ground Offset Voltage Vgoff − 0.1 x VBAT 1.5 V Ground Offset Voltage Vgofflowbat − − 0.7 V Device Capacitance (Unit Load) Cul 135 150 300 pF Network Total Capacitance Ctl 396 − 19000 pF Device Resistance (Unit Load) Rul 6435 6490 6565 Device Resistance (Min Load) Rmin 2000 − − Rtl 200 − 3332 Network Time Constant (Note 12) 1.0 − 4.0 s Network Time Constant in High−Speed Mode − − 1.5 s Rload 75 − 135 Number of System Nodes Network Distance Between Any Two ECU Nodes Network Total Resistance High−Speed Mode Network Resistance to GND 12. The network time constant incorporates the bus wiring capacitance. The minimum value is selected to limit radiated emission. The maximum value is selected to ensure proper communication modes. Not all combinations of R and C are possible. TIMING DIAGRAMS VTxD 50% t tT VCANH Vihmax + Vgoffmax 1V t tR tF tD tDR VRxD 50% t Figure 2. Input/Output Timing http://onsemi.com 9 NCV7356 TIMING DIAGRAMS VCANH Vih + Vgoff t tWU tWU tWUF VRxD wake−up interrupt tWU < tWUF t Figure 3. Wake−Up Filter Time Delay VTxD 50% t VCANH Vih t VRxD 50% t tRB Figure 4. Receive Blanking Time http://onsemi.com 10 NCV7356 HVWU Mode MODE0 MODE1 INH low high VBAT MODE0/1 => High High−Speed Mode MODE0 MODE1 INH high low VBAT MODE0&1 => Low VBATon Normal Mode MODE0 MODE1 INH high high VBAT MODE0/1 => High (If VCC_ECU on) VBAT standby MODE0/1 INH after 250 ms −> no mode change −> no valid wake−up low VS RxD CAN high/low(1) float wake−up request from Bus Sleep Mode (1) MODE0/1 INH/CAN low floating low after HVWU, high after VBAT on & VCCECU present Figure 5. State Diagram http://onsemi.com 11 NCV7356 MRA4004T3 * VBAT_ECU Voltage Regulator INH VBAT +5 V ECU Connector to Single Wire CAN Bus 100 pF** VBAT 2.7 k 1 k** 9 10 47 H 5 RxD CAN Controller VBAT 12 CANH NCV7356 MODE0 MODE1 TxD 6.49 k 3 47 pF** 4 11 LOAD 2 ESD Protection − MMBZ27VCLT1 1, 7, 8, 14 GND Copper Foil Heatsink >150 mm2 *Recommended capacitance at VBAT_ECU > 1.0 F (immunity to ISO7637/1 test pulses) ** Components to reduce EMC. Figure 6. Application Circuitry http://onsemi.com 12 NCV7356 PACKAGE DIMENSIONS SOIC−14 D SUFFIX CASE 751A−03 ISSUE G NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 14 8 −B− P 7 PL 0.25 (0.010) M B M 7 1 G F R X 45 C −T− SEATING PLANE D 14 PL 0.25 (0.010) M T B J M K S A S http://onsemi.com 13 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019 NCV7356 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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