ONSEMI NTHD4401PT1G

NTHD4401P
Power MOSFET
−20 V, −3.0 A, Dual P−Channel, ChipFET
Features
• Low RDS(on) and Fast Switching Speed in a ChipFET Package
• Leadless ChipFET Package 40% Smaller Footprint than TSOP−6
• ChipFET Package with Excellent Thermal Capabilities where Heat
http://onsemi.com
Transfer is Required
• Pb−Free Package is Available
V(BR)DSS
RDS(on) TYP
Applications
ID MAX
130 m @ −4.5 V
• Charge Control in Battery Chargers
• Optimized for Battery and Load Management Applications in
−3.0 A
−20 V
200 m @ −2.5 V
Portable Equipment
• MP3 Players, Cell Phones, Digital Cameras, PDAs
• Buck and Boost DC−DC Converters
S1
S2
G1
G2
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
−20
V
Gate−to−Source Voltage
VGS
12
V
ID
−2.1
A
Rating
Continuous Drain
Current (Note 1)
Power Dissipation
(Note 1)
Steady
State
TA = 25°C
TA = 85°C
−1.5
t5s
TA = 25°C
−3.0
Steady
State
TA = 25°C
TA = 85°C
0.6
t5s
TA = 25°C
2.1
Pulsed Drain Current
tp = 10 s
PD
−9.0
A
TJ, Tstg
−55 to
150
°C
Source Current (Body Diode)
IS
−2.5
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
Junction−to−Ambient − t 5 s
P−Channel MOSFET
ChipFET
CASE 1206A
STYLE 2
PIN
CONNECTIONS
MARKING
DIAGRAM
1 S1
1
8
A
D1 7
2 G1
2
7
°C
D2 6
3 S2
3
D2 5
4 G2
4
Symbol
Value
Unit
RJA
110
°C/W
C4 M
Junction−to−Ambient − Steady State (Note 1)
P−Channel MOSFET
D1 8
THERMAL RESISTANCE RATINGS
Rating
D2
W
1.1
IDM
Operating Junction and Storage Temperature
D1
6
5
C4 = Specific Device Code
M = Month Code
60
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq
[1 oz] including traces).
ORDERING INFORMATION
Package
Shipping†
NTHD4401PT1
ChipFET
3000/Tape & Reel
NTHD4401PT1G
ChipFET
(Pb−Free)
3000/Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
 Semiconductor Components Industries, LLC, 2004
October, 2004 − Rev. 3
1
Publication Order Number:
NTHD4401P/D
NTHD4401P
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Test Condition
Min
Typ
Max
Unit
V(Br)DSS
VGS = 0 V, ID = −250 A
−20
−23
V
−8.0
mV/°C
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Drain−to−Source Breakdown Voltage Temperature Coefficient
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
V(Br)DSS/TJ
IDSS
VGS = 0 V
TJ = 25°C
−1.0
VDS = −16 V
TJ = 85°C
−5.0
IGSS
VDS = 0 V, VGS = 12 V
VGS(th)
VGS = VDS, ID = −250 A
A
100
nA
−1.2
V
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage
Gate Threshold Temperature Coefficient
Drain−to−Source On Resistance
Forward Transconductance
VGS(th)/TJ
−0.6
−0.75
2.65
RDS(on)
VGS = −4.5 V, ID = −2.1 A
VGS = −2.5 V, ID = −1.7 A
VGS = −1.8 V, ID = −1.0 A
0.130
0.200
0.34
gFS
VDS = −10 V, ID = −2.1 A
5.0
mV/°C
0.155
0.240
S
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
Ciss
Output Capacitance
Coss
185
300
95
150
Reverse Transfer Capacitance
Crss
30
50
Total Gate Charge
QG(TOT)
3.0
6.0
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
0.9
td(on)
7.0
12
13
25
33
50
27
40
−0.85
0 85
−1.15
1 15
VGS = 0 V, f = 1.0 MHz,
VDS = −10 V
VGS = −4.5 V, VDS = −10 V,
ID = −2.1 A
pF
0.2
nC
0.5
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(off)
VGS = −4.5 V, VDD = −16 V,
ID = −2.1 A, RG = 2.5 tf
ns
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward
o a d Diode
ode Voltage
o age
VSD
Reverse Recovery Time
trr
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V
IS = −2.5 A
V
32
VGS = 0 V, dIS/dt = 90 A/s,
IS = −2.1 A
QRR
10
22
15
2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
3. Switching characteristics are independent of operating junction temperatures.
http://onsemi.com
2
ns
nC
NTHD4401P
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
VGS = −6 V to −3 V
VGS = −2.4 V
−2.2 V
4
TJ = 25°C
−2 V
−ID, DRAIN CURRENT (AMPS)
−ID, DRAIN CURRENT (AMPS)
4
3
−1.8 V
2
−1.6 V
1
−1.4 V
VDS ≥ −10 V
3
2
TC = −55°C
1
25°C
100°C
−1.2 V
0
1
2
4
3
5
7
6
0
0.5
8
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1
1.5
2
2.5
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
0
0.5
ID = −2.1 A
TJ = 25°C
0.4
0.3
0.2
0.1
0
1
6
2
4
3
5
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
3
0.25
TJ = 25°C
0.225
0.2
VGS = −2.5 V
0.175
0.15
VGS = −4.5 V
0.125
0.1
0.5
1.5
2.5
3.5
4.5
−ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
ID = −2.1 A
VGS = −4.5 V
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
1.6
1.4
1.2
1
0.8
0.6
−50
−25
0
25
50
75
100
125
150
ID = −1.0 A
VGS = −1.8 V
1.2
1
0.8
−50
TJ, JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. On−Resistance Variation with
Temperature
http://onsemi.com
3
150
NTHD4401P
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
600
10000
VDS = 0 V
VGS = 0 V
C, CAPACITANCE (pF)
−IDSS, LEAKAGE (A)
500
TJ = 150°C
1000
TJ = 100°C
100
VGS = 0 V
TJ = 25°C
Ciss
400
Crss
300
200
Coss
100
0
10
2
4
6
8
10
12
14
16
18
10
20
5
0
−VGS −VDS
5
10
15
20
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
−VDS
5
10
QT
8
4
−VGS
3
6
Q1
2
Q2
4
1
ID = −2.1 A
TJ = 25°C
0
3.5
0
0
0.5
1.5
2.5
1
2
Qg, TOTAL GATE CHARGE (nC)
2
3
100
tf
td(off)
t, TIME (ns)
12
Figure 8. Capacitance Variation
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
6
tr
10
td(on)
VDD = −16 V
ID = −2.1 A
VGS = −4.5 V
1
1
10
Figure 10. Resistive Switching Time Variation
vs. Gate Resistance
2.5
VGS = 0 V
TJ = 25°C
2
1.5
1
0.5
0
0.3
100
RG, GATE RESISTANCE (OHMS)
Figure 9. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
−IS, SOURCE CURRENT (AMPS)
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Drain−to−Source Leakage Current
vs. Voltage
0.5
0.7
0.9
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 11. Diode Forward Voltage vs. Current
http://onsemi.com
4
NTHD4401P
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1.0
0.1
D = 0.5
0.2
0.1
Normalized to θJA at 10s.
0.05
Chip
0.02
0.0175 Ω
0.0710 Ω
0.2706 Ω
0.0154 F
0.0854 F
0.3074 F
0.5776 Ω
0.7086 Ω
0.01
SINGLE PULSE
0.01
1.0E−03
1.0E−02
1.0E−01
1.0E+00
t, TIME (s)
Figure 12. Thermal Response
http://onsemi.com
5
1.0E+01
1.7891 F
1.0E+02
107.55 F
Ambient
1.0E+03
NTHD4401P
SOLDERING FOOTPRINT*
2.032
0.08
2.032
0.08
0.457
0.018
0.635
0.025
1.092
0.043
0.635
0.025
0.178
0.007
0.457
0.018
0.711
0.028
0.66
0.026
SCALE 20:1
mm
inches
0.254
0.010
0.66
0.026
Figure 13. Basic
SCALE 20:1
mm inches
Figure 14. Style 2
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BASIC PAD PATTERNS
confines of the basic footprint. The drain copper area is
0.0019 sq. in. (or 1.22 sq. mm). This will assist the power
dissipation path away from the device (through the copper
leadframe) and into the board and exterior chassis (if
applicable) for the single device. The addition of a further
copper area and/or the addition of vias to other board layers
will enhance the performance still further.
The basic pad layout with dimensions is shown in
Figure 13. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area, particularly
for the drain leads.
The minimum recommended pad pattern shown in
Figure 14 improves the thermal area of the drain
connections (pins 5, 6, 7, 8) while remaining within the
http://onsemi.com
6
NTHD4401P
PACKAGE DIMENSIONS
ChipFET
CASE 1206A−03
ISSUE E
A
8
7
M
6
K
5
S
5
6
7
8
4
3
2
1
B
1
2
3
L
4
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM
PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN
HORIZONTAL AND VERTICAL SHALL NOT EXCEED
0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE
BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND
BOTTOM LEAD SURFACE.
7. 1206A−01 AND 1206A−02 OBSOLETE. NEW
STANDARD IS 1206A−03.
J
G
DIM
A
B
C
D
G
J
K
L
M
S
C
0.05 (0.002)
MILLIMETERS
MIN
MAX
2.95
3.10
1.55
1.70
1.00
1.10
0.25
0.35
0.65 BSC
0.10
0.20
0.28
0.42
0.55 BSC
5 ° NOM
1.80
2.00
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
http://onsemi.com
7
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
INCHES
MIN
MAX
0.116
0.122
0.061
0.067
0.039
0.043
0.010
0.014
0.025 BSC
0.004
0.008
0.011
0.017
0.022 BSC
5 ° NOM
0.072
0.080
NTHD4401P
ChipFET is a trademark of Vishay Siliconix.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
http://onsemi.com
8
For additional information, please contact your
local Sales Representative.
NTHD4401P/D