SAMSUNG C9658

S3C9654/C9658/P9658
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
SAM88RCRI PRODUCT FAMILY
Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offer fast and efficient CPU, a wide
range of integrated peripherals, and supports OTP device.
A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a flexible programming
environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating
modes are included to support real-time operations.
S3C9654/C9658/P9658 MICROCONTROLLER
The S3C9654/C9658/P9658 microcontroller with USB function can be used in a wide range of general purpose
applications. It is especially suitable for mouse or joystick controller and is available in 16, 18, 20-pin DIP and
SOP package.
The S3C9654/C9658/P9658 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is
built around the powerful SAM88RCRI CPU core.
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The S3C9654/C9658/P9658 has 4/8 Kbytes of
program memory on-chip (S3C9654/C9658), and 208 bytes of RAM including 16 bytes of working register.
Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core:
— Three configurable I/O ports (14 pin, at 20 pin)
— 14-bit programmable pins for external interrupts (at 20 pin)
— 8-bit timer/counter with two operating modes
OTP
The S3C9654/C9658 microcontroller is also available in OTP (One Time Programmable) version. S3P9658
microcontroller has an on-chip 4/8 Kbyte one-time-programmable EPROM instead of masked ROM. The
S3P9658 is comparable to S3C9654/C9658, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C9654/C9658/P9658
FEATURES
CPU
Timer/Counter
•
•
One 8-bit basic timer for watchdog function and
programmable oscillation stabilization interval
generation function
•
One 8-bit timer/counter with Compare/Overflow
counter
SAM88RCRI CPU core
Memory
•
4-K byte internal program memory
(ROM S3C9654)
•
8-K byte internal program memory
(ROM S3P9658/C9658)
•
208-byte RAM
•
16 bytes of working register
USB Serial Bus
•
Compatible to USB low speed (1.5 Mbps) device
1.0 specification.
•
Serial bus interface engine (SIE)
— Packet decoding/generation
Instruction Set
•
41 instructions
— CRC generation and checking
•
IDLE and STOP instructions added for powerdown modes
— NRZI encoding/decoding and bit-stuffing
Instruction Execution Time
•
0.66 µs at 6 MHz fOSC
•
Two 8-byte receive/transmit USB buffer
Operating Temperature Range
•
– 0°C to + 85°C
Interrupts
Operating Voltage Range
•
14 interrupt sources with one vector (20 pin)
•
•
12 interrupt sources with one vector (18 pin)
•
10 interrupt sources with one vector (16 pin)
•
One level, one vector interrupt structure
4.0 V to 5.25 V
Package Types
•
16, 18, 20 pin DIP
•
16, 18, 20 pin SOP
Oscillation Circuit Options
•
6 MHz crystal/ceramic oscillator
•
External clock source
•
RC oscillator
•
Embedded oscillation capacitor (XI, XO, 33pF)
General I/O
•
14 bit-programmable I/O pins (20 pin)
•
12 bit-programmable I/O pins (18 pin)
•
10 bit-programmable I/O pins (16 pin)
Sub Oscillator
•
Internal RC sub oscillator
•
Auto interrupt wake-up
1-2
Comparator
•
6-channel mode, 32 step resolution
•
5-channel mode, external reference
•
Low EMI design
Low Voltage Reset
•
Low voltage Reset
•
Power on Reset
High Sink Current Pin for LED
•
P0.0 (VOL: 0.4 V, 50mA)
S3C9654/C9658/P9658
PRODUCT OVERVIEW
BLOCK DIAGRAM
TEST
RESET
Port I/O and
Interrupt Control
XIN
OSC
Port 1/
Compa
-rator
P1.0/CIN0/INT1
P1.1/CIN0/INT1
P1.2/CIN0/INT1
P1.3/CIN0/INT1
P1.4/CIN0/INT1
P1.5/CIN0/INT1
Port 0
P0.0/INT0
P0.1/INT0
P0.2/INT0 (note)
P0.3/INT0 (note)
P0.4/INT0 (note)
P0.5/INT0 (note)
XOUT
SUB
OSC
SAM88RCRI CPU
Basic
Timer
Timer 0
LVR
8K (4K)
ROM
NOTE:
208 Byte
RAM
USB
SIE
P2.1/D+/INT2
P2.0/D-/INT2
16, 18, 20 DIP and SOP.
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C9654/C9658/P9658
PIN ASSIGNMENTS
P0.2/INT0
1
20
P0.3/INT0
VSS
2
19
VDD
P0.0/INT0
3
18
P2.0/D-/INT2
P1.0/COM0/INT1
4
17
P2.1/D+/INT2
P1.1/COM1/INT1
5
16
RESET
P1.2/COM2/INT1
6
15
XIN
P1.3/COM3/INT1
7
14
XOUT
P1.4/COM4/INT1
8
13
TEST
P1.5/COM5/INT1
9
12
P0.1/INT0
10
11
P0.5/INT0
P0.4/INT0
S3C9654/
S3C9658
Figure 1-2. Pin Assignment (20 Pin)
1-4
S3C9654/C9658/P9658
PRODUCT OVERVIEW
P0.2/INT0
1
18
P0.3/INT0
VSS
2
17
VDD
P0.0/INT0
3
16
P2.0/D-/INT2
P1.0/COM0/INT1
4
15
P2.1/D+/INT2
P1.1/COM1/INT1
5
14
RESET
P1.2/COM2/INT1
6
13
XIN
P1.3/COM3/INT1
7
12
XOUT
P1.4/COM4/INT1
8
11
TEST
P1.5/COM5/INT1
9
10
P0.1/INT0
S3C9654/
S3C9658
Figure 1-3. Pin Assignment (18 Pin)
VSS
1
16
VDD
P0.0/INT0
2
15
P2.0/D-/INT2
P1.0/COM0/INT1
3
14
P2.1/D+/INT2
P1.1/COM1/INT1
4
13
RESET
P1.2/COM2/INT1
5
12
XIN
P1.3/COM3/INT1
6
11
XOUT
P1.4/COM4/INT1
7
10
TEST
P1.5/COM5/INT1
8
9
S3C9654/
S3C9658
P0.1/INT0
Figure 1-4. Pin Assignment (16 Pin)
1-5
PRODUCT OVERVIEW
S3C9654/C9658/P9658
Table 1-1. Signal Descriptions
Pin Names
Pin
Type
Pin Description
Circuit
Number
Pin
Numbers
Share
Pins
P0.0
I/O
Bit-programmable I/O port for Schmitt trigger
input or n-ch open drain output (50 mA).
Pull-up resistor is assignable to input pin by
software and is automatically disabled for
output pin. Port 0 can be individually configured
as external interrupt input.
SK
3
INT0
P0.1–P0.5
I/O
Bit-programmable I/O port for Schmitt trigger
input or push-pull output. Pull-up resistors
individually assignable to input pins by software
and are automatically disabled for output pins.
Port 0 can be individually configured as
external interrupt inputs.
D
1, 10, 11,
12, 20
INT0
P1.0–P1.5
I/O
Bit-programmable I/O port for Schmitt trigger
input or push-pull output. Pull-up resistors are
individually assignable to input pins by
software. Port 1 can be configured as
comparator input or external interrupt inputs.
Pull-down resistors are individually assignable.
(in comparator input)
CP
4–9
CIN0-5
INT1
P2.0/D–
P2.1/D+
I/O
Bit-programmable I/O port for Schmitt trigger
input or n-ch open drain output. Pull-up
resistors are individually assignable to input
pins by software and are automatically disabled
for output pins. Port 2 can be individually
configured as external interrupt inputs. Also it
can be configured as an USB ports.
CP
17, 18
INT2
XOUT, XIN
–
System clock input and output pin
(crystal/ceramic oscillator, or external clock
source)
–
14, 15
–
INT0
I
External interrupt for bit-programmable port 0
D
1, 3, 10,
11, 12, 20
Port 0
INT1
I
External interrupt for bit-programmable port 1
D
4–9
Port 1
INT2
I
External interrupt for bit-programmable port 2
D
17, 18
Port 2
VDD
–
Power input pin
–
19
–
VSS
–
VSS is a ground power for CPU core.
–
2
–
RESET
1
Reset input pin (Pull-up register embedded)
–
16
–
1-6
S3C9654/C9658/P9658
PRODUCT OVERVIEW
Table 1-2. Pin Circuit Assignments for the S3C9654/C9658/P9658
Circuit Number
Circuit Type
S3C9654/C9658/P9658 Assignments
C
O
D
I/O
Port 0.1–5, INT0, INT1, INT2
SK
I/O
Port 0.0
CP
I/O
Port 1, Port 2
NOTE: Diagrams of circuit types C–D, and F-8 are presented below.
VDD
V DD
Data
P-Channel
Out
Output
DIsable
N-Channel
Pull-up
Enable
Data
Output
DIsable
Circuit
Type C
I/O
Data
Figure 1-5. Pin Circuit Type C
Figure 1-6. Pin Circuit Type D
1-7
PRODUCT OVERVIEW
S3C9654/C9658/P9658
VDD
Pull-up
Registor
Pull-up Enable
Output
Disable
I/O
Output
Data
VSS
Input
Data
MUX
D0
D1
Mode
Input Data
Output
D0
Input
D1
Figure 1-7. Pin Circuit Type SK
VDD
Pull-up
Enable
Data
Output
DIsable
Circuit
Type C
Data
Input
Enable
Analog/
External VREF
Input D+/D-
Figure 1-8. Pin Circuit Type CP
1-8
I/O
S3C9654/C9658/P9658
PRODUCT OVERVIEW
S3C9654/
S3C9658/S3P9658
Button
SW1
XI
15
14
19
XI
P0.1/INT0 12
Button
XOUT
VDD
P0.2/INT0
To
Host
2
17
18
D+
SW3
VSS
VDD
Button
+ C_BULK
VSS
VDD
D-
1
DM1
VSS
P0.3/INT0
P2.1/D+/INT2
VSS
SW2
VSS
T_X
R_XY
20
P2.0/D-/INT2
P1.0/COM0/INT1
13
P1.1/COM1/INT1
TEST
16
RESET (note)
D_X
4
5
VDD
VSS
T_Y
P1.2/COM2/INT1
P1.3/COM3/INT1
10
11
7
VDD
P0.4/INT0
P0.5/INT0
VDD
T_Z
P1.4/COM4/INT1
P1.5/COM5/INT1
P0.0/INT0
NOTE:
D_Y
6
R_Z
D_Z
8
9
3
RESET Pin is connected to internal Pull-up register after power on reset.
If RESET Pin is low, S3C9654/C9658/P9658 goes to reset.
Figure 1-9. USB Mouse Circuit Diagram
1-9
S3C9654/C9658/P9658
15
ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this section, the following S3C9654/C9658/P9658 electrical characteristics are presented in tables and graphs:
— Absolute maximum ratings
— D.C. electrical characteristics
— I/O capacitance
— A.C. electrical characteristics
— Oscillator characteristics
— Operating voltage range
— Oscillation stabilization time
— Clock timing measurement points at XIN
— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by a RESET
— Stop mode release timing when initiated by an external interrupt
— Characteristic curves
— Comparator Electrical Characteristics
15-1
ELECTRICAL DATA
S3C9654/C9658/P9658
Table 15-1. Absolute Maximum Ratings
(TA = 25°C)
Parameter
Supply voltage
Symbol
Conditions
VDD
–
Rating
Unit
– 0.3 to + 6.5
V
Input voltage
VI
All ports
– 0.3 to VDD + 0.3
V
Output voltage
VO
All output ports
– 0.3 to VDD + 0.3
V
Output current high
I OH
One I/O pin active
– 18
All I/O pins active
– 60
One I/O pin active (except P0.0)
+ 30
Total pin current for ports 0, 1, 2
(except P0.0)
+ 100
P0.0
+ 50
Output current low
I OL
Operating
temperature
TA
–
0 to + 85
Storage
temperature
TSTG
–
– 60 to + 150
15-2
mA
mA
°C
S3C9654/C9658/P9658
ELECTRICAL DATA
Table 15-2. D.C. Electrical Characteristics
(TA = 0°C to + 85°C, VDD = 4.0 V to 5.25 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
0.8 VDD
–
VDD
V
VIH1
All input pins except VIH2, D+, D–
VIH2
XIN
VIL1
All input pins except VIL2, D+, D–
–
–
0.2 VDD
VIL2
XIN
–
–
0.4
Output high voltage
VOH
VDD = 4.0 V–5.25 V
IOH = – 200 µA
All output ports except D+, D–
VDD – 1.0
–
–
Output low voltage
VOL
VDD = 4.0 V–5.25 V
IOL = 2 mA
All output ports except D+, D–, P0.0
–
–
0.4
Output low Current
IOL
VOL = 0.4 V
Input high leakage
current
ILIH1
VIN = VDD
All inputs except ILIH2
except D+, D–, XOUT
–
–
3
ILIH2
VIN = VDD, XIN
–
–
20
ILIL1
VIN = 0 V
All inputs except ILIL2
except D+, D–, XOUT
–
–
–3
ILIL2
VIN = 0 V, XIN
–
–
– 20
Output high leakage
current
ILOH
VOUT = VDD
All output pins except D+, D–
–
–
3
Output low leakage
current
ILOL
VOUT = 0 V
All output pins except D+, D–
XOUT, P0.0
–
–
–3
Pull-up resistors
RL1
VIN = 0 V, VDD = 5.0 V,
Port 0, Port 1
25
50
100
RL2
VIN = 0 V, VDD = 5.0 V,
Port 2
–
4.3
–
IDD1
Normal operation mode,
VDD = 4.0 V–5.25 V
6 MHz, CPU clock
–
6.5
15
IDD2
IDLE mode
VDD = 4.0 V–5.25 V
6 MHz, CPU clock
–
2
4
IDD3
Stop mode, oscillator stop
VDD = 4.0 V–5.25 V
–
13
25
Input high voltage
Input low voltage
Input low leakage
current
Supply current
VDD – 0.5
VDD
50(4)
mA
µA
KΩ
mA
µA
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors or external output current load.
2. This parameter is guaranteed, but not tested (include D+, D–).
3. Only in 4.0 V to 5.25 V, D+ and D– satisfy the USB spec 1.0.
4. P0.0 designed for direct LED current sink, see the SNKCON resistor and Figure 1-9 (Page 1-9).
15-3
ELECTRICAL DATA
S3C9654/C9658/P9658
Table 15-3. Input/Output Capacitance
(TA = 0°C to + 85°C, VDD = 0 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input
capacitance
CIN
f = 1 MHz; unmeasured pins
are connected to VSS
–
–
10
pF
Output
capacitance
COUT
–
33
–
Min
Typ
Max
Unit
100
–
200
ns
I/O capacitance
XI/XO capacitance
Except XIN, XOUT
CIO
CXI, CXO
XIN, XOUT
Table 15-4. A.C. Electrical Characteristics
(TA = 0°C to + 85°C, VDD = 4.0 V to 5.25 V)
Parameter
Noise filter
Symbol
Conditions
tNF1H, tNF1L P1 (RC delay)
tNF1L
tNF1H
tNF2
0.8 VDD
0.5 VDD
0.2 VDD
Figure 15-1. Nose Filter Timing Measurement Points
15-4
S3C9654/C9658/P9658
ELECTRICAL DATA
Table 15-5. Oscillator Characteristics
(TA = 0°C + 85°C)
Oscillator
Clock Circuit
Main crystal Main
ceramic
(fOSC)
X IN
Test Condition
Min
Typ
Max
Unit
Oscillation frequency
VDD = 4.0 V–5.25 V
–
6.0
–
MHz
Oscillation frequency
VDD = 4.0 V–5.25 V
–
6.0
–
MHz
X OUT
External clock
X IN
X OUT
RC oscillator
XIN
R
XOUT
Oscillation frequency
VDD = 5.0 V
R = 22.6 K
R = 8.8 K
R = 3.2 K
MHz
–
–
–
1.0
2.0
4.0
–
–
–
Table 15-6. Oscillation Stabilization Time
(TA = 0°C + 85°C, VDD = 4.0 V to 5.25 V)
Oscillator
Test Condition
Min
Typ
Max
Unit
–
–
10
ms
Main crystal
VDD = 4.0 V to 5.25 V, fOSC > 6.0 MHz
Main ceramic
(Oscillation stabilization occurs when VDD is
equal to the minimum oscillator voltage range.)
Oscillator
tWAIT stop mode release time by a reset
–
216/fOSC
–
stabilization wait
time
tWAIT stop mode release time by an interrupt
–
–
–
NOTE: The oscillator stabilization wait time, tWAIT, when it is released by an interrupt, is determined by the setting in the
basic timer control register, BTCON.
15-5
ELECTRICAL DATA
S3C9654/C9658/P9658
1/f OSC
tXL
tXH
V DD - 0.5 V
X IN
0.4 V
Figure 15-2. Clock Timing Measurement Points at XIN
Table 15-7. Data Retention Supply Voltage in Stop Mode
(TA = 0°C to + 70°C)
Parameter
Symbol
Conditions
Data retention
supply voltage
VDDDR
Stop mode
Data retention
supply current
IDDDR
Stop mode; VDDDR = 2.0 V
15-6
Min
Typ
Max
Unit
2.0
–
6
V
–
–
5
µA
S3C9654/C9658/P9658
ELECTRICAL DATA
IDLE Mode
(Basic Timer Active)
~
~
Stop Mode
Data Retention Mode
External
Interrupt
~
~
VDD
Normal
Operating
Mode
VDDDR
Execution Of
Stop Instrction
0.8 VDD
0.2 VDD
tWAIT
Figure 15-3. Stop Mode Release Timing When Initiated by an External Interrupt
Table 15-8. Comparator Electrical Characteristics
(TA = 0°C to + 85°C, VDD = 4.0 V to 5.25 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Conversion time (1)
tCON
–
–
6 × 12
or
6 × 192
–
f CPU
Comparator input
voltage
VICN
–
VSS
–
VDD
V
Comparator input
impedance
RCN
–
2
1000
–
MΩ
Comparator
reference voltage
VREF
–
1.8
–
VDD
V
Comparator input
current
ICIN
VDD = 5 V
–3
–
3
µA
Reference input
current
IREF
VDD = 5 V
–3
–
3
µA
Comparator block
ICOM
VDD = 5.5 V
–
1
2
mA
VDD = 4.5 V
0.5
1
mA
VDD = 5 V
(when power down mode)
100
500
nA
current (2)
NOTES:
1. Conversion time is the time required from the moment a conversion operation starts until it ends.
2. ICOM is an operating current during conversion.
15-7
ELECTRICAL DATA
S3C9654/C9658/P9658
Table 15-9. Low Speed Source Electrical Characteristics (USB)
(TA = 0°C to + 85°C, Internal Voltage Regulator Output V33OUT = 2.8 V to 3.6 V, typ 3.3 V)
Parameter
Symbol
Conditions
Min
Max
Unit
CL = 200 pF
75
–
ns
CL = 650 pF
–
300
CL = 200 pF
75
–
CL = 650 pF
–
300
Transition Time:
Rise Time
Tr
Fall Time
Tf
Rise/Fall Time Matching
Trfm
(Tr/Tf) CL = 50 pF
80
125
%
Output Signal Crossover Voltage
Vcrs
CL = 50 pF
1.3
2.0
V
Internal Voltage Regulator Output
Voltage
V33OUT
VDD = 4.0 – 5.25 V
2.8
3.6
V
Test
Point
V33OUT
S/W
D-/D+
D. U. T
R1
R2
90 %
90 %
Measurement
Points
10 %
C2
10 %
Tr
R1 = 15 KΩ
R2 = 1.5 KΩ
CL = 200 pF - 650 pF
Tf
DM: S/W ON
DP: S/W OFF
Figure 15-4. USB Data Signal Rise and Fall Time
3.3 V
DP
MAX: 2.0 V
VCRS
MIN: 1.3 V
DM
0V
Figure 15-5. USB Output Signal Crossover Point Voltage
15-8
S3C9654/C9658/P9658
16
MECHANICAL DATA
MECHANICAL DATA
OVERVIEW
This section contains the following information about the device package:
— Package dimensions in millimeters
— Pad diagram
#11
0-15
0.2
5
20-DIP-300A
+0
- 0 .10
.05
7.62
6.40 ± 0.20
#20
0.46 ± 0.10
(1.77)
NOTE:
1.52 ± 0.10
2.54
5.08 MAX
26.40 ± 0.20
3.30 ± 0.30
26.80 MAX
3.25 ± 0.20
#10
0.51 MIN
#1
Dimensions are in millimeters.
Figure 16-1. 20-DIP 300A Package Dimensions
16-1
MECHANICAL DATA
S3C9654/C9658/P9658
9.25
#11
7.62
6.48
#20
0.3
8
20-DIP-300A-SG
#1
#10
2.54
4.06
1.63
3.51
(2.92)
3.43
0.56
0.89
28.85
Figure 16-2. 20-DIP-300A-SG Package Dimensions
16-2
S3C9654/C9658/P9658
MECHANICAL DATA
0-8
#1
#10
2.30 ± 0.10
0.203
14.10 MAX
13.70 ± 0.20
+ 0.10
- 0.05
0.85 ± 0.20
20-SOP-300
9.53
5.40 ± 0.20
#11
2.50 MAX
7.80 ± 0.30
#20
1.27
(0.66)
0.40
NOTE:
+ 0.10
- 0.05
0.05 MIN
0.10 MAX
Dimensions are in millimeters.
Figure 16-3. 20-SOP-300 Package Dimensions
16-3
MECHANICAL DATA
S3C9654/C9658/P9658
10.03
#10
7.62
6.48
#18
0.3
8
18-DIP-300A-SG
#1
#9
2.54
4.06
1.63
3.51
(1.53)
3.18
0.56
0.89
23.50
Figure 16-4. 18-DIP-300A-SG Package Dimensions
16-4
S3C9654/C9658/P9658
MECHANICAL DATA
0-8
#10
7.59
18-SOP-BD300-AN
#1
0.29
#9
18.06
0.48
2.64
0.32
1.02
10.41
#18
1.27BSC
Figure 16-5. 18-SOP-BD300-AN Package Dimensions
16-5
MECHANICAL DATA
S3C9654/C9658/P9658
0.3
8
16-DIP-300A-SG
10.03
#9
7.62
6.48
#16
#1
#8
2.54
4.06
1.63
3.51
(0.53)
3.43
0.56
0.89
19.23
Figure 16-6. 16-DIP-300A-SG Package Dimensions
16-6
S3C9654/C9658/P9658
MECHANICAL DATA
0-8
#9
7.60
16-SOP-BD300-SG
#1
0.30
#8
10.56
0.48
2.65
0.32
1.27
10.50
#16
1.27BSC
Figure 16-7. 16-SOP-BD300-SG Package Dimensions
16-7
S3C9654/C9658/P9658
17
S3P9658 OTP
S3P9658 OTP
OVERVIEW
The S3P9658 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3P9658
microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data
format.
The S3P9658 is fully compatible with the S3P9658, both in function and in pin configuration. Because of its
simple programming requirements, the S3P9658 is ideal for use as an evaluation chip for the S3P9658.
P0.2/INT0
1
20
P0.3/INT0
VSS/VSS
2
19
VDD
P0.0/INT0
3
18
P2.0/D-/INT2
SCLK/P1.0/COM0/INT1
4
17
P2.1/D+/INT2
SDAT/P1.1/COM1/INT1
5
16
RESET/RESET
RESET
P1.2/COM2/INT1
6
15
XIN
P1.3/COM3/INT1
7
14
XOUT
P1.4/COM4/INT1
8
13
TEST/TEST
P1.5/COM5/INT1
9
12
P0.1/INT0
10
11
P0.5/INT0
P0.4/INT0
NOTE:
S3P9658
The bold is indicate an OTP pin name.
Figure 17-1. S3P9658 Pin Assignments (20 Pin)
17-1
KS86P6504/P6508 OTP
S3C9654/C9658/P9658
P0.2/INT0
1
18
P0.3/INT0
VSS/VSS
2
17
VDD/VDD
P0.0/INT0
3
16
P2.0/D-/INT2
SCLK/P1.0/COM0/INT1
4
15
P2.1/D+/INT2
SDAT/P1.1/COM1/INT1
5
14
RESET/RESET
RESET
P1.2/COM2/INT1
6
13
XIN
P1.3/COM3/INT1
7
12
XOUT
P1.4/COM4/INT1
8
11
TEST/TEST
P1.5/COM5/INT1
9
10
P0.1/INT0
NOTE:
S3P9658
The bold is indicate an OTP pin name.
Figure 17-2. S3P9658 Pin Assignments (18 Pin)
VSS/VSS
1
16
VDD/VDD
P0.0/INT0
2
15
P2.0/D-/INT2
SCLK/P1.0/COM0/INT1
3
14
P2.1/D+/INT2
SDAT/P1.1/COM1/INT1
4
13
RESET/RESET
RESET
P1.2/COM2/INT1
5
12
XIN
P1.3/COM3/INT1
6
11
XOUT
P1.4/COM4/INT1
7
10
TEST/TEST
P1.5/COM5/INT1
8
9
NOTE:
S3P9658
P0.1/INT0
The bold is indicate an OTP pin name.
Figure 17-3. S3P9658 Pin Assignments (16 Pin)
17-2
S3C9654/C9658/P9658
S3P9658 OTP
Table 17-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
Pin Name
P1.0
During Programming
Pin Name
Pin Number (20 DIP)
I/O
SDAT
5
I/O
Serial Data Pin (Output when reading, Input when
writing) Input and Push-pull Output Port can be
assigned
SCLK
4
I/O
Serial Clock Pin (Input Only Pin)
RESET
RESET
16
I
0 V : OTP write and test mode
5 V : Operating mode
TEST
VPP
(TEST)
13
I
Chip Initialization and EPROM Cell Writing Power
Supply Pin (Indicates OTP Mode Entering) When
writing 12.5 V is applied and when reading.
VDD/VSS
VDD/VSS
19/2
I
Logic Power Supply Pin.
P1.1
Function
Table 17-2. Comparison of S3P9658 and S3C9654/C9658 Features
Characteristic
S3P9658
S3C9654/C9658
Program Memory
8 K-byte EPROM
4/8 K-byte mask ROM
Operating Voltage (VDD)
4.0 V to 5.25 V
4.0 V to 5.25 V
OTP Programming Mode
VDD = 5 V, VPP (TEST) = 12.5 V
Pin Configuration
20/18/16 DIP, 20/18/16 SOP
20/18/16 DIP, 20/18/16 SOP, 16SSOP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (RESET) pin of the S3P9658, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 14-3 below.
Table 17-3. Operating Mode Selection Criteria
VDD
VPP (RESET
RESET)
REG/MEM
MEM
Address (A15-A0)
R/W
5V
5V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
Mode
NOTE: "0" means Low level; "1" means High level.
17-3