S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) 1 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals and various mask-programmable ROM sizes. Important CPU features include: — Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupt — Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels. S3C80E5/C80E7 MICROCONTROLLER The S3C80E5/C80E7 single-chip CMOS microcontroller is fabricated using a highly advanced CMOS process, based on Samsung’s newest CPU architecture. — Internal LVD circuit and twelve bitprogrammable pins for external interrupts. The S3C80E5/C80E7 is the microcontroller which has 16/24-Kbyte mask-programmable ROM. The S3P80E5/P80E7 is the microcontroller which has 16/24-Kbyte one-time-programmable EPROM. — One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes. Using a proven modular design approach, Samsung engineers developed the S3C80E5/C80E7 by integrating the following peripheral modules with the powerful SAM87 core: — Four programmable I/O ports, including three 8-bit ports and one 2-bit port, for a total of 26 pins. — One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset). — One 8-bit counter with auto-reload function and one-shot or repeat control. The S3C80E5/C80E7 is a versatile general-purpose microcontroller which is especially suitable for use as unified remote transmitter controller. It is currently available in a 32-pin SOP and SDIP package for S3C80E5 and S3C80E7. And available in 40 DIP package only for S3C80E7. OTP The S3P80E5/P80E7 is an OTP (One Time Programmable) version of the S3C80E5/C80E7 microcontroller. The S3P80E5/P80E7 microcontroller has an on-chip 16/24-Kbyte one-time-programmable EPROM instead of a masked ROM. The S3P80E5/P80E7 is comparable to the S3C80E5/C80E7, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) FEATURES CPU Carrier Frequency Generator • • SAM87 CPU core Memory One 8-bit counter with auto-reload function and one-shot or repeat control (Counter A) Back-up mode • 16-Kbyte internal program memory (ROM): S3C80E5 • 24-Kbyte internal program memory (ROM): S3C80E7 • 256-byte internal (RAM): 8000–80FFH Low Voltage Detect Circuit • Data memory: 317-byte internal register file • Low voltage detect for reset or back-up mode input. • Low level detect voltage : 2.2 V (Typ) –100 mV/+ 200 mV Instruction Set • 78 instructions • IDLE and STOP instructions added for powerdown modes Instruction Execution Time • 750 ns at 8 MHz f OSC (minimum) Interrupts • When reset pin is low level or when VDD is lower than VLVD, the chip enters back-up mode to reduce current consumption. Operating Temperature Range • – 40°C to + 85 °C Operating Voltage Range • 2.0 V to 5.5 V at 4 MHz fOSC • 2.1 V to 5.5 V at 8 MHz fOSC • Six interrupt levels and 18 interrupt sources • 15 vectors (14 sources have a dedicated vector address and four sources share a single vector) Package Type • Fast interrupt processing feature (for one selected interrupt level) • 32-pin SOP • 32-pin SDIP • 40-pin DIP I/O Ports • Three 8-bit I/O ports (P0–P2) and one 2-bit port (P3) for a total of 26 bit-programmable pins • Twelve input pins for external interrupts Timers and Timer/Counters • One programmable 8-bit basic timer (BT) for oscillation stabilization control or watchdog timer (software reset) function • One 8-bit timer/counter (Timer 0) with three operating modes; Interval, Capture, and PWM • One 16-bit timer/counter (Timer 1) with two operating modes; Interval and Capture 1-2 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) PRODUCT OVERVIEW BLOCK DIAGRAM VDD LVD P0.0–P0.7 (INT0–INT4) P1.0–P1.7 PORT 0 PORT 1 RESET TEST INTERNAL BUS PORT2 XIN XOUT MAIN OSC P2.0–P2.3 (INT5–INT8) P2.4–P2.7 I/O PORT and INTERRUPT CONTROL P3.0/T0PWM/ T0CAP/T1CAP 8-BIT BASIC TIMER 8-BIT TIMER/ COUNTER PORT 3 SAM87 CPU PROGRAM MEMORY (16/24-Kbyte Program Memory and 256-Byte Program RAM) P3.1/REM/T0CK 317-BYTE REGISTER FILE CARRIER GENERATOR (COUNTER A) 16-BIT TIMER/ COUNTER Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) PIN ASSIGNMENTS VSS XIN XOUT TEST P2.0/INT5 P2.1/INT6 P2.2/INT7 P2.3/INT8 P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3/INT3 P0.4/INT4 P0.5/INT4 P0.6/INT4 P0.7/INT4 1 2 3 4 5 6 S3C80E5 7 S3C80E7 8 32-SOP/SDIP 9 10 (Top View) 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD RESET/BACK-UP MODE P3.1/REM/T0CK P3.0/T0PWM/T0CAP/T1CAP P2.7 P2.6 P2.5 P2.4 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 Figure 1-2. Pin Assignment (32-Pin SOP/SDIP Package) VSS XIN XOUT TEST NC NC P2.0/INT5 P2.1/INT6 P2.2/INT7 P2.3/INT8 P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3/INT3 NC NC P0.4/INT4 P0.5/INT4 P0.6/INT4 P0.7/INT4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 S3C80E5 S3C80E7 40-DIP (Top View) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD RESET/BACK-UP MODE P3.1/REM/T0CK P3.0/T0PWM/T0CAP/T1CAP NC NC P2.7 P2.6 P2.5 P2.4 P1.7 P1.6 P1.5 P1.4 NC NC P1.3 P1.2 P1.1 P1.0 Figure 1-3. Pin Assignment (40-Pin DIP Package) 1-4 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) PRODUCT OVERVIEW Table 1-1. Pin Descriptions Pin Names Pin Type Pin Description Circuit Type Pin No. (32-pin) Pin No. (40-pin) Shared Functions P0.0–P0.7 I/O I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors are assignable by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/disable, and interrupt pending control. 1 9–16 11–14, 17–20 INT0–INT4 P1.0–P1.7 I/O I/O port with bit-programmable pins. Configurable to C-MOS input mode or output mode. Pin circuits are either pushpull or n-channel open-drain type. Pull-up resistors are assignable by software. 2 17–24 21–24, 27–30 – P2.0–P2.3 P2.4–P2.7 I/O General-purpose I/O port with bitprogrammable pins. Configurable to CMOS input mode, push-pull output mode, or n-channel open-drain output mode. Pull-up resistors are assignable by software. Lower nibble pins, P2.3–P2.0, can be assigned as external interrupt inputs with noise filters, interrupt enable/disable, and interrupt pending control. 3 4 5–8, 25–28 7–10, 31–34 INT5–INT8 – P3.0 P3.1 I/O 2-bit I/O port with bit-programmable pins. Configurable to C-MOS input mode, pushpull output mode, or n-channel open-drain output mode. Pull-up resistors are assignable by software. The two port 3 pins have high current drive capability. 5 29 30 37 38 T0PWM/ T0CAP/ T1CAP/ REM/T0CK XIN, XOUT – System clock input and output pins – 2, 3 2, 3 – RESET/ BACK-UP MODE I System reset signal input pin and back-up mode input pin. The pin circuit is a C-MOS input. 6 31 39 – TEST I Test signal input pin (for factory use only; must be connected to VSS). – 4 4 – VDD – Power supply input pin – 32 40 – VSS – Ground pin – 1 1 – 1-5 PRODUCT OVERVIEW S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) PIN CIRCUITS VDD PULL-UP RESISTOR (Typical 21 KΩ) PULL-UP ENABLE VDD DATA I/O OUTPUT DISABLE NOISE FILTER INTERRUPT INPUT IRQ6,7 (INT0-4) VSS NORMAL INPUT STOP NOTE: Oscillator Release (SED and R circuit) To prevent and recover from abnormal stop status caused by battery bouncing, the S3P80E5 has a special logic_ SED and R circuit −related to P0 and P1. This is a specific function for key input/output of universal remote controller. When these ports (P0, P1) are used as a normal input pin, unexpected stop mode recovery can occur by input level switching. Hence, the user should be aware of input level switching, if P0 and P1 are to be used as normal input ports. Figure 1-4. Pin Circuit Type 1 (Port 0) 1-6 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) PRODUCT OVERVIEW VDD PULL-UP RESISTOR (Typical 21 KΩ) PULL-UP ENABLE VDD DATA I/O OUTPUT DISABLE VSS NORMAL INPUT STOP NOTE: NOISE FILTER Oscillator Release (SED and R circuit) To prevent and recover from abnormal stop status caused by battery bouncing, the S3P80E5 has a special logic −SED and R circuit −related to P0 and P1. This is a specific function for key input/output of universal remote controller. When these ports (P0, P1) are used as a normal input pin, unexpected stop mode releasing can occur by input level switching. Hence, the user should be aware of input level switching, if P0 and P1 are to be used as normal input ports. Figure 1-5. Pin Circuit Type 2 (Port 1) 1-7 PRODUCT OVERVIEW S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) VDD PULL-UP RESISTOR (Typical 21 KΩ) PULL-UP ENABLE VDD DATA I/O OPEN-DRAIN OUTPUT DISABLE VSS EXTERNAL INTERRUPT IRQ5 (INT5-8) NOISE FILTER NORMAL INPUT Figure 1-6. Pin Circuit Type 3 (Ports 2.0–2.3) 1-8 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) PRODUCT OVERVIEW VDD PULL-UP RESISTOR (Typical 21 KΩ) PULL-UP ENABLE VDD DATA I/O OPEN-DRAIN OUTPUT DISABLE VSS NORMAL INPUT Figure 1-7. Pin Circuit Type 4 (P2.4− −P2.7) 1-9 PRODUCT OVERVIEW S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) VDD PULL-UP RESISTOR (Typical 21 KΩ) PULL-UP ENABLE SELECT VDD PORT 3 DATA ALTERNATIVE OUTPUT M U X DATA I/O OPEN-DRAIN OUTPUT DISABLE VSS NORMAL INPUT ALTERNATIVE INPUT NOISE FILTER Figure 1-8. Pin Circuit Type 5 (P 3) BACK-UP MODE RESET/ BACK-UP MODE NOISE FILTER SYSTEM RESET Figure 1-9. Pin Circuit Type 6 (RESET RESET/BACK-UP BACK-UP MODE) MODE 1-10 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) 14 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, the S3C80E5/C80E7 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — Characteristics of low voltage detect circuit — Data retention supply voltage in Stop mode — Stop mode release timing when initiated by an external interrupt — Stop mode release timing when initiated by a RESET — Stop mode release timing when initiated by a LVD — I/O capacitance — A.C. electrical characteristics — Input timing for external interrupts (port 0, P2.3–P2.0) — Input timing for RESET — Oscillation characteristics — Oscillation stabilization time — Operating voltage range 14-1 ELECTRICAL DATA S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) Table 14-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Conditions Rating Unit Supply voltage VDD – – 0.3 to + 6.5 V Input voltage VIN – – 0.3 to VDD + 0.3 V Output voltage VO All output pins – 0.3 to VDD + 0.3 V Output current High I OH One I/O pin active – 18 mA All I/O pins active – 60 One I/O pin active + 30 Total pin current for ports 0, 1, and 2 + 100 Total pin current for port 3 + 40 I OL Output current Low mA Operating temperature TA – – 40 to + 85 °C Storage temperature TSTG – – 65 to + 150 °C Table 14-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Symbol Operating Voltage VDD Conditions Min Typ Max Unit f OSC = 8 MHz (Instruction clock = 1.33 MHz) 2.1 – 5.5 V f OSC = 4 MHz (Instruction clock = 0.67 MHz) 2.0 – 5.5 – VDD Input High VIH1 All input pins except VIH2 and VIH3 0.8 VDD voltage VIH2 RESET 0.85 VDD VDD VIH3 XIN VDD – 0.3 VDD VIL1 All input pins except VIL2 and VIL3 VIL2 RESET VIL3 XIN VOH1 VDD = 2.4 V; IOH = – 6 mA VDD – 0.7 VDD = 2.4 V; IOH = – 3 mA VDD – 0.7 Input Low voltage Output High voltage VOH2 14-2 Port 3.1 only; TA = 25 °C Port 3.0 only; TA = 25 °C 0 – 0.2 VDD V V 0.4 VDD 0.3 – – V S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) ELECTRICAL DATA Table 14-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Output High voltage Symbol VOH3 Conditions VDD = 5 V; IOH = – 3 mA Port 2.7 only; TA = 25°C Min Typ Max Unit VDD – 0.25 – – V 0.4 0.5 V VDD = 2 V; IOH = – 1 mA Port 2.7 only; TA = 25°C Output Low voltage Input High leakage current Input Low leakage current VOH4 VDD = 3.0 V; IOH = – 1 mA All output pins except P3 and P2.7 port; TA = 25°C VOL1 VDD = 2.4 V; IOL = 15 mA VDD – 1 – Port 3.1 only; TA = 25°C VOL2 VDD = 2.4 V; IOL = 5 mA 0.4 0.5 VOL3 IOL = 1 mA 0.4 1 ILIH1 VIN = VDD All input pins except XIN and XOUT – 1 ILIH2 VIN = VDD, XIN, and XOUT ILIL1 VIN = 0 V All input pins except XIN, XOUT, Port 3.0 only; TA = 25°C Port 0, 1, and 2; TA = 25°C – µA 20 – – –1 µA and RESET ILIL2 VIN = 0 V XIN and XOUT Output High leakage current ILOH VOUT = VDD All output pins – – 1 µA Output Low leakage current ILOL VOUT = 0 V All output pins – – –1 µA Pull-up resistors RL1 VIN = 0 V; VDD = 2.4 V 44 55 82 kΩ VDD = 5.5 V 15 21 32 – 20 TA = 25 °C; Ports 0–3 14-3 ELECTRICAL DATA S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) Table 14-2. D.C. Electrical Characteristics (Concluded) (TA = – 40 °C to + 85 °C, VDD = 2 V to 5.5 V) Parameter Symbol Supply current (note) IDD1 IDD2 IDD3 Conditions Min Typ Max Unit – 6 11 mA 4 MHz crystal 4.5 9 Idle mode VDD = 5 V ± 10 % 8 MHz crystal 1.8 3.5 4 MHz crystal 1.6 3 Stop mode VDD = 6.0 V 20 35 VDD = 5.5 V 18 25 VDD = 3.3 V 12 15 VDD = 0.7 V 1.0 1.5 Operating mode VDD = 5 V ± 10 % 8 MHz crystal µA NOTE: Supply current does not include the current drawn through internal pull-up resistors or external output current loads. Table 14-3. Characteristics of Low Voltage Detect Circuit (TA = – 40 °C to + 85 °C) Parameter Symbol Conditions Min Typ Max Unit Hysteresys Voltage of LVD(Slew Rate of LVD) ∆V LVDCON = 10001111B – 10 100 mV Low level detect voltage VLVD LVDCON = 10001111B 2.10 2.20 2.40 V NOTE: The reset values of bit 1 and bit 0 are in a unknown status, so is recommended to input the value #8FH in LVDCON for typical VLVD (2.2 V –100/+200 mV). Table 14-4. Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR – 1.0 – 5.5 V Data retention supply current IDDDR – – 1 µA 14-4 VDDDR = 1.0 V Stop mode S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) ELECTRICAL DATA ~ ~ IDLE MODE (Basic Timer active) NORMAL OPERATING MODE STOP MODE ~ ~ DATA RETENTION MODE VDD VDD > VLVD EXECUTION OF STOP INSTRUCTION EXT INT 0.8 V DD 0.2 V DD t WAIT Figure 14-1. Stop Mode Release Timing When Initiated by an External Interrupt RESET OCCURS OSCILLATION STABILIZATION TIME ~ ~ STOP MODE NORMAL OPERATING MODE ~ ~ DATA RETENTION MODE VDD VDD > VLVD EXECUTION OF STOP INSTRUCTION RESET NOTE: t WAIT is the same as 4096 x 16 x 1/f OSC. t WAIT Figure 14-2. Stop Mode Release Timing When Initiated by a RESET 14-5 ELECTRICAL DATA S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) ~ ~ RESET OCCUR OSCILLATION STABILIZATION NORMAL OPERATING MODE STOP MODE ~ ~ BACK-UP MODE ~ ~ VDD VLVD VDDDR EXECUTION OF STOP INSTRUCTION t WAIT DATA RETENTION MODE NOTE: t WAIT is the same as 4096 x 16 x 1/f OSC. Figure 14-3. Stop Mode Release Timing When Initiated by a LVD Table 14-5. Input/output Capacitance (TA = – 40 °C to + 85 °C, VDD = 0 V) Parameter Symbol CIN Input capacitance Conditions f = 1 MHz; unmeasured pins are connected to VSS Min Typ Max Unit – – 10 pF Min Typ Max Unit ns COUT Output capacitance CIO I/O capacitance Table 14-6. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C) Parameter Symbol Conditions Interrupt input, High, Low width tINTH, tINTL P0.0–P0.7, P2.3–P2.0 VDD = 5 V 200 300 – RESET input Low width tRSL Input VDD = 5 V 1000 – – 14-6 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) ELECTRICAL DATA t INTL t INTH 0.8 V DD 0.2 V DD NOTE: The unit t CPU means one CPU clock period. Figure 14-4. Input Timing for External Interrupts (Port 0, P2.3–P2.0) RESET OCCRURRS NORMAL OPERATING MODE Back-Up Mode (STOP MODE) VDD OSCILLATION STABILIZATION TIME NORMAL OPERATING MODE RESET t WAIT NOTE: t WAIT is the same as 4096 x 16 x 1/f OSC. Figure 14-5. Input Timing for RESET 14-7 ELECTRICAL DATA S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) Table 14-7. Oscillation Characteristics (TA = – 40 °C + 85 °C) Oscillator Crystal Clock Circuit C1 XIN Conditions Min Typ Max Unit CPU clock oscillation frequency 1 – 8 MHz CPU clock oscillation frequency 1 – 8 MHz XIN input frequency 1 – 8 MHz Min Typ Max Unit XOUT C2 Ceramic C1 XIN XOUT C2 External clock XIN OPEN PIN XOUT S3C80E5 S3C80E7 EXTERNAL CLOCK Table 14-8. Oscillation Stabilization Time (TA = – 40 °C + 85 °C, VDD = 4.5 V to 5.5 V) Oscillator Test Condition Main crystal f OSC > 400 kHz – – 20 ms Main ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. – – 10 ms External clock (main system) XIN input High and Low width (tXH, tXL) 25 – 500 ns Oscillator stabilization tWAIT when released by a reset (1) – 216/fOSC – ms Wait time tWAIT when released by an interrupt (2) – – – ms NOTES: 1. fOSC is the oscillator frequency. 2. The duration of the oscillation stabilization time (tWAIT) when it is released by an interrupt is determined by the setting in the basic timer control register, BTCON. 14-8 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) ELECTRICAL DATA f OSC (Main oscillation frequency) INSTRUCTION CLOCK 1.33 MHz 8 MHz 1.00 MHz 6 MHz 670 kHz 4 MHz 500 kHz 250 kHz 400 kHz 8.32 kHz 1 2 3 4 2.1 5 6 7 5.5 SUPPLY VOLTAGE (V) INSTRUCTION CL OCK = 1/6n x oscillator frequency (n = 1, 2, 8, 16) Figure 14-6. Operating Voltage Range of S3P80E5/P80E7 14-9 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) 15 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C80E5/C80E7 microcontroller is currently available in 32-pin SOP and SDIP package. The S3C80E7 is also available in 40 DIP package. 0−8° #16 2.00 ± 0.1 1.27 0.05 MIN 19.90± 0.05 0.40 ± 0.1 0.25 0.90± 0.20 8.34± 0.2 32-SOP-450A #1 (0.43) 10.02 ± 0.1 #17 +0.10 - 0.05 2.30MAX 12.00± 0.2 #32 0.10 MAX NOTE: Dimensions are in millimeters. Figure 15-1. 32-Pin SOP Package Mechanical Data 15-1 MECHANICAL DATA S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) #32 #17 29.40 ± 0.2 0.45 ± 0.10 (1.37) 1.00 ± 0.10 1.778 5.08MAX 29.80 MAX 3.30 ± 0.3 #16 3.80 ± 0.2 #1 NOTE: Dimensions are in millimeters. Figure 15-2. 32-Pin SDIP Package Mechanical Data 15-2 – 0.0 5 0.25 +0.1 10.16 32-SDIP-400 0.51MIN 9.10 ± 0.20 0 – 15 * S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) MECHANICAL DATA #21 40-DIP-600B 2.54 ± 0.3 1.27 ± 0.1 0.3 MIN (1.92) 4.10 52.42 ± 0.2 ± 0.2 52.10 ± 0.2 5.08MAX #20 3.30 #1 0.2–50.+050.1 15.24 ± 0.2 13.80 #40 NOTE: Dimensions are in millimeters. Figure 15-3. 40-Pin DIP Package Mechanical Data 15-3 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) 16 S3P80E5/P80E7 OTP S3P80E5/P80E7 OTP OVERVIEW The S3P80E5/P80E7 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C80E5/C80E7microcontroller. It has an on-chip EPROM instead of a masked ROM. The S3P80E5/P80E7 is fully compatible with the S3C80E5/C80E7, both in function and in pin configuration. Because of its simple programming requirements, the S3P80E5/P80E7 is ideal as an evaluation chip for the S3C80E5/C80E7. VSS XIN A14 (2) /XOUT MODE/TEST PGM/P2.0/INT5 MEM_REG/P2.1/INT6 A8/P2.2/INT7 A9/P2.3/INT8 A0/P0.0/INT0 A1/P0.1/INT1 A2/P0.2/INT2 A3/P0.3/INT3 A4/P0.4/INT4 A5/P0.5/INT4 A6/P0.6/INT4 A7/P0.7/INT4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 S3P80E5 26 S3P80E7 32-SOP/SDIP 25 24 (Top View) 23 22 21 20 19 18 17 VDD RESET/VPP P3.1/REM/T0CK/ CE P3.0/T0PWM/T0CAP/T1CAP/ OE P2.7/ A13 P2.6/ A12 P2.5/ A11 P2.4/ A10 P1.7/ D7 P1.6/ D6 P1.5/ D5 P1.4/ D4 P1.3/ D3 P1.2/ D2 P1.1/ D1 P1.0/ D0 NOTES: 1. The bolds indicate an OTP pin name. 2. The address line 14 (A14) be used only for S3P80E7. Figure 16-1. S3P80E5/P80E7 Pin Assignments of 32SOP/32SDIP 16-1 S3P80E5/P80E7 OTP S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) VSS XIN A14/XOUT MODE/TEST NC NC PGM/P2.0/INT5 MEM_REG/P2.1/INT6 A8/P2.2/INT7 A9/P2.3/INT8 A0/P0.0/INT0 A1/P0.1/INT1 A2/P0.2/INT2 A3/P0.3/INT3 NC NC A4/P0.4/INT4 A5/P0.5/INT4 A6/P0.6/INT4 A7/P0.7/INT4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 S3P80E5 S3P80E7 40-DIP (Top View) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD RESET/VPP P3.1/REM/T0CK/ CE P3.0/T0PWM/T0CAP/T1CAP/OE NC NC P2.7/A13 P2.6/A12 P2.5/A11 P2.4/A10 P1.7/D7 P1.6/D6 P1.5/D5 P1.4/D4 NC NC P1.3/D3 P1.2/D2 P1.1/D1 P1.0/D0 NOTES: 1. The bolds indicate an OTP pin name. 2. The address line 14 (A14) be used only for S3P80E7. Figure 16-2. S3P80E5/P80E7 Pin Assignments of 40DIP 16-2 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) S3P80E5/P80E7 OTP Table 16-1. 32 SOP/SDIP Pin Descriptions Used to Read/Write the EPROM Pin Name Pin No. I/O Function A0–A14 3, 7– 6, 25–28 O Address lines to read/write EPROM D0–D7 17–24 I/O 8-bit data input/output lines to read/write EPROM MODE 4 – Select EPROM mode. CE 30 I Chip enable (Connect to VSS, when read/write EPROM) OE 29 I Output enable PGM 5 I EPROM Program enable MEM_REG 6 I Select Memory space of EPROM VDD 32 – Supply voltage (normally 5 V) VPP 31 – EPROM Program/Verify voltage (normally 12.5 V) VSS 1 – GROUND XIN 2 – System Clock input pin CHARACTERISTICS OF EPROM OPERATION When +12.5 V is supplied to VPP and MODE pins of the S3P80E5/P80E7, the EPROM programming mode is entered. The operating mode (read, write) is selected according to the input signals to the pins listed in Table 162 as below. Table 16-2. Operating Mode Selection Criteria VDD MODE VPP PGM MEM OE 5V VPP 12.5 V 1 1 0 READ 0 1 1 PROGRAM 1 1 0 PROGRAM VERIFY Mode NOTE: "0" means Low level; "1" means High level. 16-3 S3P80E5/P80E7 OTP S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) A14− − A0 t OED D7− − D0 t ACC t OEH OE t OEW 12.5V MODE Figure 16-3. OTP Read Timing Table 16-3. OTP Read Characteristics (TA = 25 °C ± 5 °C, VDD = 5 V ± 5 %, VPP = 12.5 V ± 0.25V) Parameter Symbol Min Typ Max Units Address to Output Delay tACC – – 75 ns OE to Address Delay tOED 0 – – OE Pulse Width tOEW 75 – – Output hold from OE whichever occurs first TOEH 0 – – 16-4 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) S3P80E5/P80E7 OTP PROGRAM PROGRAM VERIFY A14− − A0 D7− − D0 Data In Stable Data Out Valid t DS t OEH MODE t VS t DH PGM t OE t PW t OEW OE Figure 16-4. Program Memory Write Timing Table 16-4. OTP Program/Program Verify Characteristics (TA = 25 °C ± 5 °C, VDD = 5 V ± 5 %, VPP = 12.5 V ± 0.25 V) Parameter Symbol Min Typ Max Units VPP Setup Time tVS – 2 – µs Data Setup Time tDS – 2 – Data Hold Time tDH – 2 – PGM Pulse Width tPW – 300 500 Data Valid from OE tOE 75 – – OE Pulse Width tOEW 75 – – Output Enable to Output Float Delay tOEH 0 – 130 ns 16-5 S3P80E5/P80E7 OTP S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) START Address= First Location VDD =5V, V PP=12.5V x= 0 Program One 1ms Pulse Increment X YES x = 10 NO FAIL Verify Byte Verify 1 Byte Last Address FAIL NO VDD = VPP= 5 V FAIL Compare All Byte PASS Device Failed Device Passed Figure 16-5. OTP Programming Algorithm 16-6 Increment Address S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) S3P80E5/P80E7 OTP Table 16-5. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Symbol Operating Voltage VDD Conditions Min Typ Max Unit f OSC = 8 MHz (Instruction clock = 1.33 MHz) 2.1 – 5.5 V f OSC = 4 MHz (Instruction clock = 0.67 MHz) 2.0 – 5.5 – VDD Input High VIH1 All input pins except VIH2 and VIH3 0.8 VDD voltage VIH2 RESET 0.85 VDD VDD VIH3 XIN VDD – 0.3 VDD VIL1 All input pins except VIL2 and VIL3 VIL2 RESET VIL3 XIN VOH1 VDD = 2.4 V; IOH = – 6 Ma VDD – 0.7 VOH2 VDD = 2.4 V; IOH = – 3 mA VDD – 0.7 VOH3 VDD = 5 V; IOH = – 3 mA VDD – 0.25 Input Low voltage Output High voltage Output High voltage Port 3.1 only; TA = 25 °C Port 3.0 only; TA = 25 °C Port 2.7 only; TA = 25 °C 0 – 0.2 VDD V V 0.4 VDD 0.3 – – V – – V 0.4 0.5 V VDD = 2 V; IOH = – 1 mA Port 2.7 only; TA = 25 °C Output Low voltage Input High leakage current VOH4 VDD = 3.0 V; IOH = – 1 mA All output pins except P3 and P2.7 port; TA = 25 °C VDD – 1 VOL1 VDD = 2.4 V; IOL = 15 mA VOL2 VDD = 2.4 V; IOL = 5 mA 0.4 0.5 VOL3 IOL = 1 mA 0.4 1 ILIH1 VIN = VDD All input pins except XIN and XOUT – 1 ILIH2 VIN = VDD, XIN, and XOUT – Port 3.1 only; TA = 25 °C Port 3.0 only; TA = 25 °C Port 0, 1, and 2; TA = 25 °C – µA 20 16-7 S3P80E5/P80E7 OTP S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) Table 16-5. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Input Low leakage current Symbol Conditions Min Typ Max Unit ILIL1 VIN = 0 V All input pins except XIN, XOUT, and – – –1 µA RESET ILIL2 VIN = 0 V XIN and XOUT Output High leakage current ILOH VOUT = VDD All output pins – – 1 µA Output Low leakage current ILOL VOUT = 0 V All output pins – – –1 µA Pull-up resistors RL1 VIN = 0 V; VDD = 2.4 V 44 55 82 kΩ VDD = 5.5 V 15 21 32 Operating mode VDD = 5 V ± 10 % 8 MHz crystal – 6 11 4 MHz crystal 4.5 9 Idle mode VDD = 5 V ± 10 % 8 MHz crystal 1.8 3.5 4 MHz crystal 1.6 3 Stop mode; VDD = 6.0 V 20 35 VDD = 5.5 V 18 25 VDD = 3.3 V 12 15 VDD = 0.7 V 1.0 1.5 Supply current IDD1 (note) IDD2 IDD3 – 20 TA = 25 °C; Ports 0–3 mA µA NOTE: Supply current does not include the current drawn through internal pull-up resistors or external output current loads. 16-8 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) S3P80E5/P80E7 OTP f OSC (Main oscillation frequency) INSTRUCTION CLOCK 1.33 MHz 8 MHz 1.00 MHz 6 MHz 670 kHz 4 MHz 500 kHz 250 kHz 400 kHz 8.32 kHz 1 2 3 4 2.1 5 6 7 5.5 SUPPLY VOLTAGE (V) INSTRUCTION CL OCK = 1/6n x oscillator frequency (n = 1, 2, 8, 16) Figure 16-6. Operating Voltage Range 16-9