S3C921F/P921F
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
SAM88RCRI PRODUCT FAMILY
Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offer fast and efficient CPU, a wide
range of integrated peripherals, and supports OTP device.
A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a flexible programming
environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating
modes are included to support real-time operations.
S3C921F/P921F MICROCONTROLLER
The S3C921F can be used for dedicated control functions in a variety of applications, and is especially designed
for application with voice synthesizer or etc.
The S3C921F/P921F single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built
around the powerful SAM88RCRI CPU core.
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The S3C921F/P921F has 64 Kbytes of
program ROM and 192 Kbytes of data ROM on-chip (S3C921F), and 720 bytes of RAM including 16 bytes of
working register and 128 bytes of LCD display RAM.
Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core:
— Four configurable I/O ports including ports shared with segment/common drive outputs
— 8-bit programmable pins for external interrupts
— One 8-bit basic timer for oscillation stabilization and watch-dog functions
— One 8-bit and one 16-bit timer/counter with selectable operating modes
— Watch timer for real time
— Two PWM modules for direct speaker drive
OTP
The S3C921F microcontroller is also available in OTP (One Time Programmable) version. S3P921F
microcontroller has an on-chip 256 Kbyte one-time-programmable EPROM instead of masked ROM. The
S3P921F is comparable to S3C921F, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C921F/P921F
FEATURES
CPU
LCD Controller/Driver
•
•
64 segments and 16 common terminals
•
•
8, 12, and 16 common selectable
Internal resistor circuit for LCD bias
SAM88RCRI CPU core
Memory
•
64K × 8 bits program memory(ROM)
•
•
192K × 8 bits data memory(ROM)
592 × 8 bits data memory(RAM)
(Excluding LCD data memory)
Instruction Set
Two PWM Modules
•
5/6/7/8-bits PWM Selectable
•
•
Direct speaker drive
2-bit extendable
•
41 instructions
Voltage Level Detector
•
Idle and Stop instructions added for power-down
modes
•
•
32 I/O Pins
•
I/O: 8 pins
•
I/O: 24 pins(Sharing with segment drive outputs)
Programmable low voltage detector
Two criteria voltage(2.7 V, 4.0 V)
Two Power-Down Modes
•
•
Idle: only CPU clock stops
Stop: selected system clock and CPU clock stop
Interrupts
Oscillation Sources
•
•
•
Crystal, ceramic, or RC for main clock
•
•
Main clock frequency: 0.4 MHz - 8MHz
32.768 kHz crystal oscillation circuit for
sub clock
15 interrupt source and 1 vector
One interrupt level
8-Bit Basic Timer
•
•
Watchdog timer function
3 kinds of clock source
Instruction Execution Times
•
500nS at 8 MHz fx(minimum)
One 8-Bit Timer/Counter 0
•
Programmable interval timer
Operating Voltage Range
•
•
External event counter function
PWM and Capture function
•
2.4 V to 5.5 V at 0.4 - 3MHz
•
2.7 V to 5.5 V at 0.4 - 4MHz
•
4.5 V to 5.5 V at 0.4 - 8MHz
One 16-bit Timer/Counter 1
•
•
One 16-bit Timer/Counter mode
Two 8-bit Timer/Counters A/B mode
Operating Temperature Range
•
-40 °C to +85 °C
Watch Timer
Package Type
•
Interval time: 3.91mS, 0.25S, 0.5S, and 1S
at 32.768 kHz
•
•
2/4/8/16 kHz Selectable buzzer output
1-2
100-pin QFP Package
S3C921F/P921F
PRODUCT OVERVIEW
BLOCK DIAGRAM
RESET
TEST
P4.0/SEG48P4.7/SEG55
P3.0/SEG56P3.7/SEG63
Port 4
Port 3
Basic
Timer
Internal Bus
XIN
RC/X-tal
XOUT
Main
OSC
Port I/O and Interrupt
Control
XTIN
XTOUT
Sub
OSC
Watch
Timer
P1.2/BUZ
Port 2
P2.4/COM12P2.7/COM15
SAM88RCRI CPU
Port 1
P1.3/T0CK
P1.4/T0
P1.6/TA
P1.7/TB
PWM0
PWM1
Timer 0
Timer 1
P1.5/T1CK
P2.0/COM8P2.3/COM11
P1.0/INT
P1.1/INT
P1.2/BUZ/INT
P1.3/T0CK/INT
P1.4/T0/INT
P1.5/T1CK/INT
P1.6/TA/INT
P1.7/TB/INT
Timer A
Timer B
64-Kbyte ROM
VLC1
592-Byte
Register File
LCD Driver/
Controller
PWM
Module
Voltage
Level
Detector
COM0-COM7
COM8/P2.0COM15/P2.7
SEG0-SEG47
SEG48/P4.0SEG55/P4.7
SEG56/P3.0SEG63/P3.7
192-Kbyte
Data
ROM
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C921F/P921F
PIN ASSIGNMENTS
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SEG1
SEG0
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
VLC1
RC/X-tal
PWM0
PWM1
VDD
VSS
XOUT
XIN
TEST
XTIN
XTOUT
RESET
P1.0/INT
P1.1/INT
P1.2/BUZ/INT
P1.3/T0CK/INT
P1.4/T0/INT
P1.5/T1CK/INT
P1.6/TA/INT
P1.7/TB/INT
1
2
3
4
5
6
7
8
9
10
11
12
13 (SDAT)
14 (SCLK)
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
S3C921F
(100-QFP-1420C)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P4.4/SEG52
P4.5/SEG53
P4.6/SEG54
P4.7/SEG55
P3.0/SEG56
P3.1/SEG57
P3.2/SEG58
P3.3/SEG59
P3.4/SEG60
P3.5/SEG61
P3.6/SEG62
P3.7/SEG63
P2.0/COM8
P2.1/COM9
P2.2/COM10
P2.3/COM11
P2.4/COM12
P2.5/COM13
P2.6/COM14
P2.7/COM15
Figure 1-2. Pin Assignment (100 Pin)
1-4
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
P4.0/SEG48
P4.1/SEG49
P4.2/SEG50
P4.3/SEG51
S3C921F/P921F
PRODUCT OVERVIEW
Table 1-1. Pin Descriptions
Pin Names
Pin
Type
Pin Description
Circuit
Number
Pin
Numbers
Share
Pins
P1.0, P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
I/O
I/O port with bit-programmable pins;
Schmitt trigger input or push-pull, opendrain output and software assignable pullups;
Alternately used for external interrupt
input(noise filters, interrupt enable and
pending control).
E-2
23, 24
25
26
27
28
29
30
INT
BUZ/INT
T0CK/INT
T0/INT
T1CK/INT
TA/INT
TB/INT
P2.0 - P2.7
I/O
I/O port with nibble-programmable pins;
Schmitt trigger input or push-pull, opendrain output and software assignable pullups.
H-9
38 - 31
COM8COM15
P3.0 - P3.7
I/O
I/O port with bit-programmable pins;
Schmitt trigger input or push-pull, opendrain output and software assignable pullups.
H-8
46 - 39
SEG56SEG63
P4.0 - P4.7
I/O
I/O port with nibble-programmable pins;
Schmitt trigger input or push-pull output
and software assignable pull-ups.
H-10
54 - 47
SEG48SEG55
PWM0
PWM1
O
PWM output pins.
C
13
14
–
VLC1
I
LCD power supply pin.
–
11
–
INT
I/O
External interrupt input pins.
E-2
23, 24
25
26
27
28
29
30
P1.0, P1.1
P1.2/BUZ
P1.3/T0CK
P1.4/T0
P1.5/T1CK
P1.6/TA
P1.7/TB
BUZ
I/O
Output pin for buzzer signal.
E-2
25
P1.2/INT
T0CK
I/O
Timer 0 clock input.
E-2
26
P1.3/INT
T0
I/O
Capture input or interval/PWM output.
E-2
27
P1.4/INT
T1CK
I/O
Timer 1/A external clock input.
E-2
28
P1.5
TA
I/O
Timer 1/A clock output.
E-2
29
P1.6
TB
I/O
Timer B clock output.
E-2
30
P1.7
COM0-COM7
O
LCD common data outputs.
H-4
10 - 3
–
COM8-COM15
I/O
LCD common data outputs.
H-9
38 - 31
P2.0 - P2.7
SEG0-SEG47
O
LCD segment data outputs.
H-5
2-1
100-55
–
SEG48-SEG55
SEG56-SEG63
I/O
LCD segment data outputs.
H-10
H-8
54 - 47
46 - 39
P4.0 - P4.7
P3.0 - P3.7
1-5
PRODUCT OVERVIEW
S3C921F/P921F
Table 1-1. Pin Descriptions (Continued)
Pin Names
Pin
Type
Pin Description
Circuit
Number
Pin
Numbers
Share
Pins
RESET
I
System reset pin
B
22
–
XTIN,XTOUT
–
Crystal oscillator pins for sub clock.
–
20, 21
–
XIN,XOUT
–
Main oscillator pins.
–
18, 17
–
RC/X-tal
–
Main oscillator type selection pin
("High" for RC osc. and "Low" for X-tal)
–
12
–
TEST
I
Test input: it must be connected to VSS
–
19
–
VDD,VSS
–
Power input pins
–
15, 16
–
1-6
S3C921F/P921F
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD
Pull-Up
Resistor
P-Channel
In
In
N-Channel
Schmitt Trigger
Figure 1-4. Pin Circuit Type B
Figure 1-3. Pin Circuit Type A
VDD
VDD
Pull-Up
Resistor
Pull-Up
Resistor
Enable
P-Channel
Data
Out
Output
Disable
In
P-Channel
N-Channel
Schmitt Trigger
Figure 1-5. Pin Circuit Type A-3
Figure 1-6. Pin Circuit Type C
1-7
PRODUCT OVERVIEW
S3C921F/P921F
VDD
Pull-up
Resistor
VDD
Resistor
Enable
Open-Drain
P-CH
I/O
Data
N-CH
Output
Disable
External
Interrupt
Input
Noise
Filter
Figure 1-7. Pin Circuit Type E-2
VDD
Pull-up
Resistor
Resistor
Enable
Data
Output
Disable
P-Channel
Circuit
Type C
Figure 1-8. Pin Circuit Type E-3
1-8
I/O
S3C921F/P921F
PRODUCT OVERVIEW
VLC1
VLC2
Out
COM Data
VLC5
VSS
Figure 1-9. Pin Circuit Type H-4
VLC1
VLC3
SEG Data
Out
VLC4
VSS
Figure 1-10. Pin Circuit Type H-5
1-9
PRODUCT OVERVIEW
S3C921F/P921F
VLC1
VLC2
COM
Output
Disable
VLC5
VSS
Figure 1-11. Pin Circuit Type H-6
VLC1
VLC3
SEG
Out
Output
Disable
VLC4
VSS
Figure 1-12. Pin Circuit Type H-7
1-10
S3C921F/P921F
PRODUCT OVERVIEW
VDD
Pull-up
Resistor
VDD
Resistor
Enable
Open-Drain
P-CH
I/O
Data
N-CH
Output Disable 1
SEG
Output Disable 2
Circuit
Type H-7
Figure 1-13. Pin Circuit Type H-8
VDD
VDD
Pull-up
Resistor
Resistor
Enable
Open-Drain
P-CH
I/O
Data
N-CH
Output Disable 1
COM
Output Disable 2
Circuit
Type H-6
Figure 1-14. Pin Circuit Type H-9
1-11
PRODUCT OVERVIEW
S3C921F/P921F
VDD
VDD
Pull-up
Resistor
Resistor
Enable
P-CH
I/O
Data
N-CH
Output Disable 1
SEG
Output Disable 2
Circuit
Type H-7
Figure 1-15. Pin Circuit Type H-10
1-12
S3C921F/P921F
17
ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this chapter, S3C921F electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
— Absolute maximum ratings
— D.C. electrical characteristics
— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by an external interrupt
— Stop mode release timing when initiated by a Reset
— I/O capacitance
— A.C. electrical characteristics
— Input timing for external interrupts (port 1)
— Input timing for RESET
— Oscillation characteristics
— Oscillation stabilization time
17-1
ELECTRICAL DATA
S3C921F/P921F
Table 17-1. Absolute Maximum Ratings
(TA = 25°C)
Parameter
Symbol
Conditions
Supply voltage
VDD
–
Input voltage
VIN
Output voltage
Output current
High
Output current
Low
Rating
Unit
– 0.3 to + 6.5
V
Ports 1, 2, 3 and 4
– 0.3 to VDD + 0.3
V
VO
All output pins
– 0.3 to VDD + 0.3
V
I OH
One I/O pin active
– 18
All I/O pins active
– 60
One I/O pin active
+ 30 (Peak Value)
Total pin current for ports 1-4
+ 100 (Peak Value)
I OL
mA
mA
Operating
temperature
TA
–
– 40 to + 85
°C
Storage
temperature
TSTG
–
– 65 to + 150
°C
17-2
S3C921F/P921F
ELECTRICAL DATA
Table 17-2. D.C. Electrical Characteristics
(TA = – 40°C to + 85°C, VDD = 2.4 V to 5.5 V)
Parameter
Symbol
Operating Voltage
VDD
Min
Typ
Max
Unit
fx = 8MHz
(Instruction clock = 2.0MHz)
4.5
–
5.5
V
fx = 4MHz
(Instruction clock = 1.0MHz)
2.7
–
5.5
2.4
–
5.5
VIH1
fx = 3MHz
(Instruction clock = 0.75MHz)
Ports 1-4
0.8 VDD
–
VDD
VIH2
RESET
0.7 VDD
VDD
VIH3
XIN, XOUT and XTIN
VDD – 0.1
VDD
VIL1
Ports 1-4
VIL2
RESET
VIL3
XIN, XOUT and XTIN
Output High
voltage
VOH
Output Low
voltage
VOL
VDD = 4.5 to 5.5 V;
IOH = –1 mA
Ports 1-4
VDD = 4.5 to 5.5 V;
IOL= 10 mA
Ports 1-4
VDD = 2.4 to 5.5 V;
IOL= 1.6 mA
Input High
voltage
Input Low voltage
Input High
leakage current
Input Low
leakage current
Conditions
ILIH1
VI = VDD;
All input pins except those
specified below for ILIH2
ILIH2
VI = VDD;
XIN, XOUT, XTIN
ILIL1
VI = 0 V; All input pins except
–
–
0.2 VDD
V
V
0.2 VDD
0.1
VDD – 1.0
–
–
V
–
–
2.0
V
0.4
–
–
3
µA
20
–
–
–3
RESET, XIN, XOUT, XTIN
ILIL2
VI = 0 V;
XIN, XOUT, XTIN
Output High
leakage current
ILOH
Output Low
leakage current
ILOL
VO = VDD
All output pins
VO = 0 V
All output pins
–20
–
–
3
–
–
–3
17-3
ELECTRICAL DATA
S3C921F/P921F
Table 17-2. D.C. Electrical Characteristics (Continued)
(TA = – 40°C to + 85°C, VDD = 2.4 V to 5.5 V)
Min
Typ
Max
Unit
25
50
75
kΩ
VDD = 3V
50
100
150
VI = 0 V; VDD = 5V; RESET
150
250
350
VDD = 3V
250
500
750
RLCD1
TA = + 25 °C
When LCON.1 = "0"
38
54
70
RLCD2
TA = + 25 °C
When LCON.1 = "1"
19
27
35
Parameter
Symbol
Pull-Up Resistor
RL1
Conditions
VI = 0 V; VDD = 5V
Ports 1-4
RL2
LCD Voltage
Dividing Resistor
VLCD-COMi
Voltage Drop
(i = 0-15)
VDC
–15 uA per common pin
–
–
120
VLCD-SEGx
Voltage Drop
(x = 0–63)
VDS
–15 uA per common pin
–
–
120
Middle Output
VLC2
VDD = 2.4 V to 5.5 V,
1/5 bias
0.8VDD–0.2
0.8VDD
0.8VDD+ 0.2
VLC3
0.6VDD–0.2
0.6VDD
0.6VDD+ 0.2
VLC4
0.4VDD–0.2
0.4VDD
0.4VDD+ 0.2
VLC5
0.2VDD–0.2
0.2VDD
0.2VDD+ 0.2
Voltage (note)
LCD clock = 0Hz,
VLC1 = VDD
NOTE: It is middle output voltage when LCD controller/driver is 1/16 duty and 1/5 bias.
17-4
kΩ
mV
V
S3C921F/P921F
ELECTRICAL DATA
Table 17-2. D.C. Electrical Characteristics (Continued)
(TA = – 40°C to + 85°C, VDD = 2.4 V to 5.5 V)
Parameter
Symbol
Supply current (1)
IDD1(2)
IDD2(2)
Conditions
Min
Typ
Max
Unit
–
5.0
10.0
mA
VDD = 5 V ± 10%
Crystal oscillator
8 MHz
C1 = C2 = 22pF
4.19 MHz
3.0
6.4
VDD = 3 V ± 10%
4.0 MHz
1.4
2.8
Idle mode
VDD = 5 V ± 10%
8 MHz
1.0
2.0
Crystal oscillator
C1 = C2 = 22pF
4.19 MHz
0.8
1.6
VDD = 3 V ± 10%
4 MHz
0.3
0.6
–
IDD3(3)
VDD = 3 V ± 10%,
32 kHz crystal oscillator
–
15
30
IDD4(3)
Idle mode;
VDD = 3 V ± 10%,
32 kHz crystal oscillator
–
6
15
–
0.3
3
0.1
1
IDD5
Stop mode;
VDD=5 V ± 10%,
VDD=3 V ± 10%,
OSCCON.2="1"
µA
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors, PWM, or external output current loads.
2. IDD1 and IDD2 include power consumption for sub clock oscillation.
3. IDD3 and IDD4 are current when main clock oscillation stops and the sub clock is used.
4.
Every values in this table is measured when bits 4-3 of the system clock control register (CLKCON.4-.3) is set to 11B.
17-5
ELECTRICAL DATA
S3C921F/P921F
Table 17-3. Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply
voltage
VDDDR
–
2.2
–
5.5
V
Data retention supply
current
IDDDR
Stop mode,
VDDDR=2.2 V
–
–
1
µA
Oscillator stabilization
wait time
tWAIT
Released by RESET
–
216/fx (1)
–
ms
Released by interrupt
–
(2)
–
NOTES:
1. fx is the main oscillator frequency.
2. The duration of the oscillation stabilization time (tWAIT) when it is released by an interrupt is determined by
the setting in the basic timer control register, BTCON.
Idle Mode
(Basic Timer Active)
~
~
Stop Mode
Normal
Operating Mode
Data Retention Mode
~
~
VDD
VDDDR
Interrupt
Request
Execution of
STOP Instruction
0.8 VDD
tWAIT
Figure 17-1. Stop Mode Release Timing When Initiated by an External Interrupt
17-6
S3C921F/P921F
ELECTRICAL DATA
RESET
Occurs
~
~
Stop Mode
Data Retention Mode
~
~
VDD
VDDDR
Oscillation
Stabilization
TIme
Normal
Operating Mode
tSRL
Execution of
STOP Instrction
RESET
0.7 VDD
0.2 VDD
tWAIT
Figure 17-2. Stop Mode Release Timing When Initiated by a RESET
17-7
ELECTRICAL DATA
S3C921F/P921F
Table 17-4. Input/Output Capacitance
(TA = – 40°C to + 85°C, VDD = 0 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input
capacitance
CIN
f = 1 MHz; unmeasured pins
are connected to VSS
–
–
10
pF
Output
capacitance
COUT
Min
Typ
Max
Unit
I/O capacitance
CIO
Table 17-5. A.C. Electrical Characteristics
(TA = – 40°C to + 85°C)
Parameter
Symbol
Conditions
Interrupt input,
High, Low width
tINTH,
tINTL
P1.0 – P1.7
VDD = 5 V
150
200
–
ns
RESET input Low
width
tRSL
Input
VDD = 5 V
10
–
–
µs
tINTL
tINTH
External
Interrupt
0.8 VDD
0.2 VDD
NOTE:
The unit tCPU means one CPU clock period.
Figure 17-3. Input Timing for External Interrupts (P1.0–P1.7)
tRSL
RESET
0.2 VDD
Figure 17-4. Input Timing for RESET
17-8
S3C921F/P921F
ELECTRICAL DATA
Table 17-6. Main Oscillation Characteristics
(TA = – 40°C + 85°C)
Oscillator
Ceramic
Oscillator
Clock
Configuration
XIN
XOUT
C1
Crystal
Oscillator
XIN
Min
Typ
Max
Units
0.4
–
8.0
MHz
–
–
4
ms
0.4
–
8.0
MHz
ms
Oscillation frequency(1)
RC/X-tal = 0 V
Stabilization time(2)
Stabilization occurs
when VDD is equal to
the minimum
oscillator voltage
range.
XOUT
Oscillation frequency(1)
RC/X-tal = 0 V
Stabilization time(2)
VDD = 4.5 V to 5.5 V
–
–
10
VDD = 1.8 V to 5.5 V
–
–
30
XIN
0.4
–
8.0
MHz
–
62.0
–
1250
ns
VDD = 2.7 V to 5.5 V
RC/X-tal = VDD
–
4
–
MHz
VDD = 2.4 V to 5.5 V
RC/X-tal = VDD
–
2
–
C2
XOUT
XIN input frequency(1)
XIN input high and low
level width (tXH, tXL)
RC
Oscillator
Test Condition
C2
C1
External
Clock
Parameter
XIN
XOUT
Frequency(1)
RC/X-tal = 0 V
R
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
17-9
ELECTRICAL DATA
S3C921F/P921F
1/fx
tXL
tX
XIN
VDD-0.1 V
0.1 V
Figure 17-5. Clock Timing Measurement at XIN
17-10
S3C921F/P921F
ELECTRICAL DATA
Table 17-7. Sub Oscillation Characteristics
(TA = – 40°C + 85°C, VDD = 2.4 V to 5.5 V)
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max
Units
Crystal
Oscillator
XTIN XTOUT
Oscillation frequency(1)
–
32
32.768
35
kHz
VDD = 4.5 V to 5.5 V
–
1.0
2
s
VDD = 2.4 V to 4.5 V
–
–
10
XTIN input frequency(1)
–
32
–
100
kHz
XTIN input high and low
level width (tXTL, tXTH)
–
5
–
15
us
C1
C2
Stabilization time(2)
External
Clock
XTIN XTOUT
NOTES:
1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs .
1/fxt
tXTL
tXTH
XTIN
VDD-0.1 V
0.1 V
Figure 17-6. Clock Timing Measurement at XTIN
17-11
ELECTRICAL DATA
S3C921F/P921F
Table 17-8. PWM0/PWM1 Electrical Characteristics
( TA = – 40 °C + 85 °C)
Parameter
PWM Output
Voltage
Symbol
VPWM0
Conditions
VDD = 2.4 V
Min
IPWMh0 = –8mA
IPWMl0 = 15 mA
VPWM1
VDD = 2.4 V
IPWMh1 = –12mA
IPWMl1 = 20 mA
VPWM2
VDD = 2.4 V
IPWMh2 = –16mA
IPWMl2 = 25 mA
VPWM3
VDD = 2.4 V
IPWMh3 = –20mA
IPWMl3 = 30 mA
VDD – 0.5
Typ
Max
Unit
–
–
V
–
0.5
VDD – 0.5
–
–
0.5
VDD – 0.5
–
–
0.5
VDD – 0.5
–
–
0.5
Table 17-9. VLD Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.4 V to 5.5 V)
Parameter
VLD Voltage
Symbol
VVLD
VLD Circuit Response
Time
TB
VLD Operating Current
IBL
17-12
Conditions
Min
Typ
Max
Unit
BLDCON.4 = 0B
2.4
2.7
3.0
V
BLDCON.4 = 1B
3.7
4.0
4.3
fw = 32.768 kHz
–
–
1.0
mS
–
50
100
uA
S3C921F/P921F
ELECTRICAL DATA
fx
(Main oscillation
frequency)
Clock
2 MHz
8 MHz
1.0 MHz
4 MHz
750 kHz
3 MHz
400 kHz
8.32 kHz
1
2
2.4 2.7
5.5 6
4.5
Supply Voltage (V)
Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)
Figure 17-7. Operating Voltage Range
17-13
S3C921F/P921F
MECHANICAL DATA
18
MECHANICAL DATA
OVERVIEW
The S3C921F microcontroller is currently available in a 100-pin QFP package.
23.90 ± 0.30
0-8
20.00 ± 0.20
+ 0.10
14.00 ± 0.20
0.10 MAX
100-QFP-1420C
0.80 ± 0.20
17.90 ± 0.30
0.15 - 0.05
#100
#1
0.65
0.30
+ 0.10
- 0.05
0.05 MIN
0.15 MAX
(0.58)
2.65 ± 0.10
3.00 MAX
0.80 ± 0.20
NOTE: Dimensions are in millimeters.
Figure 19-1. 100-QFP-1420C Package Dimensions
18-1
S3C921F/P921F
19
S3P921F OTP
S3P921F OTP
OVERVIEW
The S3P921F single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C921F
microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data
format.
The S3P921F is fully compatible with the S3C921F, both in function in D.C. electrical characteristics and in pin
configuration. Because of its simple programming requirements, the S3P921F is ideal as an evaluation chip for
the S3C921F.
19-1
S3P921F OTP
S3C921F/P921F
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SEG1
SEG0
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
VLC1
RC/X-tal
SDAT/PWM0
SCLK/PWM1
VDD/VDD
VSS/VSS
XOUT
XIN
VPP/TEST
XTIN
XTOUT
RESET/RESET
RESET
P1.0/INT
P1.1/INT
P1.2/BUZ/INT
P1.3/T0CK/INT
P1.4/T0/INT
P1.5/T1CK/INT
P1.6/TA/INT
P1.7/TB/INT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
S3P921F
(100-QFP-1420C)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
P4.0/SEG48
P4.1/SEG49
P4.2/SEG50
P4.3/SEG51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P4.4/SEG52
P4.5/SEG53
P4.6/SEG54
P4.7/SEG55
P3.0/SEG56
P3.1/SEG57
P3.2/SEG58
P3.3/SEG59
P3.4/SEG60
P3.5/SEG61
P3.6/SEG62
P3.7/SEG63
P2.0/COM8
P2.1/COM9
P2.2/COM10
P2.3/COM11
P2.4/COM12
P2.5/COM13
P2.6/COM14
P2.7/COM15
Figure 19-1. S3P921F Pin Assignments (100-Pin QFP Package)
19-2
S3C921F/P921F
S3P921F OTP
Table 19-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
PWM0
SDAT
13
I/O
PWM1
SCLK
14
I
Serial clock pin. Input only pin.
TEST
VPP
19
I
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
(Option)
RESET
RESET
22
I
Chip Initialization
VDD/VSS
VDD/VSS
15/16
–
Logic power supply pin. VDD should be tied to
+5 V during programming.
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.
Table 19-2. Comparison of S3P921F and S3C921F Features
Characteristic
S3P921F
S3C921F
Program Memory
64-Kbyte EPROM
64-Kbyte mask ROM
Data Memory
192-Kbyte EPROM
192-Kbyte mask ROM
Operating Voltage (VDD)
2.4 V to 5.5 V
2.4 V to 5.5 V
OTP Programming Mode
VDD = 5 V, VPP (EA) = 12.5 V
Pin Configuration
100 QFP
100 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (EA) pin of the S3P921F, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 21-3 below.
Table 19-3. Operating Mode Selection Criteria
VDD
VPP
(EA)
REG/
MEM
Address
(A17–A0)
R/W
Mode
5V
5V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
19-3
S3P921F OTP
S3C921F/P921F
fx
(Main oscillation
frequency)
Clock
2 MHz
8 MHz
1.0 MHz
4 MHz
750 kHz
3 MHz
400 kHz
8.32 kHz
1
2
2.4 2.7
5.5 6
4.5
Supply Voltage (V)
Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)
Figure 19-2. Operating Voltage Range
19-4