Product Overview Address Spaces Addressing Modes Control Registers Interrupt Structure Instruction Set S3C8625/C8627/C8629/P8629 1 PRODUCT OVERVIEW PRODUCT OVERVIEW SAM8 PRODUCT FAMILY Samsung's SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU with a wide range of integrated peripherals, in various mask-programmable ROM sizes. Analog its major CPU features are: — Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupt — Built-in basic timer with watchdog function The sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to specific interrupt levels. S3C8625/C8627/C8629/P8629 MICROCONTROLLERS S3C8625/C8627/C8629/P8629 single-chip 8-bit microcontrollers are based on the powerful SAM8 CPU architecture. The internal register file is logically expanded to increase the on-chip register space. S3C8625/C8627/C8629/P8629 contain 16/32 K bytes of on-chip program ROM. In line with Samsung's modular design approach, the following peripherals are integrated with the SAM8 core: — Four programmable I/O ports (total 27 pins) — One 8-bit basic timer for oscillation stabilization and watchdog functions — One 8-bit general-purpose timer/counter with selectable clock sources — One 12-bit counter with selectable clock sources, including Hsync or Csync input — One interval timer — PWM block with seven 8-bit PWM circuits — Sync processor block (for Vsync and Hsync I/O, Csync input, and Clamp signal output) — DDC and normal Multi-master IIC-bus — 4-channel A/D converter (8-bit resolution) S3C8625/C8627/C8629/P8629 are a versatile microcontrollers which are ideal for use in multi-sync monitors or in general-purpose applications that require sophisticated timer/counter, PWM, sync signal processing, A/D converter, and multi-master IIC-bus support with DDC. They are available in a 42pin SDIP or a 44-pin QFP package. OTP S3C8625/C8627/C8629 microcontrollers are also available in OTP (One Time Programmable) version named, S3P8629. S3P8629 microcontroller has an on-chip 32-Kbyte one-time-programmable EPROM instead of masked ROM. S3P8629 is comparable to S3C8625/C8627/C8629, both in function and pin configuration except its ROM size. 1-1 PRODUCT OVERVIEW S3C8625/C8627/C8629/P8629 FEATURES CPU Pulse Width Modulator (PWM) • • SAM8 CPU core 8-bit PWM: 7-CH Memory Sync-Processor Block • 16/24/32-Kbyte internal program memory (ROM) • • 464-byte general-purpose register area Vsync-I, Hsync-I, Csync-I input and Vsync-O, Hsync-O, Clamp-O output pins • Pseudo sync signal output Instruction Set • Auto SOG detection • 78 instructions • Auto Hsync polarity detection • IDLE and STOP instructions added for power-down modes Instruction Execution Time • Minimum 500 ns (with 12 MHz CPU clock) Interrupts DDC Multi-Master IIC-Bus 1-Ch • Serial Peripheral Interface • Support for Display Data Channel (DDC1/DDC2B/DDC2Bi/DDC2B+) Normal Multi-Master IIC-Bus 1-Ch • Ten interrupt sources • Ten interrupt vectors • Seven interrupt level A/D Converter • Fast interrupt feature • • Serial Peripheral Interface 4-channel; 8-bit resolution General I/O Oscillator Frequency • • 8 MHz to 12 MHz crystal operation • Internal Max. 12 MHz CPU clock Four I/O Ports (total 27pins) 8-Bit Basic Timer • Programmable timer for oscillation stabilization interval control or watchdog timer function • Three selective internal clock frequencies Timer/Counters • One 8-bit Timer/Counter with several clock sources (Capture mode) • One 12-bit Counter with H-sync and several clock sources • One Interval Timer 1-2 Operating Temperature Range • – 40 °C to + 85 °C Operating Voltage Range • 4.0 V to 5.5 V Package Types • 42-pin SDIP, 44-pin QFP S3C8625/C8627/C8629/P8629 PRODUCT OVERVIEW BLOCK DIAGRAM RESET INT0-INT2 XIN XOUT PWM0 • • • • PWM6 P0.0 −P0.7/INT0 −INT2 P2.0 −P2.7 PORT 0 PORT 2 MAIN OSC VDD , AVREF VSS1, V SS2 TEST INTERNAL BUS PORT 1 P1.0–P1.2 PORT3 P3.0–P3.7 ADC AD0 −AD3 I/O PORT and INTERRUPT CONTROL 8-BIT PWM (7-CH) SAM8 CPU Vsync-I Hsync-I Csync-I Vsync-O Hsync-O Clamp-O SyncProcessor MT0CAP 8-Bit Counter (Timer M0) 16/24/32Kbyte ROM 12-Blt Counter (Timer M1) MT1CK Interval Timer (Timer M2) 464-Byte Register File Multi Master IIC-Bus SCL1 SDA1 Multi Master IIC-Bus and DDC1/2B/2Bi/2B+ SCL0 SDA0 Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C8625/C8627/C8629/P8629 PIN ASSIGNMENTS P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3 P0.4/TM0CAP P0.5/TM1CK P0.6 P0.7 P1.0/SDA1 P1.1/SCL1 VDD VSS1 XOUT XIN TEST SDA0 SCL0 RESET P1.2 P2.0/PWM0 P2.1/PWM1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S3C8625/ C8627/C8629 42-SDIP (Top View) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P3.7 P3.6 P3.5 P3.4 P3.3/AD3 P3.2/AD2 P3.1/AD1 P3.0/AD0 AVREF VSS2 P2.7/Csync-I Hsync-I Vsync-I Vsync-O Hsync-O Clamp-O P2.6/PWM6 P2.5/PWM5 P2.4/PWM4 P2.3/PWM3 P2.2/PWM2 Figure 1-2. S3C8625/C8627/C8629 42-SDIP Pin Assignment 1-4 S3C8625/C8627/C8629/P8629 P0.4/TM0CAP P0.3 P0.2/INT2 P0.1/INT1 P0.0/INT0 N.C. P3.7 P3.6 P3.5 P3.4 P3.3/AD3 44 43 42 41 40 39 38 37 36 35 34 P0.5/TM1CK PRODUCT OVERVIEW 1 33 P3.2/AD2 P0.6 2 32 P3.1/AD1 P0.7 3 31 P3.0 /AD0 P1.0/SDA1 4 30 AVREF P1.1/SCL1 5 29 V SS2 28 P2.7/Csync-I 27 Hsync-I S3C8625/ C8627/C8629 44-QFP (Top View) V DD 6 V SS1 7 XOUT 8 26 Vsync-I XIN 9 25 Vsync-O TEST 10 24 Hsync-O SDA0 11 23 Clamp-O 12 13 14 15 16 17 18 19 20 21 22 SCL0 RESET P1.2 P2.0/PWM0 P2.1/PWM1 N.C. P2.2/PWM2 P2.3/PWM3 P2.4/PWM4 P2.5/PWM5 P2.6/PWM6 Figure 1-3. S3C8627/C8629 44-QFP Pin Assignment 1-5 PRODUCT OVERVIEW S3C8625/C8627/C8629/P8629 PIN DESCRIPTIONS Table 1-1. S3C8625/C8627/C8629/P8629 Pin Descriptions Pin Names Pin Type Pin Description Circuit Type SDIP Pin Numbers Shared Functions General-purpose, 8-bit I/O port. Shared functions include three external interrupt inputs and I/O for timer M0 and M1. Selective configuration of port 0 pins to input or output mode is supported. D-1 D-1 D-1 D-1 D-1 D-1 D-1 D-1 1 2 3 4 5 6 7 8 INT0 INT1 INT2 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 I/O P1.0 P1.1 P1.2 I/O General-purpose, 3-bit I/O port. Selective configuration is available for port 1 pins to input, push-pull output, n-channel opendrain mode, or IIC-bus clock and data I/O. E-1 E-1 E-1 9 10 19 SDA1 SCL1 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 I/O General-purpose, 8-bit I/O port Selective configuration of port 2 pins to input or output mode is supported. The port 2 pin circuits are designed to push-pull PWM output and Csync signal input. D-1 D-1 D-1 D-1 E-1 E-1 E-1 D-1 20 21 22 23 24 25 26 32 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 Csync-I P3.0–P3.3 P3.4–P3.7 I/O General-purpose, 8-bit I/O port Selective configuration port 3 pins to input or output mode is supported. Multiplexed for alternative use as A/D converter inputs AD0–AD3. D-1 E 35–38, 39–42 AD0–AD3 Hsync-I Vsync-I Clamp-O Hsync-O Vsync-O SDA0 SCL0 I I O O O I/O I/O The pins are sync processor signal I/O, IICbus clock, and data I/O. A A A A A G-3 G-3 31 30 27 28 29 16 17 – TM0CAP TM1CK VDD, VSS1, AVREF, VSS2 – Power pins ADC power pins – – 11, 12 34, 33 – XIN, XOUT – System clock I/O pins – 14, 13 – RESET I System reset pin B 18 – TEST I Factory test pin input 0V:Normal operation,5V:Factory test mode – 15 – 1-6 S3C8625/C8627/C8629/P8629 PRODUCT OVERVIEW PIN CIRCUITS VDD VDD Data or Other Function Output Output Data VSS Figure 1-4. Pin Circuit Type A Output Disable VSS Digital Input TTL Input or ADC Input Figure 1-6. Pin Circuit Type D-1 VDD 280 KΩ Noise Filter RESET Figure 1-5. Pin Circuit Type B (RESET RESET) 1-7 PRODUCT OVERVIEW S3C8625/C8627/C8629/P8629 VDD Typical 47-KΩ Pull-up Enable VDD Data Output Open drain Output Disable VSS Input Figure 1-7. Pin Circuit Type E VDD Data Output Open drain Output Disable VSS Input Figure 1-8. Pin Circuit Type E-1 1-8 S3C8625/C8627/C8629/P8629 PRODUCT OVERVIEW Output Data VSS Input Figure 1-9. Pin Circuit Type G-3 1-9 S3C8625/C8627/C8629/P8629 19 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, S3C8625/C8627/C8629 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — Data retention supply voltage in stop mode — Stop mode release timing when initiated by a reset — I/O capacitance — A/D Converter electrical characteristics — A.C. electrical characteristics — Input timing measurement points for P0.0–P0.2, TM0CAP, and TM1CK — Oscillation characteristics — Oscillation stabilization time — Clock timing measurement points for XIN — Schmitt trigger characteristics 19-1 ELECTRICAL DATA S3C8625/C8627/C8629/P8629 Table 19-1. Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbol VDD Input voltage Conditions Rating Unit – – 0.3 to + 6.5 V – 0.3 to + 7.0 V VI1 Type C (n-channel, open-drain) VI2 All port pins except VI1 – 0.3 to VDD + 0.3 Output voltage VO All output pins – 0.3 to VDD + 0.3 Output current High I OH One I/O pin active – 10 All I/O pins active – 60 One I/O pin active + 30 Total pin current except port 3 + 100 Sync-processor I/O pins and IIC-bus clock and data pins + 150 Output current Low I OL V mA mA Operating temperature TA – – 40 to + 85 °C Storage temperature TSTG – – 65 to + 150 °C Table 19-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 4.0 V to 5.5 V) Parameter Input High voltage Input Low voltage Output High voltage 19-2 Symbol Conditions Min Typ Max Unit 0.8 VDD – VDD V VIH1 All input pins except VIH2 and VIH3 VIH2 XIN 2.7 VDD VIH3 TTL input (HsyncI, VsyncI, and CsyncI) 2.0 VDD VIL1 All input pins except VIL2 and VIL3 VIL2 XIN 1.0 VIL3 TTL input (HsyncI, VsyncI, and CsyncI) 0.8 VOH1 IOH = – 8 mA; Port 3 only VOH2 IOH = – 2 mA Ports 0, 2, ClampO, H, and VsyncO VOH3 IOH = – 6 mA; Port 1 – VDD – 1.0 – – 0.2 VDD – V V S3C8625/C8627/C8629/P8629 ELECTRICAL DATA Table 19-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 4.0 V to 5.5 V) Parameter Output Low voltage Input High leakage current Input Low leakage current Symbol Conditions Min Typ Max Unit – – 0.4 V VOL1 IOL = 8 mA; port 3 only VOL2 IOL = 2 mA Port 0, 2, ClampO, H, and VsyncO 0.4 VOL3 IOL = 6 mA Port 1; SCL and SDA 0.6 ILIH1 VIN = VDD All input pins except XIN, XOUT – – 3 ILIH2 VIN = VDD; XOUT only – – 20 ILIH3 VIN = VDD; XIN only 2.5 6 20 ILIL1 VIN = 0 V; All input pins except XIN, – – –3 – – – 20 – 2.5 –6 – 20 µA µA XOUT, and RESET ILIL2 VIN = 0 V; XOUT only ILIL3 VIN = 0 V; XIN only Output High leakage current ILOH1 VOUT = VDD – – 3 µA Output Low leakage current ILOL1 VOUT = 0 V – – –3 µA Pull-up resistor RL1 VIN = 0 V Ports 3.7–3.4 20 47 80 kΩ RL2 VIN = 0 V 150 280 480 – 15 30 RESET only Supply current (note) IDD1 Operation mode; 12 MHz crystal C1 = C2 = 22pF IDD2 Idle mode; 12 MHz crystal C1 = C2 = 22pF 5 10 IDD3 Stop mode 1 10 mA µA NOTE: Supply current does not include drawn internal pull–up resistors and external loads of output. 19-3 ELECTRICAL DATA S3C8625/C8627/C8629/P8629 Table 19-3. Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR Stop mode 2 – 5.5 V Data retention supply current IDDDR Stop mode, VDDDR = 2.0 V – – 5 µA NOTES: 1. During the oscillator stabilization wait time (tWAIT), all CPU operations must be stopped. 2. Supply current does not include drawn through internal pull–up resistors and external output current loads. OSCILLATION STABILIZATION TIME ~ ~ VDD STOP MODE ~ ~ RESET OCCURS DATA RETENTION MODE NORMAL OPERATING MODE VDDDR EXECUTION OF STOP INSTRUCTION RESET t WAIT NOTE: t WAIT is the same as 4,096 x x32 x 1/f OSC. Figure 19-1. Stop Mode Release Timing When Initiated by a Reset Table 19-4. Input/Output Capacitance (TA = –40 °C to + 85 °C, VDD = 0 V) Parameter Symbol Conditions Min Typ Max Unit Input capacitance CIN f = 1 MHz; unmeasured pins are connected to VSS – – 10 pF Output capacitance COUT I/O capacitance 19-4 CIO S3C8625/C8627/C8629/P8629 ELECTRICAL DATA Table 19-5. A/D Converter Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 4.0 V to 5.5 V, VSS = 0 V) Parameter Symbol Conditions Resolution Total accuracy VDD = 5 V Conversion time = 5 µs Min Typ Max Unit – 8 – bit – – ±2 LSB Integral linearity error ILE AVREF = 5 V – ±1 Differential linearity error DLE AVSS = 0 V – ±1 Offset error of top EOT ±1 ±2 Offset error of bottom EOB ± 0.5 ±2 Conversion time (1) tCON 8 bit conversion 34 x n/fOSC (3), n=1,4,8,16 17 – 170 µs Analog input voltage VIAN – AVSS – AVREF V Analog input impedance RAN – 2 1000 – mΩ Analog reference voltage AVREF – 2.5 – VDD V Analog ground AVSS (4) – VSS – VSS V Analog input current IADIN AVREF = VDD = 5V – – 10 µA Analog block Current (2) IADC AVREF = VDD = 5V – 1 3 mA AVREF = VDD = 3V 0.5 1.5 mA AVREF = VDD = 5V When power down mode 100 500 nA NOTES: 1. "Conversion time" is the time required from the moment a conversion operation starts until it ends. 2. IADC is an operating current during the A/D conversion. 3. fOSC is the main oscillator clock. 4. VSS port shaves with the AVSS for S3C8625/C8627/C8629. 19-5 ELECTRICAL DATA S3C8625/C8627/C8629/P8629 Table 19-6. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 4.0 V to 5.5V) Parameter Noise Filter Symbol Conditions Min Typ Max Unit ns tNF1H tNF1L INT0–2, TM0CAP and TM1CK (RC delay) 300 – – tNF2 RESET only (RC delay) 800 – – t NF1L t NF1H t NF2 0.8 V DD 0.2 V DD Figure 19-2. Input Timing Measurement Points for P0.0–P0.2, TM0CAP, and TM1CK 19-6 S3C8625/C8627/C8629/P8629 ELECTRICAL DATA Table 19-7. Oscillation Characteristics (TA = – 40 °C + 85 °C) Oscillator Main crystal or ceramic Clock Circuit Conditions C1 XIN Min Typ Max Unit VDD = 4.0 V to 5.5 V 8 – 12 MHz VDD = 4.0 V to 5.5 V 8 – 12 MHz XOUT C2 External clock (main) XIN XOUT NOTE: The maximum oscillator frequency is 12 MHz. If you use an oscillator frequency higher than 12 MHz, you cannot select a non-divided CPU clock using CLKCON settings. That is, you must select one of the divide-by values. Table 19-8. Oscillation Stabilization Time (TA = – 40 °C + 85 °C, VDD = 4.0 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit ms Crystal VDD = 4.0 V to 5.5 V – – 20 Ceramic VDD = 4.0 V to 5.5V – – 10 External clock XIN input high and low level width (tXH, tXL) 25 – 500 ns NOTE: Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after a power-on occurs, or when Stop mode is released. 1 / fX t XL t XH VDD − 0.5 V XIN 0.4 V Figure 19-3. Clock Timing Measurement Points for XIN 19-7 ELECTRICAL DATA S3C8625/C8627/C8629/P8629 Vout VDD A : 0.2 V DD B : 0.4 V DD C : 0.6 V DD D : 0.8 V DD VSS Vin A B C D Figure 19-4. Schmitt Trigger Characteristics (Normal Port; except TTL Input) 19-8 S3C8625/C8627/C8629/P8629 20 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C8625/C8627/C8629 microcontroller is available in a 42-pin SDIP package (Samsung part number 42SDIP-600) and a 44-QFP package (Samsung part number 44-QFP-1010B). 22 0 ~ 15 ° 15.24 42-SDIP-600 0.50 ± 0.1 1.00 ± 0.1 1.778 5.08MAX (1.77) 3.30 ± 0.3 39.10 ± 0.2 3.50 ± 0.2 21 0.51MIN #1 0.25 +0.1 – 0.0 5 14.00 ± 0.2 42 NOTE: Dimensions are in millimeters. Figure 20-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600) 20-1 MECHANICAL DATA S3C8625/C8627/C8629/P8629 13.20 ± 0.3 0~8° 0.15 +0.10 - 0.05 10.00 ± 0.2 13.20 ± 0.3 0.80 ±0.20 10.00 ± 0.2 44-QFP-1010B 0.10 MAX #44 0.05 MIN 2.05 ± 0.10 #1 0.80 +0.10 0.35 - 0.05 (1.00) 2.30 MAX NOTE: Dimensions are in millimeters. Figure 20-2. 44-Pin QFP Package Mechanical Data (44-QFP-1010B) 20-2 S3C8625/C8627/C8629/P8629 21 KS88P6232 OTP S3P8629 OTP OVERVIEW The S3P8629 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C8625/C8627/C8629 microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P8629 is fully compatible with the S3C8625/C8627/C8629, both in function and in pin configuration. Because of its simple programming requirements, the S3P8629 is ideal for use as an evaluation chip for the S3C8625/C8627/C8629. P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3 P0.4/TM0CAP P0.5/TM1CK P0.6 P0.7 SDAT/P1.0/SDA1 SCLK /P1.1/SCL1 VDD VSS1 XOUT XIN VPP/TEST SDA0 SCL0 RESET/RESET P1.2 P2.0/PWM0 P2.1/PWM1 NOTE: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S3P8629 42-SDIP (Top View) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P3.7 P3.6 P3.5 P3.4 P3.3/AD3 P3.2/AD2 P3.1/AD1 P3.0/AD0 AVREF VSS2 P2.7/Csync-I Hsync-I Vsync-I Vsync-O Hsync-O Clamp-O P2.6/PWM6 P2.5/PWM5 P2.4/PWM4 P2.3/PWM3 P2.2/PWM2 The bolds indicate an OTP pin name. Figure 21-1. S3P8629 Pin Assignments (42-SDIP Package) 21-1 KS88P6232 OTP S3C8625/C8627/C8629/P8629 P0.4/TM0CAP P0.3 P0.2/INT2 P0.1/INT1 P0.0/INT0 N.C. P3.7 P3.6 P3.5 P3.4 P3.3/AD3 44 43 42 41 40 39 38 37 36 35 34 P0.5/TM1CK 1 33 P3.2/AD2 P0.6 2 32 P3.1/AD1 P0.7 3 31 P3.0/AD0 SDAT/P1.0/SDA1 4 30 AVREF SCLK/P1.1/SCL1 5 29 VSS2 VDD 6 28 P2.7/Csync-I VSS1 7 27 Hsync-I XOUT 8 26 Vsync-I XIN 9 25 Vsync-O VPP/TEST 10 24 Hsync-O SDA0 11 23 Clamp-O S3P8629 44-QFP (Top View) 12 13 14 15 16 17 18 19 20 21 22 SCL0 RESET/RESET P1.2 P2.0/PWM0 P2.1/PWM1 N.C. P2.2/PWM2 P2.3/PWM3 P2.4/PWM4 P2.5/PWM5 P2.6/PWM6 NOTE: The bolds indicate an OTP pin name. Figure 21-2. S3P8629 Pin Assignments (44-QFP Package) 21-2 S3C8625/C8627/C8629/P8629 KS88P6232 OTP Table 21-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P1.0 SDAT 9 (4) I/O P1.1 SCLK 10 (5) I Serial clock pin. Input only pin. TEST VPP (TEST) 15 (10) I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) RESET RESET 18 (13) I Chip Initialization VDD/VSS1 VDD/VSS1 11/12 (6/7) I Logic power supply pin. VDD should be tied to +5 V during programming. Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. NOTE: Parentheses indicate 44-QFP OTP pin number. Table 21-2. Comparison of S3P8629 and S3C8625/C8627/C8629 Features Characteristic S3P8629 S3C8625/C8627/C8629 Program Memory 32-Kbyte EPROM 16/24/32-Kbyte mask ROM Operating Voltage (VDD) 4.0 V to 5.5 V 4.0 V to 5.5V OTP Programming Mode VDD = 5 V, VPP (TEST)=12.5V Pin Configuration 42SDIP, 44QFP 42SDIP, 44QFP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3P8629, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-3 below. Table 21-3. Operating Mode Selection Criteria VDD VPP (TEST) REG/ MEM ADDRESS (A15–A0) R/W MODE 5V 5V 0 0000H 1 EPROM read 12.5 V 0 0000H 0 EPROM program 12.5 V 0 0000H 1 EPROM verify 12.5 V 1 0E3FH 0 EPROM read protection NOTE: "0" means Low level; "1" means High level. 21-3 KS88P6232 OTP S3C8625/C8627/C8629/P8629 D.C. ELECTRICAL CHARACTERISTICS Table 21-4. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 4.0 V to 5.5 V) Parameter Symbol Input High leakage current ILIH1 Input Low leakage current Conditions Min Typ Max Unit VIN = VDD All input pins except XIN, XOUT – – 3 µA ILIH2 VIN = VDD; XOUT only – – 20 ILIH3 VIN = VDD; XIN only 2.5 6 20 ILIL1 VIN = 0 V; All input pins except XIN, – – –3 – – – 20 – 2.5 –6 – 20 µA XOUT, and RESET ILIL2 VIN = 0 V; XOUT only ILIL3 VIN = 0 V; XIN only Output High leakage current ILOH1 VOUT = VDD – – 3 µA Output Low leakage current ILOL1 VOUT = 0 V – – –3 µA Pull-up resistor RL1 VIN = 0 V Ports 3.7–3.4 20 47 80 kΩ RL2 VIN = 0 V 150 280 480 – 15 30 RESET only Supply current (note) IDD1 Operation mode; 12 MHz crystal C1 = C2 = 22pF IDD2 Idle mode; 12 MHz crystal C1 = C2 = 22pF 5 10 IDD3 Stop mode 1 10 NOTE: Supply current does not include drawn internal pull–up resistors and external loads of output. 21-4 mA µA