S3C821A/P821A 1 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLES Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are: — Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupt — Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to specific interrupt levels. S3C821A/P821A MICROCONTROLLER The S3C821A/P821A single-chip CMOS microcontroller is fabricated using the highly advanced CMOS process, based on Samsung’s newest CPU architecture. The S3C821A is a microcontroller with a 48-Kbyte mask-programmable ROM embedded. The S3P821A is a microcontroller with a 48-Kbyte one-time-programmable ROM embedded. Using a proven modular design approach, Samsung engineers have successfully developed the S3C821A/P821A by integrating the following peripheral modules with the powerful SAM8 core: — Six programmable I/O ports, including five 8-bit ports and one 7-bit port, for a total of 47 pins. — Twelve bit-programmable pins for external interrupts. — One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset). — One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes. — Watch timer for real time. — 4-input A/D converter — Serial I/O interface The S3C821A/P821A is versatile microcontroller for cordless phone, pager, etc. They are currently available in 80-pin TQFP and 80-pin QFP package. OTP The S3P821A is an OTP (One Time Programmable) version of the S3C821A microcontroller. The S3P821A microcontroller has an on-chip 48-Kbyte one-time-programmable EPROM instead of a masked ROM. The S3P821A is comparable to the S3C821A, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C821A/P821A FEATURES CPU LCD Controller/Driver • • Up to 32 segment pins • 3, 4, and 8 common selectable • Choice of duty cycle • All dots can be switched on/off • Internal resistor circuit for LCD bias SAM8 CPU core Memory • Data memory: 1040-byte of internal register file (Excluding LCD RAM) • Program memory: 48-Kbyte internal program memory (ROM) Serial Port External Interface • • One synchronous SIO 64-Kbyte external data memory area A/D Converter Instruction Execution Time • 8-bit conversion resolution × 4 channel • 750 ns at 8 MHz (minimum, Main oscillator) • 34 µs conversion time (4 MHz CPU clock, fxx/4) • 183 µs at 32,768 Hz (minimum, Sub oscillator) Oscillation Sources Interrupts • Crystal, ceramic, or RC for main system clock • 7 interrupt levels and 19 interrupt sources • Crystal or external oscillator for subsystem clock • 19 vectors • Main system clock frequency: 8 MHz • Fast interrupt processing feature (for one selected interrupt level) • Subsystem clock frequency: 32.768 kHz Power-down Modes I/O Ports • Five 8-bit I/O ports (P0–P4) and one 7-bit I/O port (P5) for a total of 47 bit-programmable pins • Main idle mode (only CPU clock stops) • Sub idle mode • Stop mode (main/sub system oscillation stops) 8-Bit Basic Timer • One programmable 8-bit basic timer (BT) for oscillation stabilization control or watchdog timer (software reset) function Operating Temperature Range • – 40 °C to + 85 °C Operating Voltage Range Watch Timer • Time internal generation: 3.91 ms, 0.5 s at 32,768 Hz • Four frequency outputs to BUZ pin • Clock source generation for LCD • 2.0 V to 5.5 V at 32 kHz (sub clock)-6 MHz (main clock) • 2.2 V to 5.5 V at 8 MHz Package Type • Timers and Timer/Counters • One 8-bit timer/counter (Timer 0) with three operating modes: Interval, Capture, and PWM • One 16-bit timer/counter (Timer 1) with two 8-bit timer/counter modes 1-2 80-pin TQFP, 80-pin QFP S3C821A/P821A PRODUCT OVERVIEW BLOCK DIAGRAM RESET P0.0-P0.7 P1.0-P1.7 P2.0-P2.7 PORT 0 PORT 1 PORT 2 INTERNAL BUS XIN XOUT MAIN OSC PORT 3 P3.0-P3.7 PORT 4 P4.0-P4.7 PORT 5 P5.0-P5.6 I/O PORT and INTERRUPT CONTROL XIN XOUT SUB OSC T1CK TA TB TIMER 1 A and B T0CK T0/T0CAP/ T0PWM TIMER 0 SAM8 CPU 48-KB ROM SCK SI SO 1-KBYTE REGISTER FILE LCD DRIVER SIO AVSS AVREF A/D CONVERTER VDD1 (INTERNAL) VSS 1 (INTERNAL) VDD2 (EXTERNAL) VSS 2 (EXTERNAL) WATCH TIMER COM0-COM3 SEG0-SEG3/ COM4-COM7 SEG4-SEG31 VLC1 BUZ ADC0-ADC3 Figure 1-1. S3C821A Simplified Block Diagram 1-3 PRODUCT OVERVIEW S3C821A/P821A 80 79 78 77 76 75 74 73 72 71 70 69 68 67 65 64 63 62 61 60 P1.0/SEG24/AD0 P0.7/SEG23/A15 P0.6/SEG22/A14 P0.5/SEG21/A13 P0.4/SEG20/A12 P0.3/SEG19/A11 P0.2/SEG18/A10 P0.1/SEG17/A9 P0.0/SEG16/A8 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 PIN ASSIGNMENTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 S3C821A (80-TQFP) P2.5/INT1/T1CK P2.6/INT2/TA P2.7/INT3/TB AVREF P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 AVSS P3.4 P3.5 P3.6 P3.7/T0/T0PWM/T0CAP P4.0/INT4 P4.1/INT5 P4.2/INT6 P4.3/INT7 P4.4/INT8 P4.5/INT9 P4.6/INT10 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P1.1/SEG25/AD1 P1.2/SEG26/AD2 P1.3/SEG27/AD3 P1.4/SEG28/AD4 P1.5/SEG29/AD5 P1.6/SEG30/AD6 P1.7/SEG31/AD7 P2.0/AS P2.1/DR VDD1(INT) VSS1 XOUT XIN TEST XTIN XTOUT RESET P2.2/DW P2.3/DM P2.4/INT0/T0CK Figure 1-2. S3C821A Pin Assignments (80-TQFP-1212) 1-4 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG4 SEG3/COM7 SEG2/COM6 SEG1/COM5 SEG0/COM4 COM3 COM2 COM1 COM0 VDD2 (EXT) VSS2 VLC1 P5.6 P5.5 P5.4 P5.3/BUZ P5.2/SO P5.1/SI P5.0/SCK P4.7/INT11 PRODUCT OVERVIEW 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P0.6/SEG22/A14 P0.5/SEG21/A13 P0.4/SEG20/A12 P0.3/SEG19/A11 P0.2/SEG18/A10 P0.1/SEG17/A9 P0.0/SEG16/A8 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 S3C821A/P821A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 S3C821A (80-QFP) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG6 SEG5 SEG4 SEG3/COM7 SEG2/COM6 SEG1/COM5 SEG0/COM4 COM3 COM2 COM1 COM0 VDD2 (EXT) VSS2 VLC1 P5.6 P5.5 P5.4 P5.3/BUZ P5.2/SO P5.1/SI P5.0/SCK P4.7/INT11 P4.6/INT10 P4.5/INT9 P2.7/INT3/TB AVREF P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 AVSS P3.4 P3.5 P3.6 P3.7/T0/T0PWM/T0CAP P4.0/INT4 P4.1/INT5 P4.2/INT6 P4.3/INT7 P4.4/INT8 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P0.7/SEG23/A15 P1.0/SEG24/AD0 P1.1/SEG25/AD1 P1.2/SEG26/AD2 P1.3/SEG27/AD3 P1.4/SEG28/AD4 P1.5/SEG29/AD5 P1.6/SEG30/AD6 P1.7/SEG31/AD7 P2.0/AS P2.1/DR VDD1(INT) VSS1 XOUT XIN TEST XTIN XTOUT RESET P2.2/DW P2.3/DM P2.4/INT0/T0CK P2.5/INT1/T1CK P2.6/INT2/TA Figure 1-3. S3C821A Pin Assignments (80-QFP-1420C) 1-5 PRODUCT OVERVIEW S3C821A/P821A PIN DESCRIPTIONS Table 1-1. S3C821A Pin Descriptions Pin Names Pin Type Pin Description Circuit Type Pin Numbers (note) Share Pins P0.0–P0.7 I/O 4-bit-programmable I/O port. Pull-up resistors and open-drain outputs are software assignable. Pull-up resistors are automatically disabled for output pins. Configurable as LCD segments/ external interface address and data lines H-32 72–79 (74-80, 1) SEG16/A8 – SEG23/A15 P1.0–1.7 I/O 4-bit-programmable I/O port. Pull-up resistors and open-drain outputs are software assignable. Pull-up resistors are automatically disabled for output pins. Configurable as LCD segments/ external interface address and data lines H-32 80, 1–7 (2-9) SEG24/AD0 – SEG31/AD7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 I/O 1-bit-programmable I/O port. Pull-up resistors are software assignable, and automatically disabled for output pins. P2.0–P2.3 can alternately be used as external interface lines. P2.4–P2.7 are configurable as alternate functions or external interrupts at falling edge with noise filters. D-4 8 (10) 9 (11) 18 (20) 19 (21) 20 (22) 21 (23) 22 (24) 23 (25) AS DR DW DM INT0/T0CK INT1/T1CK INT2/TA INT3/TB P3.0–P3.3 I/O 1-bit-programmable I/O port. Pull-up resistors are software assignable, and automatically disabled for output pins. P3.0–P3.3 can alternately be used as ADC. P3.7 is configurable as an alternate function. F-16 25–28 (27–30) ADC0–ADC3 D-4 30–32 (32–34) D-4 33 (35) P3.4–P3.6 P3.7 T0/T0PWM/ T0CAP P4.0–P4.7 I/O 1-bit-programmable I/O port. Pull-up resistors and open-drain outputs are software assignable. Pull-up resistors are automatically disabled for output pins. P4.0–P4.7 are configurable as external interrupts at a selectable edge with noise filters. E-4 34–41 (36–43) INT4–INT11 P5.0 P5.1 P5.2 P5.3 P5.4–P5.6 I/O 1-bit-programmable I/O port. Pull-up resistors are software assignable, and automatically disabled for output pins. P5.0–P5.3 are configurable as alternate functions. If SCK and SI are used as input, these pins have noise filters. D-4 42 (44) 43 (45) 44 (46) 45 (47) 46–48 (48–50) SCK SI SO BUZ NOTE: Parentheses indicate pin number for 80-QFP package. 1-6 S3C821A/P821A PRODUCT OVERVIEW Table 1-1. S3C821A Pin Descriptions (Continued) Pin Names Pin Type Pin Description Circuit Type Pin Numbers (note) Share Pins VSS1, VDD1 – Power input pins for internal power block – 10, 11 (12, 13) – XOUT, XIN – Main oscillator pins – 12, 13 (14, 15) – TEST – Chip test input pin Hold GND when the device is operating – 14 (16) – XTIN, XTOUT – Sub oscillator pins for sub-system clock – 15, 16 (17,18) – RESET I RESET signal input pin. Schmitt trigger input with internal pull-up resistor. B 17 (19) – INT0–INT3 I/O External interrupts input with noise filter. D-4 20–23 (22–25) P2.4–P2.7 T0CK I/O 8Bit Timer 0 external clock input. D-4 20 (22) P2.4 T1CK I/O Timer 1/A external clock input. D-4 21 (23) P2.5 TA I/O Timer 1/A clock output D-4 22 (24) P2.6 TB I/O Timer B clock output D-4 23 (25) P2.7 T0 I/O Timer 0 clock output D-4 33 (35) P3.7 T0PWM I/O Timer 0 PWM output D-4 33 (35) P3.7 T0CAP I/O Timer 0 capture input D-4 33 (35) P3.7 ADC0–ADC3 I/O Analog input pins for A/D converts module F-16 25–28 (27–30) P3.0–P3.3 AVREF, AVSS – – 24, 29 (26, 31) – INT4–INT11 I/O External interrupts input with noise filter. E-4 34–41 (36–43) P4.0–P4.7 BUZ I/O Buzzer signal output D-4 45 (47) P5.3 SCK, SI, SO I/O Serial clock, serial data input, serial data output D-4 42–44 (44–46) P5.0–P5.2 VLC1 – LCD bias voltage input pins – 49 (51) – VSS2, VDD2 – Power input pins for external power block – 50, 51 (52, 53) – COM0–COM3 O LCD Common signal output H-30 52–55 (54–57) – SEG0–SEG3 (COM4–COM7) O LCD Common or Segment signal output H-31 56–59 (58–61) – SEG4–SEG15 O LCD segment signal output H-29 60–71 (62–73) – A/D converter reference voltage and ground NOTE: Parentheses indicate pin number for 80-QFP package. 1-7 PRODUCT OVERVIEW S3C821A/P821A Table 1-1. S3C821A Pin Descriptions (Continued) Pin Names Pin Type SEG16– SEG23 I/O SEG24– SEG31 Pin Description Circuit Type Pin Numbers Share Pins LCD segment signal output H-32 72–79 (74–80, 1) P0.0–P0.7 I/O LCD segment signal output H-32 80, 1–7 (2–9) P1.0–P1.7 A8–A15 I/O External interface address lines H-32 72–79 (74–80, 1) P0.0–P0.7 AD0–AD7 I/O External interface address/data lines H-32 80, 1–7 (2–9) P1.0–P1.7 AS I/O Address strobe D-4 8 (10) P2.0 DR I/O Data read D-4 9 (11) P2.1 DW I/O Data write D-4 18 (20) P2.2 DM I/O Data memory select D-4 19 (21) P2.3 NOTE: Parentheses indicate pin number for 80-QFP package. 1-8 S3C821A/P821A PRODUCT OVERVIEW PIN CIRCUITS VDD VDD DATA P-CHANNEL OUTPUT INPUT N-CHANNEL OUTPUT DISABLE VSS Figure 1-4. Pin Circuit Type A Figure 1-6. Pin Circuit Type C VDD VDD PULL-UP ENABLE PULL-UP RESISTOR DATA RESET Noise Filter OUTPUT DISABLE CIRCUIT TYPE C I/O SCHMITT TRIGER Figure 1-5. Pin Circuit Type B Figure 1-7. Pin Circuit Type D-4 1-9 PRODUCT OVERVIEW S3C821A/P821A VDD PULL-UP RESISTOR PULL-UP ENABLE VDD OPEN-DRAIN EN I/O DATA OUTPUT DISABLE VSS Figure 1-8. Pin Circuit Type E-4 VDD PULL-UP ENABLE DATA OUTPUT DISABLE CIRCUIT TYPE C ADEN ADSELECT DATA T0 ADC Figure 1-9. Pin Circuit Type F-16 1-10 I/O S3C821A/P821A PRODUCT OVERVIEW VLC1 VLC1 VLC2 VLC3 VLC3 OUTPUT VLC4 VLC4 OUTPUT VLC5 VSS VSS Figure 1-10. Pin Circuit Type H-29 Figure 1-12. Pin Circuit Type H-31 VLC1 VLC2 OUTPUT VLC5 VSS Figure 1-11. Pin Circuit Type H-30 1-11 PRODUCT OVERVIEW S3C821A/P821A VDD PULL-UP RESISTOR V DD PULL-UP ENABLE OPEN-DRAIN EN DATA LCD OUT EN SEG I/O V SS CIRCUIT TYPE H-29 OUTPUT DISABLE Figure 1-13. Pin Circuit Type H-32 1-12 S3C821A/P821A 17 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, S3C821A electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — Data retention supply voltage in Stop mode — Stop mode release timing when initiated by an external interrupt — Stop mode release timing when initiated by a Reset — I/O capacitance — A.C. electrical characteristics — A/D converter electrical characteristics — Input timing for external interrupts (P4, P2.4–P2.7) — Input timing for RESET — Serial data transfer timing — Oscillation characteristics — Oscillation stabilization time — Operating voltage range 17-1 ELECTRICAL DATA S3C821A/P821A Table 17-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Conditions Rating Unit Supply voltage VDD – – 0.3 to + 6.5 V Input voltage VIN – 0.3 to VDD + 0.3 V Output voltage VO – 0.3 to VDD + 0.3 V Output current High I OH One I/O port active – 18 mA All I/O ports active – 60 One I/O port active + 30 (peak value) Output current Low I OL All I/O ports – mA + 15 (note) Ports 0, 1, 2, and 3 + 100 (peak value) + 60 (note) Ports 4 and 5 + 100 (peak value) + 60 (note) Operating temperature Storage temperature TA – – 40 to + 85 °C TSTG – – 65 to + 150 °C NOTE: The values for Output Current Low (IOL) are calculated as Peak Value × 17-2 Duty . S3C821A/P821A ELECTRICAL DATA Table 17-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Symbol Operating Voltage VDD Conditions Min Typ Max Unit f OSC = 8 MHz (Instruction clock = 1.33 MHz) 2.2 – 5.5 V f OSC = 6 MHz (Instruction clock = 1 MHz) 2.0 – VDD V VIH1 P0 and P1 0.7 VDD VIH2 RESET, P2, P3, P4, and P5 0.8 VDD VDD VIH3 XIN, XTIN VDD – 0.1 VDD VIL1 P0 and P1 VIL2 RESET, P2, P3, P4, and P5 VIL3 XIN, XTIN Output High voltage VOH VDD = 3 V; IOH = – 200 µA All output pins Output Low voltage VOL Input High leakage current Input High voltage Input Low voltage 0 – 0.3 VDD 0.2 VDD 0.1 VDD – 1.0 – – VDD = 3 V; IOL= 1 mA All output pins – 0.4 1.0 ILIH1 VIN = VDD All input pins except those specified below for ILIH2 – – 1 ILIH2 VIN = VDD XIN, XOUT, XTIN, and XTOUT ILIL1 VIN = 0 V All input pins except those specified below for ILIL2 and RESET ILIL2 VIN = 0 V XIN, XOUT, XTIN, and XTOUT Output High leakage current ILOH VOUT = VDD All output pins – – 1 Output Low leakage current ILOL VOUT = 0 V All output pins – – –1 |VDD–COMi| voltage drop (i = 0–7) VDC VDD = 2.7 V to 5.5 V – 15 µA per common pin – – 120 |VDD–SEGx| voltage drop (x = 0–31) VDS VLCD = 2.7 V to 5.5 V – 15 µA per segment pin – – 120 Input Low leakage current µA 20 – – –1 – 20 mV 17-3 ELECTRICAL DATA S3C821A/P821A Table 17-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter VLC2 output voltage Symbol VLC2 Conditions VDD = 2.7 V to 5.5 V LCD clock = 0 Hz VLC1 = VDD VLC3 output voltage VLC3 VLC4 output voltage VLC4 VLC5 output voltage VLC5 Pull-up resistors RL1 VIN = 0 V; TA = 25 °C VDD = 3.0 ± 10 %; Ports 0–5 RL2 VIN = 0 V; TA = 25 °C VDD = 3.0 ± 10 % Typ 0.8 VDD 80 Max 0.8 VDD + 0.15 0.6 VDD + 0.15 0.4 VDD + 0.15 0.2 VDD + 0.15 200 200 450 800 45 65 80 kΩ – 6.0 12 mA 0.6 VDD 0.4 VDD 0.2 VDD LCD voltage dividing resistor RLCD RESET only VLCD = 2.7 V to 5.5 V TA = 25 °C Supply current IDD1 Run mode; VDD=5.0V±10% 6.0 MHz Crystal oscillator C1 = C2 = 22 pF 4.19 MHz 4.5 9.0 VDD = 3.0 V ± 10 % 6.0 MHz 2.9 5.8 4.19 MHz 2.0 4.0 Idle mode; VDD=5.0 V± 0 % 6.0 MHz 1.3 2.6 Crystal oscillator C1 = C2 = 22 pF 4.19 MHz 1.2 2.4 VDD = 3.0 V ± 10 % 6.0 MHz 0.6 1.2 4.19 MHz 0.4 0.8 (note) IDD2 Unit Min 0.8 VDD – 0.15 0.6 VDD – 0.15 0.4 VDD – 0.15 0.2 VDD – 0.15 30 IDD3 Run mode; VDD = 3.0 V ± 10 % 32 kHz crystal oscillator 20 40 IDD4 Idle mode; VDD = 3.0 V ± 10 % 32 kHz crystal oscillator 7 14 IDD5 Stop mode; VDD = 5.0 V ± 10 % 0.5 3 Stop mode; VDD = 3.0 V ± 10 % 0.3 2 V kΩ µA NOTES: 1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and ADC. 2. IDD1 and IDD2 include power consumption for subsystem clock oscillation. 3. IDD3 and IDD4 are current when main system clock oscillation stops and the subsystem clock is used. 4. IDD5 is current when main system clock and subsystem clock oscillation stops. 17-4 S3C821A/P821A ELECTRICAL DATA Table 17-3. Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR – 2.2 – 3.4 V Data retention supply current IDDDR VDDDR = 1.0 V Stop mode – – 1 µA Oscillator stabilization wait time tWAIT Released by RESET Released by interrupt – 216/fx (1) – ms – (2) – NOTES: 1. fx is the main oscillator frequency. 2. The duration of the oscillation stabilization time (tWAIT) when it is released by an interrupt is determined by the setting in the basic timer control register, BTCON. ~ ~ IDLE MODE (Basic Timer active) STOP MODE NORMAL OPERATING MODE ~ ~ DATA RETENTION MODE VDD V DDDR EXECUTION OF STOP INSTRUCTION 0.8 V DD Interrupt Request t WAIT Figure 17-1. Stop Mode Release Timing When Initiated by an External Interrupt 17-5 ELECTRICAL DATA S3C821A/P821A ~ ~ RESET OCCURS OSCILLATION STABILIZATION TIME STOP MODE NORMAL OPERATING MODE ~ ~ DATA RETENTION MODE VDD VDDDR EXECUTION OF STOP INSTRUCTION RESET 0.2 V DD 0.8 VDD t WAIT Figure 17-2. Stop Mode Release Timing When Initiated by a RESET 17-6 S3C821A/P821A ELECTRICAL DATA Table 17-4. Input/output Capacitance (TA = – 25 °C, VDD = 0 V) Parameter Symbol Conditions Min Typ Max Unit Input capacitance CIN f = 1 MHz; unmeasured pins are connected to VSS – – 10 pF Output capacitance COUT Min Typ Max Unit External SCK source 1,000 – – ns Internal SCK source 1,000 External SCK source 500 Internal SCK source tKCY/2–50 External SCK source 250 Internal SCK source 250 External SCK source 400 Internal SCK source 400 External SCK source – – 300 ns I/O capacitance CIO Table 17-5. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter SCK cycle time SCK high, low width Symbol tKCY tKH, tKL SI setup time to SCK high tSIK SI hold time to SCK high tKSI Output delay for SCK to SO tKSO Interrupt input, high, low width RESET input low width Conditions Internal SCK source tINTH, tINTL tRSL All interrupt VDD = 3 V Input VDD = 3 V 250 500 700 – 2,000 – – ns 17-7 ELECTRICAL DATA S3C821A/P821A Table 17-6. A/D Converter Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Symbol Conditions Resolution VDD = 5.12 V Total accuracy Min Typ Max Unit – 8 – bit – – ±2 LSB 17 – 170 µs AVREF = 5.12 V AVSS = 0 V Conversion time (1) tCON Analog input voltage VIAN – AVSS – AVREF V Analog input impedance RAN – 2 1,000 – MΩ Analog reference voltage AVREF – 2.5 – VDD V Analog ground AVSS – VSS – VSS + 0.3 V Analog input current IADIN – – 10 µA 8 bit conversion 34 x n/fxx (2), n=1,4,8,16 AVREF = VDD = 5V NOTES: 1. "Conversion time" is the time required from the moment a conversion operation starts until it ends. 2. fxx is a selected system clock for peripheral hardware. 17-8 S3C821A/P821A ELECTRICAL DATA t INTL t INTH 0.8 V DD 0.2 V DD NOTE: The unit t CPU means one CPU clock period. Figure 17-3. Input Timing for External Interrupts t RSL RESET 0.2 V DD Figure 17-4. Input Timing for RESET t KCY t KL t KH 0.8 V DD 0.2 V DD SCK t SIK t KSI INPUT DATA SI 0.8 V DD 0.2 V DD t KSO SO OUTPUT DATA Figure 17-5. Serial Data Transfer Timing 17-9 ELECTRICAL DATA S3C821A/P821A Table 17-7. Main System Oscillation Characteristics (TA = – 40 °C + 85 °C) Oscillator Clock Circuit Crystal C1 XIN C1 XIN Min Typ Max Unit 2.2 V–5.5 V 0.4 – 8 MHz 2.0 V–5.5 V 0.4 – 6 Main oscillation frequency 2.2 V–5.5 V 0.4 – 8 2.0 V–5.5 V 0.4 – 6 2.2 V–5.5 V 0.4 – 8 2.0 V–5.5 V 0.4 – 6 3.0 V 0.4 – 2 XOUT C2 External clock Main oscillation frequency Condition (VDD) XOUT C2 Ceramic Parameter XIN XIN input frequency XOUT RC Frequency XIN R XOUT Table 17-8. Subsystem Oscillation Characteristics (TA = – 40 °C + 85 °C) Oscillator Crystal Clock Circuit C1 XTIN C2 Min Typ Max Unit Sub oscillation frequency 2.0 V–5.5 V 32 32.768 35 kHz XTIN input frequency 2.0 V–5.5 V 32 – 500 kHz XTOUT External clock XTIN XTOUT 17-10 Condition (VDD) Parameter S3C821A/P821A ELECTRICAL DATA Table 17-9. Main Oscillation Stabilization Time (TA = – 40 °C + 85 °C, VDD = 2.0 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit Crystal fx > 400 kHz – – 20 ms Ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. – – 10 ms External clock XIN input High and Low width (tXH, tXL) 25 – 500 ns 1/fx t XL t XH XIN VDD – 0.1 V 0.1 V Figure 17-6. Clock Timing Measurement at XIN Table 17-10. Sub Oscillation Stabilization Time (TA = – 40 °C + 85 °C, VDD = 2.0 V to 5.5 V) Oscillator Crystal External clock Test Condition Min Typ Max Unit – – – 10 s 1 – 18 µs XTIN input High and Low width (tXH, tXL) 1 / f xt t XTL t XTH XTIN VDD – 0.1 V 0.1 V Figure 17-7. Clock Timing Measurement at XTIN 17-11 ELECTRICAL DATA S3C821A/P821A INSTRUCTION CLOCK f x(Main oscillation frequency) 1.33 MHz 8 MHz 1.00 MHz 6 MHz 8.33 kHz 400 kHz 1 2 2.2 3 4 5 6 7 5.5 SUPPLY VOLTAGE (V) INSTRUCTION CLOCK = 1/6n x oscillator frequency (n = 1, 2, 8, 16) Figure 17-8. Operating Voltage Range 17-12 S3C821A/P821A MECHANICAL DATA 18 MECHANICAL DATA OVERVIEW The S3C821A microcontroller is currently available in 80-pin QFP and TQFP package. 23.90 ± 0.3 0−8° 20.00 ± 0.2 14.00 ± 0.2 +0.10 - 0.05 0.10 MAX 80-QFP-1420C 0.80 ± 0.20 17.90 ± 0.3 0.15 (1.00) #80 #1 0.80 0.35 ± 0.1 ± 0.15 MAX (0.80) 0.05 MIN 2.65 ± 0.10 3.00 MAX 0.80 ± 0.20 NOTE: Dimensions are in millimeters. Figure 18-1. 80-Pin QFP Package Demensions 18-1 MECHANICAL DATA S3C821A/P821A 14.00BSC 0− 7° 12.00BSC 0.60 ± 0.15 12.00BSC 14.00BSC 0.09−0.20 80-TQFP-1212 0.05-0.15 #80 1.00 ± 0.05 1.20 MAX #1 0.50 0.17−0.27 (1.25) ± 0.08 MAX M NOTE: Dimensions are in millimeters. Figure 18-2. 80-Pin TQFP Package Demensions 18-2 S3C821A/P821A 20 S3P821A OTP S3P821A OTP OVERVIEW The S3P821A single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C821A microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data format. The S3P821A is fully compatible with the S3C821A, both in function and in pin configuration. Because of its simple programming requirements, the S3P821A is ideal as an evaluation chip for the S3C821A. 20-1 S3C821A/P821A 80 79 78 77 76 75 74 73 72 71 70 69 68 67 65 64 63 62 61 60 P1.0/SEG24/AD0 P0.7/SEG23/A15 P0.6/SEG22/A14 P0.5/SEG21/A13 P0.4/SEG20/A12 P0.3/SEG19/A11 P0.2/SEG18/A10 P0.1/SEG17/A9 P0.0/SEG16/A8 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 S3P821A OTP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 S3P821A (80-TQFP) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P2.5/INT1/T1CK P2.6/INT2/TA P2.7/INT3/TB AVREF P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 AVSS P3.4 P3.5 P3.6 P3.7/T0/T0PWM/T0CAP P4.0/INT4 P4.1/INT5 P4.2/INT6 P4.3/INT7 P4.4/INT8 P4.5/INT9 P4.6/INT10 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P1.1/SEG25/AD1 P1.2/SEG26/AD2 P1.3/SEG27/AD3 P1.4/SEG28/AD4 P1.5/SEG29/AD5 P1.6/SEG30/AD6 P1.7/SEG31/AD7 SDAT/P2.0/AS SCLK/P2.1/DR VDD1/VDD1 VSS1/VSS1 XOUT XIN VPP/TEST XTIN XTOUT RESET/RESET P2.2/DW P2.3/DM P2.4/INT0/T0CK Figure 20-1. S3P821A Pin Assignments (80-TQFP-1212 Package) 20-2 SEG4 SEG3/COM7 SEG2/COM6 SEG1/COM5 SEG0/COM4 COM3 COM2 COM1 COM0 VDD2 (EXT) VSS2 VLC1 P5.6 P5.5 P5.4 P5.3/BUZ P5.2/SO P5.1/SI P5.0/SCK P4.7/INT11 S3P821A OTP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P0.6/SEG22/A14 P0.5/SEG21/A13 P0.4/SEG20/A12 P0.3/SEG19/A11 P0.2/SEG18/A10 P0.1/SEG17/A9 P0.0/SEG16/A8 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 S3C821A/P821A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 S3P821A (80-QFP) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG6 SEG5 SEG4 SEG3/COM7 SEG2/COM6 SEG1/COM5 SEG0/COM4 COM3 COM2 COM1 COM0 VDD2 (EXT) VSS2 VLC1 P5.6 P5.5 P5.4 P5.3/BUZ P5.2/SO P5.1/SI P5.0/SCK P4.7/INT11 P4.6/INT10 P4.5/INT9 P2.7/INT3/TB AVREF P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 AVSS P3.4 P3.5 P3.6 P3.7/T0/T0PWM/T0CAP P4.0/INT4 P4.1/INT5 P4.2/INT6 P4.3/INT7 P4.4/INT8 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P0.7/SEG23/A15 P1.0/SEG24/AD0 P1.1/SEG25/AD1 P1.2/SEG26/AD2 P1.3/SEG27/AD3 P1.4/SEG28/AD4 P1.5/SEG29/AD5 P1.6/SEG30/AD6 P1.7/SEG31/AD7 SDAT/P2.0/AS SCLK/P2.1/DR VDD1/VDD1 VSS1/VSS1 XOUT XIN VPP/TEST XTIN XTOUT RESET/RESET RESET P2.2/DW P2.3/DM P2.4/INT0/T0CK P2.5/INT1/T1CK P2.6/INT2/TA Figure 20-2. S3P821A Pin Assignments (80-QFP-1420C Package) 20-3 S3P821A OTP S3C821A/P821A Table 20-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P2.0 SDAT 8 (10) I/O Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. P2.1 SCLK 9 (11) I/O Serial clock pin. Input only pin. VPP TEST 14 (16) I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) RESET RESET 17 (19) I Chip Initialization VDD1/VSS1 VDD1/VSS1 10 (12)/11 (13) – Logic power supply pin. VDD should be tied to + 5 V during programming. NOTE: ( ) means 80 QFP package. Table 20-2. Comparison of S3P821A and S3C821A Features Characteristic S3P821A S3C821A Program Memory 48-K byte EPROM 48-K byte mask ROM Operating Voltage (VDD) 2.0 V to 5.5 V 2.0 V to 5.5 V OTP Programming Mode VDD = 5 V, VPP (TEST) = 12.5 V Pin Configuration 80 QFP/80 TQFP 80 QFP/80 TQFP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the S3P821A, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 20-3 below. Table 20-3. Operating Mode Selection Criteria VDD 5V REG/ MEM ADDRESS (TEST) VPP 5V 0 0000H 1 EPROM read 12.5 V 0 0000H 0 EPROM program 12.5 V 0 0000H 1 EPROM verify 12.5 V 1 0E3FH 0 EPROM read protection NOTE: "0" means Low level; "1" means High level. 20-4 R/W MODE (A15–A0) S3C821A/P821A S3P821A OTP Table 20-4. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Symbol Operating Voltage VDD Min Typ Max Unit f OSC = 8 MHz (Instruction clock = 1.33 MHz) 2.2 – 5.5 V 2.0 VIH1 f OSC = 6 MHz (Instruction clock = 1 MHz) P0 and P1 0.7 VDD – VDD V VIH2 RESET, P2, P3, P4, and P5 0.8 VDD VDD VIH3 XIN, XTIN VDD – 0.1 VDD VIL1 P0 and P1 VIL2 RESET, P2, P3, P4, and P5 VIL3 XIN, XTIN Output High voltage VOH Output Low voltage VOL Input High leakage current ILIH1 VDD = 3 V; IOH = – 200 µA All output pins VDD = 3 V; IOL= 1 mA All output pins VIN = VDD All input pins except those specified below for ILIH2 Input High voltage Input Low voltage Conditions ILIH2 VIN = VDD XIN, XOUT, XTIN, and XTOUT ILIL1 VIN = 0 V All input pins except those specified below for ILIL2 and RESET ILIL2 VIN = 0 V XIN, XOUT, XTIN, and XTOUT Output High leakage current ILOH Output Low leakage current ILOL |VDD–COMi| voltage drop (i = 0-7) VDC VOUT = VDD All output pins VOUT = 0 V All output pins VDD = 2.7 V to 5.5 V – 15 µA per common pin |VDD–SEGx| voltage drop (x = 0-31) VDS Input Low leakage current VLCD = 2.7 V to 5.5 V – 15 µA per segment pin 0 – 0.3 VDD 0.2 VDD 0.1 VDD – 1.0 – – – 0.4 1.0 – – 1 µA 20 – – –1 – 20 – – 1 – – –1 – – 120 – – 120 mV 20-5 S3P821A OTP S3C821A/P821A Table 20-4. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Symbol Conditions VLC2 output voltage VLC2 VLC3 output voltage VLC3 VLC4 output voltage VLC4 VLC5 output voltage VLC5 Pull-up resistors RL1 VIN = 0 V; TA = 25°C VDD = 3.0 ± 10%; Ports 0–5 RL2 VIN = 0 V; TA = 25 °C VDD = 3.0 ± 10 % LCD voltage dividing resistor RLCD Supply current IDD1 (note) IDD2 VDD = 2.7 V to 5.5 V LCD clock = 0 Hz VLC1 = VDD RESET only VLCD = 2.7 V to 5.5 V TA = 25 °C 6.0 MHz Min Typ Max Unit 0.8 VDD – 0.15 0.6 VDD – 0.15 0.4 VDD – 0.15 0.2 VDD – 0.15 30 0.8 VDD V 80 0.8 VDD + 0.15 0.6 VDD + 0.15 0.4 VDD + 0.15 0.2 VDD + 0.15 200 300 500 800 45 65 80 kΩ – 6.0 12 mA 0.6 VDD 0.4 VDD 0.2 VDD Run mode; VDD=5.0V±10% Crystal oscillator C1 = C2 = 22 pF 4.19 MHz 4.5 9.0 VDD = 3.0 V ± 10 % 6.0 MHz 2.9 5.8 4.19 MHz 2.0 4.0 Idle mode; VDD=5.0 V± 0% 6.0 MHz 1.3 2.6 Crystal oscillator C1 = C2 = 22 pF 4.19 MHz 1.2 2.4 VDD = 3.0 V ± 10 % 6.0 MHz 0.6 1.2 4.19 MHz 0.4 0.8 IDD3 Run mode; VDD = 3.0 V ± 10 % 32 kHz crystal oscillator 20 40 IDD4 Idle mode; VDD = 3.0 V ± 10 % 32 kHz crystal oscillator 7 14 IDD5 Stop mode; VDD = 5.0 V ± 10 % 0.5 3 Stop mode; VDD = 3.0 V ± 10 % 0.3 2 kΩ µA NOTES: 1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and ADC. 2. IDD1 and IDD2 include power consumption for subsystem clock oscillation. 3. IDD3 and IDD4 are current when main system clock oscillation stops and the subsystem clock is used. 4. IDD5 is current when main system clock and subsystem clock oscillation stops. 20-6 S3C821A/P821A S3P821A OTP INSTRUCTION CLOCK f x(Main oscillation frequency) 1.33 MHz 8 MHz 1.00 MHz 6 MHz 8.33 kHz 400 kHz 1 2 2.2 3 4 5 6 7 5.5 SUPPLY VOLTAGE (V) INSTRUCTION CLOCK = 1/6n x oscillator frequency (n = 1, 2, 8, 16) Figure 20-3. Operating Voltage Range 20-7