KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW 1 PRODUCT OVERVIEW OVERVIEW The KS57C5204/C5208/C5304/C5308/C5312 single-chip CMOS microcontroller has been designed for highperformance using SAM 47 (Samsung Arrangeable Microcontrollers). SAM 47, Samsung's newest 4-bit CPU core is notable for its low energy consumption and low operating voltage. You can select from three ROM sizes: 4K, 8K, or 12K bytes. Except for the difference in ROM size, the features and functions of the KS57C5204 and the KS57C5208 are identical and the KS57C5304, KS57C5308, and the KS57C5312 are identical. With it's DTMF generator, watchdog timer function, and versatile 8-bit timer/counters, the KS57C5204/C5208 /C5304/C5308/C5312 offers an excellent design solution for a wide variety of telecommunication applications. Up to 35 pins of the available 42-pin SDIP or 44-pin QFP package for the KS57C5204/C5208, and up to 23 pins of the available 30-pin SDIP or 32-pin SOP package for the KS57C5304/C5308/C5312 can be assign to I/O. Six vectored interrupts for KS57C5204/C5208 and four vectored interrupts for KS57C5304/C5308/C5312 provide fast response to internal and external events. In addition, the KS57C5204/C5208/C5304/C5308/C5312's advanced CMOS technology provides for low power consumption and a wide operating voltage range. OTP The KS57C5204/C5208 microcontroller is also available in OTP (One Time Programmable) version, KS57P5208. The KS57C5304/C5308/C5312 microcontroller is also available in OTP (One Time Programmable) version, KS57P5308/P5312. The KS57P5208/P5308/P5312 microcontroller has an on-chip 8K-byte (P5208/P5308) or 12K-byte (P5312) one-time-programable EPROM instead of masked ROM. The KS57P5208 is comparable to KS57C5204/C5208, both in function and in pin configuration. Also, the KS57P5308/P5312 is comparable to the KS57C5304/C5308/C5312, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 FEATURES format Memory • 768 × 4-bit RAM 4,096 × 8-bit ROM (KS57C5204/C5304) 8,192 × 8-bit ROM (KS57C5208/C5308) 12,288 × 8-bit ROM (KS57C5312) I/O Pins Interrupts • 3 external interrupt vectors (KS57C5204/C5208) 1 external interrupt vectors (KS57C5304/C5308/C5312) • 3 internal interrupt vectors • Input only: 4 pins (KS57C5204/C5208) 1 pins (KS57C5304/C5308/C5312) • 2 quasi-interrupts • I/O: 35 pins (KS57C5204/C5208) 23 pins (KS57C5304/C5308/C5312) Power-Down Modes • • Idle: Only CPU clock stops N-channel open-drain I/O: 8 pins • Stop: System clock stops Memory-Mapped I/O Structure • Data memory bank 15 DTMF Generator • 16 dual-tone frequencies for tone dialing Oscillation Sources • Crystal, or ceramic for main system clock • Main system clock frequency: 0.4–6.0 MHz (typical) • CPU clock divider circuit (by 4, 8, or 64) 8-Bit Basic Timer • Programmable interval timer • Watchdog timer Two 8-Bit Timer/Counters • Programmable 8-bit timer • External event counter function • Arbitrary clock frequency output Watch Timer Instruction Execution Times • 0.95, 1.91, and 15.3 µs at 4.19 MHz • 1.12, 2.23, 17.88 µs at 3.58 MHz • 0.67, 1.33, 10.7 µs at 6.0 MHz Operating Temperature • – 40 °C to 85 °C Operating Voltage Range • Real-time and time interval generation • • Four frequency outputs to the BUZ pin Package Types Bit Sequential Carrier • 1-2 Supports 16-bit serial data transfer in arbitrary 1.8 V to 5.5 V • 42 SDIP, 44 QFP (KS57C5204/C5208) • 30 SDIP, 32 SOP (KS57C5304/C5308/C5312) KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW BLOCK DIAGRAM INT0, INT1, INT2, INT4 8-Bit Timer/ Counter 0 8-Bit Timer/ Counter 1 P6.0-P6.3/ KS0-KS3 I/O Port 6 P7.0-P7.3/ KS4-KS7 I/O Port 7 P8.0 - P8.3 I/O Port 8 P9.0 - P9.2 I/O Port 9 RESET XIN XOUT Watchdog Timer Interrupt Control Block Clock Stack Pointer Program Counter Internal Interrupts Instruction Decoder Arithmetic and Logic Unit Basic Timer Watch Timer Input Port 1 Program Status Word I/O Port 2 Flags I/O Port 3 I/O Port 4 768x4-Bit Data Memory NOTE: Program Memory KS57C5204/C5304: 4KBytes KS57C5208/C5308: 8KBytes KS57C5312: 12KBytes P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO1 P2.2/CLO P2.3/BUZ P3.0/TCL0 P3.1/TCL1 P3.2 P3.3 P4.0/BTCO P4.1-4.3 I/O Port 5 P5.0-P5.3 DTMF Generator DTMF KS57C5304/C5308/C5312 does not use P1.1/INT1, P1.2/INT2, P1.3/INT4, P3.2, P3.3, INT1, INT2, INT4, P8.0-P8.3, and P9.0-P9.2. Figure 1-1. KS57C5204/C5208/C5304/C5308/C5312 Simplified Block Diagram 1-3 PRODUCT OVERVIEW KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 PIN ASSIGNMENTS RESET P3.2 P3.3 P4.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 KS57C5204/C5208 (42-SDIP-600) P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO1 P2.2/CLO P2.3/BUZ P3.0/TCL0 P3.1/TCL1 VDD VSS XOUT XIN TEST P4.0/BTCO P4.1 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P9.2 P9.1 P9.0 DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1 P5.0 P8.3 P8.2 P8.1 P8.0 P4.3 Figure 1-2. KS57C5204/C5208 Pin Assignment Diagram (42-SDIP) 1-4 33 32 31 30 29 28 27 26 25 24 23 P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW KS57C5204 /C5208 (44-QFP-1010B) 1 2 3 4 5 6 7 8 9 10 11 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 P5.0 P8.3 P8.2 P8.1 P8.0 P4.3 NC P4.2 P3.3 P3.2 RESET P2.2/CLO P2.3/BUZ P3.0/TCL0 P3.1/TCL1 VDD VSS XOUT XIN TEST P4.0/BTCO P4.1 DTMF P9.0 P9.1 P9.2 NC P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO1 Figure 1-3. KS57C5204/C5208 Pin Assignment Diagram (44-QFP) 1-5 PRODUCT OVERVIEW KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 RESET P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P6.0/KS0 P6.1/KS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 KS57C5304/C5308/C5312 (30-SDIP-400) VSS XOUT XIN TEST P4.0/BTCO P4.1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD P3.1/TCL1 P3.0/TCL0 P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P1.0/INT0 DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 Figure 1-4. KS57C5304/C5308/C5312 Pin Assignment Diagram (30-SDIP) RESET P4.2 NC P4.3 P5.0 P5.1 P5.2 P5.3 P6.0/KS0 P6.1/KS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 KS57C5304/C5308/C5312 (32-SOP-450A) VSS XOUT XIN TEST P4.0/BTCO P4.1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD P3.1/TCL1 P3.0/TCL0 P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P1.0/INT0 NC DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 Figure 1-5. KS57C5304/C5308/C5312 Pin Assignment Diagram (32-SOP) 1-6 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. KS57C5204/C5208 Pin Descriptions Pin Name Pin Reset Type Value Description Pin Number Share Pin Circuit Type P1.0 P1.1 P1.2 P1.3 I I 4-bit input port. 1-bit and 4-bit read and test is possible. Each pull-up resistors are assignable by software. 1 (39) 2 (40) 3 (41) 4 (42) INT0 INT1 INT2 INT4 A-4 P2.0 P2.1 P2.2 P2.3 I/O I 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 5 (43) 6 (44) 7 (1) 8 (2) TCLO0 TCLO1 CLO BUZ D-2 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. Ports 2 and 3 can be paired to enable 8-bit data transfer. 9 (3) 10 (4) 19 (13) 20 (14) TCL0 TCL1 D-4 4-bit I/O ports. 1-bit and 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. N-channel open-drain or push-pull output can be selected by software (1-bit unit) Ports 4 and 5 can be paired to support 8-bit data transfer. 16 (10) 17 (11) 21 (15) 22 (17) BTCO E-2 D-4 P3.0 P3.1 P3.2 P3.3 P4.0 P4.1 P4.2 P4.3 I/O I P5.0-P5.3 P6.0-P6.3 I/O I P7.0-P7.3 P8.0-P8.3 P9.0-P9.2 I/O I 27-30 (22-25) 4-bit I/O ports. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. Ports 6 and 7 can be paired to enable 8-bit data transfer. 31-34 (26-29) 35-38 (30-33) KS0-KS3 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. Ports 8 and 9 can be paired to enable 8-bit data transfer. 23-26 (18-21) 40-42 (35-37) – KS4-KS7 D-2 1-7 PRODUCT OVERVIEW KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Table 1-1. KS57C5204/C5208 Pin Descriptions (Continued) Pin Name Pin Reset Type Value Description Pin Number Share Pin Circu it Type DTMF O – DTMF output. 39 (34) – G-6 BTCO I/O I Basic timer clock output 16 (10) P4.0 E-2 INT0 INT1 I I External interrupts. The triggering edge for INT0 and INT1 is selectable. 1 (39) 2 (40) P1.0 P1.1 A-4 INT2 I I Quasi-interrupt with detection of rising edges 3 (41) P1.2 A-4 INT4 I I External interrupt with detection of rising and falling edges. 4 (42) P1.3 A-4 TCLO0 I/O I Timer/counter 0 clock output 5 (43) P2.0 D-2 TCLO1 I/O I Timer/counter 1 clock output 6 (44) P2.1 D-2 CLO I/O I Clock output 7 (1) P2.2 D-2 BUZ I/O I 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the watch timer clock frequency of 4.19 MHz for buzzer sound 8 (2) P2.3 D-2 TCL0 I/O I External clock input for timer/counter 0 9 (3) P3.0 D-4 TCL1 I/O I External clock input for timer/counter 1 10 (4) P3.1 D-4 KS0-KS3 I/O I Quasi-interrupt inputs with falling edge detection 31-34 (26-29) 35-38 (30-33) P6.0-P6.3 P7.0-P7.3 D-4 VDD – – Power supply 11 (5) – – VSS – – Ground 12 (6) – – RESET – – RESET 18 (12) – B XIN XOUT – – Crystal, or ceramic oscillator signal for main system clock. (For external clock input, use XIN and input XIN's reverse phase to XOUT) 14 (8) 13 (7) – – TEST – – Chip test input pin, Hold GND when the device is operating. 15 (9) – – NC – – No connection (16, 38) – – KS4-KS7 signal NOTE: Parentheses indicate pin number for 44 QFP package. 1-8 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW Table 1-2. KS57C5304/C5308/C5312 Pin Descriptions Pin Name Pin Type P1.0 I P2.0 P2.1 P2.2 P2.3 I/O P3.0 P3.1 Description Pin Number Share Pin Circuit Type 1-bit input port. 1-bit and 4-bit read and test is possible. Each bit pull-up resistors are assignable. 23 (25) INT0 A-4 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. Each individual pin can be assignable as input or output. 4-bit pull-up resisters are software assignable to input pins and are automatically disabled for output pins. Ports 2 and 3 can be paired to enable 8-bit data transfer. 24 (26) 25 (27) 26 (28) 27 (29) TCLO0 TCLO1 CLO BUZ D-2 28 (30) 29 (31) TCL0 TCL1 D-4 P4.0 P4.1 P4.2 P4.3 P5.0-P5.3 I/O 4-bit I/O ports. 1-bit and 4-bit read/write and test is possible. Each individual pin can be assignable as input or output. 4-bit pull-up resisters are software assignable to input pins and are automatically disabled for output pins. The N-channel open-drain or push-pull output can be selected by software (1-bit unit). Ports 4 and 5 can be paired to enable 8-bit data transfer. 5 (5) 6 (6) 8 (8) 9 (10) 10-13 (11-14) BTCO E-2 P6.0-P6.3 I/O 4-bit I/O ports. 1-bit and 4-bit read/write and test is possible. Each individual pin can be assignable as input or output. 4-bit pull-up resisters are software assignable to input pins and are automatically disabled for output pins. Ports 6 and 7 can be paired to enable 8-bit data transfer. 14-17 (15-18) 18-21 (19-22) KS0-KS3 D-4 P7.0-P7.3 KS4-KS7 1-9 PRODUCT OVERVIEW KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Table 1-2. KS57C5304/C5308/C5312 Pin Descriptions (Continued) Pin Name I/O Type Description Pin Number Share Pin Circuit Type DTMF O DTMF output. 22 (23) – G-6 INT0 I External interrupt input. The triggering edge for INT0 is selectable. 23 (25) P1.0 A-3 TCLO0 I/O Timer/counter 0 clock output 24 (26) P2.0 D-2 TCLO1 I/O Timer/counter 1 clock output 25 (27) P2.1 D-2 CLO I/O Clock output 26 (28) P2.2 D-2 BUZ I/O 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the watch timer clock frequency of 4.19 MHz for buzzer sound 27 (29) P2.3 D-2 TCL0 I/O External clock input for timer/counter 0 28 (30) P3.0 D-4 TCL1 I/O External clock input for timer/counter 1 29 (31) P3.1 D-4 BTCO I/O Basic timer clock output 5 (5) P4.0 E-2 30 (32) – – VDD – Power supply VSS – Ground 1 (1) – – XIN XOUT – Crystal, or ceramic oscillator signal for main system clock. (For external clock input, use XIN and input XIN's reverse phase to XOUT) 3 (3) 2 (2) – – NC – No connection (9, 24) – – TEST – Chip test input pin, Hold GND when the device is operating. 4 (4) – – RESET KS0-KS3 – I/O RESET signal Quasi-interrupt inputs with falling edge detection KS4-KS7 NOTE: Parentheses indicate the pin number for 32-SOP package. 1-10 7 (7) – B 14-17 (15-18) 18-21 (19-22) P6.0-P6.3 P7.0-P7.3 D-4 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD VDD Pull-Up Resistor P-Channel In In N-Channel Schmitt Trigger Figure 1-8. Pin Circuit Type B Figure 1-6. Pin Circuit Type A VDD VDD Pull-Up Resistor Resistor Enable P-Channel In Data P-Channel Out Output DIsable N-Channel Schmitt Trigger Figure 1-7. Pin Circuit Type A-4 Figure 1-9. Pin Circuit Type C 1-11 PRODUCT OVERVIEW KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 VDD VDD Pull-up Resistor Pull-up Enable Data Output DIsable PNE VDD Pull-up Resistor P-Channel Circuit Type C Data P-Channel Output Disable N-Channel I/O Figure 1-10. Pin Circuit Type D-2 Pull-up Resistor Enable I/O Figure 1-12. Pin Circuit Type E-2 VDD Pull-up Resistor Pull-up Enable Data Output Disable P-Channel Circuit Type C DTMF Out I/O Output Disable Schmitt Trigger Figure 1-11. Pin Circuit Type D-4 1-12 Figure 1-13. Pin Circuit Type G-6 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 13 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, information on KS57C5204/C5208/C5304/C5308/C5312 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics — Absolute maximum ratings — D.C. electrical characteristics — System clock oscillator characteristics — I/O capacitance — A.C. electrical characteristics — Operating voltage range Miscellaneous Timing Waveforms — A.C timing measurement point — Clock timing measurement at XIN and XOUT — TCL timing — Input timing for RESET — Input timing for external interrupts Stop Mode Characteristics and Timing Waveforms — RAM data retention supply voltage in stop mode — Stop mode release timing when initiated by RESET — Stop mode release timing when initiated by an interrupt request 13-1 ELECTRICAL DATA KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Table 13-1. Absolute Maximum Ratings (TA = 25 °C) Symbol Conditions Supply Voltage Parameter VDD – Input Voltage VI1 Output Voltage VO Output Current High I OH Output Current Low I OL Rating All I/O ports – Units – 0.3 to + 6.5 V – 0.3 to VDD + 0.3 V – 0.3 to VDD + 0.3 V One I/O port active – 15 All I/O ports active – 35 One I/O port active + 30 (Peak value) + 15 All I/O ports active mA mA (note) + 100 (Peak value) + 60 (note) Operating Temperature TA – – 40 to + 85 °C Storage Temperature Tstg – – 65 to + 150 °C NOTE: The values for output current low ( IOL ) are calculated as peak value × Duty . Table 13-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Input high voltage Input low voltage 13-2 Symbol Conditions Min Typ Max Units – VDD V VIH1 All input pins except those specified below for VIH2 – VIH3 0.7 VDD VIH2 Ports 1, 3, 6, 7, and RESET 0.8 VDD VDD VIH3 XIN and XOUT VDD – 0.1 VDD VIL1 All input pins except those specified below for VIL2–VIL3 VIL2 Ports 1, 3, 6, 7, and RESET VIL3 XIN and XOUT – – 0.3 VDD 0.2 VDD 0.1 V KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 ELECTRICAL DATA Table 13-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Units VDD – 1.0 – – V V Output high voltage VOH IOH = – 1 mA Ports except 1 Output low voltage VOL1 VDD = 4.5 V to 5.5 V IOL = 15 mA, Ports 4 and 5 only – – 2 VDD = 1.8 to 5.5 V, IOL = 1.6mA – – 0.4 VDD = 4.5 V to 5.5 V IOL= 4 mA, all out ports except 4,5 – – 2 VDD = 1.8 to 5.5 V, IOL = 1.6mA – – 0.4 ILIH1 VI = VDD All input pins except those specified below – – 3 ILIH2 VI = VDD XIN and XOUT ILIL1 VI = 0 V All input pins except below and RESET ILIL2 VI = 0 V XIN and XOUT only Output high leakage current ILOH VO = VDD All out pins – – 3 µA Output low leakage current ILOL VO = 0 V All out pins – – –3 µA Pull-up resistor RL1 VDD = 5 V; VI = 0 V except RESET 25 47 100 kΩ VDD = 3 V 50 95 200 VDD = 5 V; VI = 0 V; RESET 100 220 400 VDD = 3 V 200 450 800 VOL2 Input high leakage current Input low leakage current RL2 V µA 20 – – –3 µA – 20 13-3 ELECTRICAL DATA KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Table 13-2. D.C. Electrical Characteristics (Concluded) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Supply current (1) Symbol IDD1 (DTMF on) Conditions Run mode; VDD = 5 V ± 10% (2) 3.58 MHz crystal oscillator, C1 = C2 = 22 pF Min Typ Max Units – 2.5 5.0 mA 1.4 3.0 2.5 8.0 VDD = 3 V ± 10% IDD2 (DTMF off) IDD3 IDD4 Run mode; VDD = 5 V ± 10% 6.0 MHz crystal oscillator, C1 = C2 = 22 pF 3.58 MHz 1.6 4.0 VDD = 3 V ± 10% 6.0 MHz 1.2 4.0 3.58 MHz 0.7 2.3 0.7 2.5 – Idle mode; = VDD = 5 V ± 10% 6.0 MHz crystal oscillator, C1 = C2 = 22 pF 3.58 MHz 0.6 1.8 VDD = 3 V ± 10% 6.0 MHz 0.3 1.5 3.58 MHz 0.2 1.0 0.01 3 0.01 2 Stop mode; VDD = 5 V ± 10% – – Stop mode; VDD = 3 V ± 10% mA mA µA Row tone level VROW VDD = 2.0 V to 5.5 V RL = 12 kΩ, Temp = – 30 °C to 60 °C Ratio of column to row tone dBCR VDD = 2.0 V to 5.5 V RL = 12 kΩ, Temp = – 30 °C to 60 °C 1 2 3 dB Distortion (Dual tone) THD VDD = 2.0 V to 5.5 V 1MHz band; RL= 12 kΩ – – 5 % – 16.0 – 14.0 – 11.0 Temp = – 30 °C to 60 °C NOTES: 1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up registers. 2. For D.C. electrical values, the power control register (PCON) must be set to 0011B. 13-4 dBV KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 ELECTRICAL DATA Table 13-3. Main System Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration XIN XOUT C1 Crystal Oscillator XIN Test Condition Min Typ Max Units Oscillation frequency (1) VDD = 2.7 V to 5.5 V 0.4 – 6.0 MHz VDD = 1.8 V to 5.5 V 0.4 – 3 – – 4 ms MHz C2 XOUT C1 Parameter Stabilization time (2) VDD = 3 V Oscillation frequency (1) VDD = 2.7 V to 5.5 V 0.4 – 6.0 VDD = 1.8 V to 5.5 V 0.4 – 3 – – 10 ms VDD = 2.7 V to 5.5 V 0.4 – 6.0 MHz VDD = 1.8 V to 5.5 V 0.4 – 3 – 83.3 – 1250 C2 Stabilization time (2) External Clock XIN XOUT XIN input frequency (1) XIN input high and low level width (tXH, tXL) VDD = 3 V ns NOTES: 1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated. 13-5 ELECTRICAL DATA KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Table 13-4. Recommended Oscillator Constants (TA = – 40 °C to + 85 °C) Manufacturer TDK Series Number (1) Frequency Range Load Cap (pF) Oscillator Voltage Range (V) C1 C2 MIN MAX Remarks M5 3.58 MHz-6.0 MHz 33 33 2.0 5.5 Leaded Type FCR MC5 3.58 MHz-6.0 MHz (2) (2) 2.0 5.5 On-chip C Leaded Type CCR MC3 3.58 MHz-6.0 MHz (3) (3) 2.0 5.5 On-chip C SMD Type FCR NOTES: 1. Please specify normal oscillator frequency. 2. On-chip C: 30pF built in. 3. On-chip C: 38pF built in. Table 13-5. Input/Output Capacitance (TA = 25 °C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance 13-6 Symbol Condition Min Typ Max Units CIN f = 1 MHz; Unmeasured pins are returned to VSS – – 15 pF COUT – – 15 pF CIO – – 15 pF KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 ELECTRICAL DATA Table 13-6. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time TCL0, TCL1 Input Frequency Symbol tCY fTI0, fTI1 Conditions Min Typ Max Units VDD = 2.7 V to 5.5 V 0.67 – 64 µs VDD = 1.8 V to 5.5 V 1.33 VDD = 2.7 V to 5.5 V 0 – 1.5 MHz 1 MHz – – µs VDD = 1.8 V to 5.5V TCL0, TCL1 Input High, Low Width Interrupt Input High, Low Width RESET Input Low tTIH0, tTIL0 tTIH1, tTIL1 VDD = 2.7 V to 5.5 V 0.48 VDD = 1.8 V to 5.5 V 1.8 tINTH, tINTL INT0, INT1, INT2, INT4, KS0-KS7 10 – – µs tRSL Input 10 – – µs Width 13-7 ELECTRICAL DATA KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Main Oscillator Frequency (Divided by 4) CPU Clock 1.5 MHz 6 MHz 0.75 MHz 3 MHz 15.625 kHz 1 2 1.8 3 4 5 6 7 2.7 Supply Voltage (V) CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64) Figure 13-1. Standard Operating Voltage Range Table 13-7. RAM Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Symbol Data retention supply voltage VDDDR Data retention supply current IDDDR Release signal set time tSREL Oscillator stabilization wait time (1) tWAIT Conditions Min Typ Max Unit – 1.8 – 5.5 V VDDDR = 1.8 V – Released by RESET Released by interrupt – 0.1 10 µA 0 – – µs – 17 – ms 2 /fx (2) NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time. 13-8 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 ELECTRICAL DATA TIMING WAVEFORMS Internal RESET Operation ~ ~ Idle Mode Stop Mode Operating Mode Data Retention Mode ~ ~ VDD VDDDR Execution of STOP Instruction RESET tWAIT tSREL Figure 13-2. Stop Mode Release Timing When Initiated by RESET Idle Mode ~ ~ Normal Operating Mode Stop Mode Data Retention ~ ~ VDD VDDDR Execution of STOP Instruction tSREL tWAIT Power-down Mode Terminating Signal (Interrupt Request) Figure 13-3. Stop Mode Release Timing When Initiated by Interrupt Request 13-9 ELECTRICAL DATA KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Timing Waveforms (continued) 0.8 VDD 0.8 VDD Measurement Points 0.2 VDD 0.2 VDD Figure 13-4. A.C. Timing Measurement Points (Except for XIN) 1/fx tXL tXH XIN VDD - 0.1 V 0.1 V Figure 13-5. Clock Timing Measurement at XIN 1/fTI tTIL tTIH TCL 0.8 VDD 0.2 VDD Figure 13-6. TCL Timing 13-10 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 ELECTRICAL DATA tRSL RESET 0.2 VDD Figure 13-7. Input Timing for RESET Signal tINTL INT0, 1, 2, 4, KS0 to KS7 tINTH 0.8 VDD 0.2 VDD Figure 13-8. Input Timing for External Interrupts and Quasi-Interrupts 13-11 ELECTRICAL DATA KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 NOTES 13-12 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312MECHANICAL DATA 14 MECHANICAL DATA OVERVIEW The KS57C5204/C5208 microcontroller are available in a 42-pin SDIP package (42-SDIP-600), and a 44-pin QFP package (44-QFP-1010B). The KS57C5304/C5308/C5312 microcontrollers are available in a 30-pin SDIP package (30-SDIP-400) and a 32-pin SOP package (32-SOP-450A). #22 0.2 5 42-SDIP-600 +0 - 0 .1 .05 0-15 15.24 14.00 ± 0.2 #42 (1.77) NOTE : 1.00 ± 0.1 5.08 MAX 39.10 ± 0.2 0.1 3.30 ± 0.3 0.2 39.50 MAX 0.50 ± 3.50 ± #21 0.51 MIN #1 1.778 Dimensions are in millimeters. Figure 14-1. 42-SDIP-600 Package Dimensions 14-1 MECHANICAL DATA KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 13.20 ± 0.3 0-8 10.00 ± 0.2 10.00 ± 0.2 + 0.10 - 0.05 0.10 MAX 44-QFP-1010B 0.80 ± 0.20 13.20 ± 0.3 0.15 #44 #1 + 0.10 0.35 - 0.05 0.80 0.05 MIN (1.00) 2.05 ± 0.10 2.30 MAX NOTE : Dimensions are in millimeters. Figure 14-2. 44-QFP-1010B Package Dimensions 14-2 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312MECHANICAL DATA #16 0.2 5 30-SDIP-400 +0 - 0 .1 .05 0-15 10.16 8.94 ± 0.2 #30 NOTE : 0.56 ± 0.1 1.12 ± 0.1 5.08 MAX (1.77) ± 0.2 3.30 ± 0.3 0.2 27.88 MAX 27.48 3.81 ± #15 0.51 MIN #1 1.778 Dimensions are in millimeters. Figure 14-3. 30-SDIP-400 Package Dimensions 14-3 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 0-8 MECHANICAL DATA 2.00 ± 0.2 #16 19.90 ± 0.2 (0.43) NOTE: 0.40 ± 0.1 1.27 0.05 MIN #1 Dimensions are in millimeters Figure 14-4. 32-SOP-450A Package Dimensions 14-4 0.20 + 0.1 - 0.05 0.78 ± 0.2 32-SOP-450A 11.43 8.34 ± 0.2 #17 2.40 MAX 12.00 ± 0.3 #32 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 15 KS57P5208/P5308/P5312 OTP KS57P5208/P5308/P5312 OTP OVERVIEW The KS57P5208/P5308/P5312 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the KS57C5204/C5208/C5304/C5308/C5312 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a serial data format. The KS57P5208/P5308/P5312 is fully compatible with the KS57C5208/C5308/C5312, both in function and in pin configuration. Because of its simple programming requirements, the KS57P5208/P5308/P5312 is ideal for use as an evaluation chip for the KS57C5208/C5308/C5312. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 KS57P5208 (42-SDIP-600) P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO1 P2.2/CLO P2.3/BUZ SDAT /P3.0/TCL0 SCLK /P3.1/TCL1 VDD/VDD VSS/VSS XOUT XIN VPP/TEST P4.0/BTCO P4.1 RESET/RESET P3.2 P3.3 P4.2 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P9.2 P9.1 P9.0 DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1 P5.0 P8.3 P8.2 P8.1 P8.0 P4.3 Figure 15-1. KS57P5208 Pin Assignment Diagram (42-SDIP) 15-1 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 33 32 31 30 29 28 27 26 25 24 23 P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1 KS57P5208/P5308/P5312 OTP KS57P5208 (44-QFP-1010B) 1 2 3 4 5 6 7 8 9 10 11 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 P5.0 P8.3 P8.2 P8.1 P8.0 P4.3 NC P4.2 P3.3 P3.2 RESET/RESET P2.2/CLO P2.3/BUZ SDAT/P3.0/TCL0 SCLK/P3.1/TCL1 VDD/VDD VSS/VSS XOUT XIN VPP/TEST P4.0/BTCO P4.1 DTMF P9.0 P9.1 P9.2 NC P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO1 Figure 15-2. KS57P5208 Pin Assignment Diagram (44-QFP) 15-2 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 RESET/RESET P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P6.0/KS0 P6.1/KS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 KS57P5308/P5312 (30-SDIP-400) VSS/VSS XOUT XIN VPP/TEST P4.0/BTCO P4.1 KS57P5208/P5308/P5312 OTP 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD/VDD P3.1/TCL1/SCLK P3.0/TCL0/SDAT P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P1.0/INT0 DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 Figure 15-3. KS57P5308/P5312 Pin Assignment Diagram (30-SDIP) RESET/RESET P4.2 NC P4.3 P5.0 P5.1 P5.2 P5.3 P6.0/KS0 P6.1/KS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 KS57P5308/P5312 (32-SOP-450A) VSS/VSS XOUT XIN VPP/TEST P4.0/BTCO P4.1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD/VDD P3.1/TCL1/SCLK P3.0/TCL0/SDAT P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P1.0/INT0 NC DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 Figure 15-4. KS57P5308/P5312 Pin Assignment Diagram (32-SOP) 15-3 KS57P5208/P5308/P5312 OTP KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Table 15-1. KS57P5208 Pin Descriptions Used to Read/Write the EPROM Main Chip Pin Name During Programming Pin Name Pin No. I/O Function P3.0 SDAT 9 (3) I/O Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input / push-pull output port. P3.1 SCLK 10 (4) I/O Serial clock pin. Input only pin. TEST VPP (TEST) 15 (9) I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Hold GND when OPT is operating. RESET RESET 18 (12) I Chip initialization VDD / VSS VDD / VSS 11/12 (5/6) I Logic power supply pin. VDD should be tied to +5 V during programming. NOTE: Parentheses indicate pin numbers of 44 QFP package. Table 15-2. KS57P5308/P5312 Pin Descriptions Used to Read/Write the EPROM Main Chip Pin Name During Programming Pin Name Pin No. I/O Function P3.0 SDAT 28 (30) I/O Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input / push-pull output port. P3.1 SCLK 29 (31) I/O Serial clock pin. Input only pin. TEST VPP (TEST) 4 (4) I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Hold GND when OPT is operating. RESET RESET 7 (7) I Chip initialization VDD / VSS VDD / VSS 30/1 (32/1) I Logic power supply pin. VDD should be tied to +5 V during programming. NOTE: Parentheses indicate pin numbers of 32 SDIP package. 15-4 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 KS57P5208/P5308/P5312 OTP Table 15-3. Comparison of KS57P5208 and KS57C5208 Features Characteristic KS57P5208 KS57C5208 Program Memory 8 K byte EPROM 8 K byte mask ROM Operating Voltage (VDD) 1.8 V (3 MHz) to 5.5 V 1.8 V (3 MHz) to 5.5 V OTP Programming Mode VDD = 5 V, VPP (TEST) = 12.5 V Pin Configuration 42 SDIP / 44 QFP 42 SDIP / 44 QFP EPROM Programmability User Program 1 time Programmed at the factory – Table 15-4. Comparison of KS57P5308/P5312 and KS57C5308/C5312 Features Characteristic KS57P5308/P5312 KS57C5308/C5312 Program Memory 8 K byte EPROM / 12 K (P5312) 8 K byte mask ROM / 12 K (C5312) Operating Voltage (VDD) 1.8 V (3 MHz) to 5.5 V 1.8 V (3 MHz) to 5.5 V OTP Programming Mode VDD = 5 V, VPP (TEST) = 12.5 V Pin Configuration 30 SOP / 32 SOP 30 SOP / 32 SOP EPROM Programmability User Program 1 time Programmed at the factory – OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the Vpp(TEST) pin of the KS57P5208/P5308/P5312, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 15-3 below. Table 15-5. Operating Mode Selection Criteria VDD 5V Vpp (TEST) REG/ Address (A15-A0) R/W MEM Mode 5V 0 0000H 1 EPROM read 12.5V 0 0000H 0 EPROM program 12.5V 0 0000H 1 EPROM verify 12.5V 1 0E3FH 0 EPROM read protection NOTE: "0" means Low level; "1" means High level. 15-5 KS57P5208/P5308/P5312 OTP KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 OTP ELECTRICAL DATA Table 15-6. Absolute Maximum Ratings (TA = 25 °C) Symbol Conditions Supply Voltage Parameter VDD – Input Voltage VI1 Output Voltage VO Output Current High I OH Output Current Low I OL Rating All I/O ports – V – 0.3 to VDD + 0.3 V – 0.3 to VDD + 0.3 V One I/O port active – 15 All I/O ports active – 35 One I/O port active + 30 (Peak value) + 15 All I/O ports active Units – 0.3 to + 6.5 mA mA (note) + 100 (Peak value) + 60 (note) Operating Temperature TA – – 40 to + 85 °C Storage Temperature Tstg – – 65 to + 150 °C NOTE: The values for output current low ( IOL ) are calculated as peak value × Duty . Table 15-7. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Input high voltage Input low voltage 15-6 Symbol Conditions Min Typ Max Units – VDD V VIH1 All input pins except those specified below for VIH2 – VIH3 0.7 VDD VIH2 Ports 1, 3, 6, 7, and RESET 0.8 VDD VDD VIH3 XIN and XOUT VDD – 0.1 VDD VIL1 All input pins except those specified below for VIL2–VIL3 VIL2 Ports 1, 3, 6, 7, and RESET VIL3 XIN and XOUT – – 0.3 VDD 0.2 VDD 0.1 V KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 KS57P5208/P5308/P5312 OTP Table 15-7. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Units VDD – 1.0 – – V V Output high voltage VOH IOH = – 1 mA Ports except 1 Output low voltage VOL1 VDD = 4.5 V to 5.5 V IOL = 15 mA, Ports 4 and 5 only – – 2 VDD = 1.8 to 5.5 V, IOL = 1.6mA – – 0.4 VDD = 4.5 V to 5.5 V IOL= 4 mA, all out ports except 4,5 – – 2 VDD = 1.8 to 5.5 V, IOL = 1.6mA – – 0.4 ILIH1 VI = VDD All input pins except those specified below – – 3 ILIH2 VI = VDD XIN and XOUT ILIL1 VI = 0 V All input pins except below and RESET ILIL2 VI = 0 V XIN and XOUT only Output high leakage current ILOH VO = VDD All out pins – – 3 µA Output low leakage current ILOL VO = 0 V All out pins – – –3 µA Pull-up resistor RL1 VDD = 5 V; VI = 0 V except RESET 25 47 100 kΩ VDD = 3 V 50 95 200 VDD = 5 V; VI = 0 V; RESET 100 220 400 VDD = 3 V 200 450 800 VOL2 Input high leakage current Input low leakage current RL2 V µA 20 – – –3 µA – 20 15-7 KS57P5208/P5308/P5312 OTP KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Table 15-7. D.C. Electrical Characteristics (Concluded) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Supply current (1) Symbol IDD1 (DTMF on) Conditions Run mode; VDD = 5 V ± 10% (2) 3.58 MHz crystal oscillator, C1 = C2 = 22 pF Min Typ Max Units – 2.5 5.0 mA 1.4 3.0 2.5 8.0 VDD = 3 V ± 10% IDD2 (DTMF off) IDD3 IDD4 Run mode; VDD = 5 V ± 10% 6.0 MHz crystal oscillator, C1 = C2 = 22 pF 3.58 MHz 1.6 4.0 VDD = 3 V ± 10% 6.0 MHz 1.2 4.0 3.58 MHz 0.7 2.3 0.7 2.5 – Idle mode; = VDD = 5 V ± 10% 6.0 MHz crystal oscillator, C1 = C2 = 22 pF 3.58 MHz 0.6 1.8 VDD = 3 V ± 10% 6.0 MHz 0.3 1.5 3.58 MHz 0.2 1.0 0.01 3 0.01 2 Stop mode; VDD = 5 V ± 10% – – Stop mode; VDD = 3 V ± 10% mA mA µA Row tone level VROW VDD = 2.0 V to 5.5 V RL = 12 kΩ, Temp = – 30 °C to 60 °C Ratio of column to row tone dBCR VDD = 2.0 V to 5.5 V RL = 12 kΩ, Temp = – 30 °C to 60 °C 1 2 3 dB Distortion (Dual tone) THD VDD = 2.0 V to 5.5 V 1MHz band; RL= 12 kΩ Temp = – 30 °C to 60 °C – – 5 % – 16.0 – 14.0 – 11.0 NOTES: 1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up registers. 2. For D.C. electrical values, the power control register (PCON) must be set to 0011B. 15-8 dBV KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 KS57P5208/P5308/P5312 OTP Table 15-8. Main System Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration XIN XOUT C1 Crystal Oscillator XIN Test Condition Min Typ Max Units Oscillation frequency (1) VDD = 2.7 V to 5.5 V 0.4 – 6.0 MHz VDD = 1.8 V to 5.5 V 0.4 – 3 – – 4 ms MHz C2 XOUT C1 Parameter Stabilization time (2) VDD = 3 V Oscillation frequency (1) VDD = 2.7 V to 5.5 V 0.4 – 6.0 VDD = 1.8 V to 5.5 V 0.4 – 3 – – 10 ms VDD = 2.7 V to 5.5 V 0.4 – 6.0 MHz VDD = 1.8 V to 5.5 V 0.4 – 3 – 83.3 – 1250 C2 Stabilization time (2) External Clock XIN XOUT XIN input frequency (1) XIN input high and low level width (tXH, tXL) VDD = 3 V ns NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated. 15-9 KS57P5208/P5308/P5312 OTP KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Table 15-9. Input/Output Capacitance (TA = 25 °C, VDD = 0 V ) Parameter Symbol Condition Min Typ Max Units CIN f = 1 MHz; Unmeasured pins are returned to VSS – – 15 pF COUT – – 15 pF CIO – – 15 pF Min Typ Max Units VDD = 2.7 V to 5.5 V 0.67 – 64 µs VDD = 1.8 V to 5.5 V 1.33 VDD = 2.7 V to 5.5 V 0 – 1.5 MHz 1 MHz – – µs Input Capacitance Output Capacitance I/O Capacitance Table 15-10. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time TCL0, TCL1 Input Frequency Symbol tCY fTI0, fTI1 Conditions VDD = 1.8 V to 5.5V TCL0, TCL1 Input High, Low Width Interrupt Input High, Low Width RESET Width 15-10 Input Low VDD = 2.7 V to 5.5 V 0.48 VDD = 1.8 V to 5.5 V 1.8 tINTH, tINTL INT0, INT1, INT2, INT4, KS0-KS7 10 – – µs tRSL Input 10 – – µs tTIH0, tTIL0 tTIH1, tTIL1 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 KS57P5208/P5308/P5312 OTP Main Oscillator Frequency (Divided by 4) CPU Clock 1.5 MHz 6 MHz 0.75 MHz 3 MHz 15.625 kHz 1 2 1.8 3 4 5 6 7 2.7 Supply Voltage (V) CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64) Figure 15-5. Standard Operating Voltage Range Table 15-11. RAM Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Symbol Data retention supply voltage VDDDR Data retention supply current IDDDR Release signal set time tSREL Oscillator stabilization wait time (1) tWAIT Conditions Min – VDDDR = 1.8 V – Released by RESET Released by interrupt Typ Max 1.8 – 5.5 V – 0.1 10 µA 0 – – µs – 17 – ms 2 /fx Unit (2) NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time. 15-11 KS57P5208/P5308/P5312 OTP KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 NOTES 15-12