S3C8465/C8469/P8469 1 PRODUCT OVERVIEW PRODUCT OVERVIEW SAM8 PRODUCT FAMILY Samsung's new SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. A dual address/data bus architecture and a large number of bit- or nibble-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations. Many SAM8 microcontrollers have an external interface that provides access to external memory and other peripheral devices. A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to one interrupt level at a time. S3C8465/C8469 MICROCONTROLLER The S3C8465/C8469 single-chip 8-bit microcontroller is designed for useful 10-bit resolution A/D converter, UART, SIO, ZCD extended PWM application field. Its powerful SAM87 CPU architecture includes. The internal register file is logically expanded to increase the on-chip register space. The S3C8465/C8469 has 16/32K bytes of on-chip program ROM. A sophisticated bus interface enables access to external memory and other peripherals when you use the chip in ROM-less mode. Following Samsung's modular design approach, the following peripherals are integrated with the SAM87 core: — Large number of programmable I/O ports (total 56 pins) — One asynchronous UART module — One synchronous SIO module — Analog-to-digital converter with eight input channels and 10-bit resolution — One 8-bit basic timer for watchdog function — One 8-bit timer/counter with three operating modes (timer 0) — One 8-bit timer for zero-cross detection circuit (timer 2) — Two general-purpose 16-bit timer/counters with four operating modes (timer module 1) — PWM block with one capture module, 16-bit timer/counter, PWM extension mode, and two PWM outputs — One zero cross detection module The S3C8465/C8469 is a versatile general-purpose microcontroller that is ideal for use in a wide range of electronics applications requiring complex timer/counter, PWM, capture, SIO, UART and ZCD functions. It is available in a 64-pin SDIP or 64-pin QFP package. OTP The S3P8469 is an OTP (One Time Programmable) version of the S3C8465/C8469 microcontroller. The S3P8469 microcontroller has an on-chip 32-Kbyte one-time-programmable EPROM instead of a masked ROM. The S3P8469 is comparable to the S3C8465/C8469, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C8465/C8469/P8469 FEATURES CPU Timer/Counters • • One 8-bit basic timer for watchdog function • One 8-bit timer/counter with three operating modes (timer 0) • One 8-bit timer for the zero-cross detection circuit • Two 16-bit general-purpose timer/counters with four operating modes (timer C and D) SAM87 CPU core Memory • 528-byte general purpose register area • 16/32K-byte internal program memory • ROM-less operating mode External Interface • 64K-byte external data memory area • 64K-byte external program memory area (ROM-less mode) Instruction Set • 79 instructions • IDLE and STOP instructions added for power-down modes UART • One UART module • Full duplex serial I/O interface with three UART modes A/D Converter • Eight analog input pins • 10-bit conversion resolution • 20 µs conversion time (10 MHz CPU clock) Instruction Execution Time • 500 ns at 12 MHz fOSC (minimum) Zero Cross Detection Circuit • Interrupts Zero cross detection circuit that generates a digital signal in synchronization with an AC signal input • 21 interrupt sources and 21 vectors • Eight interrupt levels Buzzer Frequency Output • Fast interrupt processing • 200 Hz to 20 kHz signal can be generated General I/O Oscillator Frequency • Seven I/O ports (total 56 pins) • 1 MHz to 12 MHz external crystal oscillator • Seven bit-programmable ports • Maximum 12 MHz CPU clock PWM and Capture Operating Temperature Range • Two 14-bit PWM output • • One capture – 40°C to + 85°C Operating Voltage Range Serial I/O • 2.7 V to 5.5 V • One synchronous serial I/O module • Selectable transmit and receive rates Package Types • Selectable baud rate for Rx and Tx respectively • 1-2 64-pin SDIP, 64-pin QFP S3C8465/C8469/P8469 PRODUCT OVERVIEW BLOCK DIAGRAM Basic Timer XIN XOUT P1.0-P1.7 (AD0-AD7) P2.0-P2.3 P2.4/ZCD-P2.7/INT3 Port 0 Port 1 Port 0 SAM8 BUS OSC T0CK T0 Timer TCG TDG TCCK TDCK Timers C and D PWM0 PWM1 CAPA PWM/ CAP SI SO SCK SIO RxD TxD UART ADC0 -ADC7 P0.0-P0.7 (A8-A15) Port 3 P3.0-P3.7 Port 4 P4.0/INT4P4.7/INT11 Port 5 P5.0-P5.7 Port 6 P6.0-P6.7 Port I/O and Interrupt Control SAM8 CPU 16/32-Kbyte ROM 528-byte Register File ADC Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C8465/C8469/P8469 PIN ASSIGNMENTS P0.7/A15 P0.6/A14 P0.5/A13 P0.4/A12 P0.3/A11 P0.2/A10 P0.1/A9 P0.0/A8 P4.7/INT11/TDG P4.6/INT10/TCG P4.5/INT9/TDCK P4.4/INT8/TCCK P4.3/INT7/CAPA P4.2/INT6 P4.1/INT5/RxD VDD VSS XOUT XIN EA P4.0/INT4 P3.7/TxD RESET P3.6/SO P3.5/SI P3.4/SCK P3.3/T0CK P3.2/T0 P3.1/PWM1 P3.0/PWM0 P2.7/INT3 P2.6/INT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 S3C8465 S3C8469 64-SDIP-750 (Top View) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P1.0/AD0 P1.1/AD1 P1.2/AD2 P1.3/AD3 P1.4/AD4 P1.5/AD5 P1.6/AD6 P1.7/AD7 P5.7/ADC7 P5.6/ADC6 P5.5/ADC5 P5.4/ADC4 P5.3/ADC3 P5.2/ADC2 P5.1/ADC1 P5.0/ADC0 AVSS AVREF P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 P2.0/AS P2.1/DS P2.2/R/W P2.3/DM P2.4/ZCD P2.5/BUZ Figure 1-2. Pin Assignment Diagram (64-SDIP) 1-4 PRODUCT OVERVIEW 64 63 62 61 60 59 58 57 56 55 54 53 52 P0.1/A9 P0.2/A10 P0.3/A11 P0.4/A12 P0.5/A13 P0.6/A14 P0.7/A15 P1.0/AD0 P1.1/AD1 P1.2/AD2 P1.3/AD3 P1.4/AD4 P1.5/AD5 S3C8465/C8469/P8469 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 S3C8465/C8469 64-QFP-1420F (Top View) 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P1.6/AD6 P1.7/AD7 P5.7/ADC7 P5.6/ADC6 P5.5/ADC5 P5.4/ADC4 P5.3/ADC3 P5.2/ADC2 P5.1/ADC1 P5.0/ADC0 AVSS AVREF P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P3.3/T0CK P3.2/T0 P3.1/PWM1 P3.0/PWM0 P2.7/INT3 P2.6/INT2 P2.5/BUZ P2.4/ZCD P2.3/DM P2.2/R/W P2.1/DS P2.0/AS P6.0 20 21 22 23 24 25 26 27 28 29 30 31 32 P0.0/A8 P4.7/INT11/TDG P4.6/INT10/TCG P4.5/INT9/TDCK P4.4/INT8/TCCK P4.3/INT7CAPA P4.2/INT6 P4.1/INT5/RxD VDD VSS XOUT XIN EA P4.0/INT4 P3.7/TxD RESET P3.6/SO P3.5/SI P3.4/SCK Figure 1-3. Pin Assignment Diagram (64-Pin QFP Package) 1-5 PRODUCT OVERVIEW S3C8465/C8469/P8469 Table 1-1. S3C8465/C8469 Pin Descriptions Pin Name Pin Type P0.0–P0.7 I/O P1.0–P1.7 P2.0–P2.3 Circuit Number Pin Number Share Pins Bit-programmable I/O port for Schmitt trigger input or push-pull, open-drain, output. Pull-up resistors are assignable by software. Port 0 can also be configured as external interface address line A8–A15 1 8–1 (1, 64–58) – A8–A15 I/O Same general characteristics as port 0. Port 1 can also be configured as external interface address/data lines AD0–AD7 1 64–57 (57–50) – AD0–AD7 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull output. P2.0–P2.3 can be configured for external bus control signals. P2.4–P2.7 are used for general I/O or for the ZCD, BUZ, INT2 and INT3 2 38–35 (31–28) 3 34–31 (27–24) – AS, DS DM, R/W ZCD, BUZ INT2, INT3 P2.4–P2.7 Pin Description P3.0–P3.7 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull output. Each port 3 pin has an alternative function: P3.0: PWM0 (PWM0 module output) P3.1: PWM1 (PWM1 module ouptut) P3.2: T0 (T0 capture input or PWM output) P3.3: T0CK (timer 0 external clock input) P3.4: SCK (SIO module input) P3.5: SI (SIO module clock I/O) P3.6: SO (SIO module output) P3.7: TxD: SO1 (The T0 function for P3.2 is selected using the T0CON register.) 4 30–22 (23–15) (See pin description) P4.0–P4.7 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull output. Port 4 pins are used external interrupts INT4–INT11 or for the following share functions: P4.1: RxD (UART module input) P4.3: CAPA (capture input) P4.4: TCCK (timer/counter C clock input) P4.5: TDCK (timer/counter D clock input) P4.6: TCG (timer C gate input) P4.7: TDG (timer D gate input) 5 21, 15–9 (14–2) (See pin description) 1-6 S3C8465/C8469/P8469 PRODUCT OVERVIEW Table 1-1. S3C8465/C8469 Pin Descriptions (Continued) Pin Name Pin Type P5.0–P5.7 I/O P6.0–P6.7 Pin Description Circuit Number Pin Number Share Pins Bit-programmable I/O port for Schmitt trigger input or push-pull, output. Pull-up resistors are assignable by software. Port 5 pins can also be used as A/D converter inputs. 6 49–56 (42–49) ADC0– ADC7 I/O Individual pins are software configurable as input or push-pull, open-drain, output. Pull-up resistors are assignable by software. 1 39–46 (32–39) – AD0–AD7 I/O External interface address/data line 6 64–57 (57–50) P1.0–P1.7 AS DS R/W DM I/O External bus control signals 2 38–35 (31–28) P2.0–P2.3 ZCD I/O Zero cross detector input 2 34 (27) P2.4 BUZ I/O 200 Hz–20 kHz frequency output for buzzer sound 2 33 (26) P2.5 PWM0 PWM1 I/O PWM output 3 30, 29 (23, 22) P3.0–P3.1 T0 (CAP) I/O T0 capture input or PWM output 3 28 (21) P3.2 T0CK I/O External clock input for Timer 0 3 27 (20) P3.3 SCK I/O SIO clock signal 3 26 (19) P3.4 SI, SO I/O SIO data input/output 3 25, 24 (18, 17) P3.5–P3.6 TxD I/O UART data output 3 22 (15) P3.7 INT2–INT3 I/O External interrupts: the triggering edge is selectable. 2 32, 31 (25, 24) P2.6–P2.7 INT4 I/O External interrupts: the triggering edge is selectable. 4 21 (14) P4.0 RxD/INT5 I/O UART data input or external interrupt: the triggering edge is selectable. 4 15 (8) P4.1 INT6 CAPA/INT7 I/O Capture module input or external interrupt: the triggering edge is selectable. 4 14,13 (7, 6) P4.2–P4.3 1-7 PRODUCT OVERVIEW S3C8465/C8469/P8469 Table 1-1. S3C8465/C8469 Pin Descriptions (Concluded) Pin Name Pin Type TCCK/INT8 TCDK/INT9 I/O TCG/INT10 TDG/INT11 ADC0– ADC7 Pin Description Circuit Number Pin Number Share Pins Timer/counter C and D clock input or external interrupts: the triggering edge is selectable. 4 12, 11 (5, 4) P4.4–P4.5 I/O Timer/counter C and D clock input or external interrupts: the triggering edge is selectable. 4 10, 9 (3, 2) P4.6–P4.7 I/O A/D converter inputs 5 49–56 (42–49) P5.0–P5.7 XIN, XOUT – System clock input and output pins – 19, 18 (12, 11) – RESET I System reset pin 7 23 (16) – EA I External access (EA) pin with three modes: 0 V: Normal operation (internal ROM) 5 V: ROM-less operation (external interface) 12.5 V: OTP read/write mode – 20 (13) – AVREF, AVSS – A/D converter reference voltage input and ground – 47, 48 (40, 41) – VDD ,VSS – Voltage input pin and ground – 16, 17 (9, 10) – NOTE: Pin numbers shown in parentheses "( )" are for the 64-pin QFP package. 1-8 S3C8465/C8469/P8469 PRODUCT OVERVIEW PIN CIRCUITS Table 1-2. Pin Circuit Assignments for the S3C8465/C8469 Circuit Number Circuit Type S3C8465/C8469 Assignments 1 I/O Port 0,1 and port 6 2 I/O Port 2 (P2.0–P2.3 only) 3 I/O Port 2 (P2.4–P2.7 only) 4 I/O Port 3 5 I/O Port 4 6 I/O Port 5 7 I RESET NOTE: Diagrams of circuit types 1–7 are presented below. 1-9 PRODUCT OVERVIEW S3C8465/C8469/P8469 VDD Pull-up Resistor (Typical Value: 47 KΩ) Pull-up Enable VDD Data In/Out Open-drain Output DIsable In Figure 1-4. Pin Circuit Type 1 (Port 0,1 and Port 6) VDD Pull-up Resistor (Typical Value: 47 KΩ) Pull-up Enable Port 2 (Low Byte) Data External Interface (AS, DS, R/W, DM) Select M U X VDD Data In/Out Output DIsable In Figure 1-5. Pin Circuit Type 2 (Port 2, P2.0–P2.3 only) 1-10 S3C8465/C8469/P8469 PRODUCT OVERVIEW VDD Pull-up Resistor (Typical Value: 47 KΩ) Pull-up Enable Port 2 (High Byte) Data Control Output (BUZ) Select VDD M U X In/Out Output DIsable External Interrupt Input Noise Filter Normal Input ZCD Input Figure 1-6. Pin Circuit Type 3 (Port 2, P2.4–P2.7 only) 1-11 PRODUCT OVERVIEW S3C8465/C8469/P8469 VDD Pull-up Resistor (Typical Value: 47 KΩ) Pull-up Enable Port 3 Control Output Select M U X VDD Data In/Out Output DIsable Normal Input Figure 1-7. Pin Circuit Type 4 (Port 3) VDD Pull-up Resistor (Typical Value: 47 KΩ) Pull-up Enable VDD Data In/Out Output DIsable External Interrupt Input Noise Filter Alternative Input Normal Input Figure 1-8. Pin Circuit Type 5 (Port 4) 1-12 S3C8465/C8469/P8469 PRODUCT OVERVIEW VDD Pull-up Resistor (Typical Value: 47 KΩ) Pull-up Enable VDD Data In/Out Output DIsable Normal Input Analog Input Figure 1-9. Pin Circuit Type 6 (Port 5) VDD Pull-up Resistor (Typical Value: 200 KΩ) RESET Figure 1-10. Pin Circuit Type 7 (RESET RESET) 1-13 S3C8465/C8469/P8469 19 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this chapter, S3C8465/C8469 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — Input/output capacitance — D.C. electrical characteristics — A.C. electrical characteristics — Oscillation characteristics — Oscillation stabilization time — Data retention supply voltage in stop mode — Serial I/O timing characteristics — UART timing characteristics in mode 0 — A/D converter electrical characteristics — Zero crossing detector — External memory timing characteristics 19-1 ELECTRICAL DATA S3C8465/C8469/P8469 Table 19-1. Absolute Maximum Ratings (TA = 25°C) Parameter Supply Voltage Symbol Conditions Rating Unit VDD – – 0.3 to + 6.5 V Input Voltage VI All input ports – 0.3 to VDD + 0.3 V Output Voltage VO All output ports – 0.3 to VDD + 0.3 V Output Current High I OH One I/O pin active – 18 mA All I/O pins active – 60 One I/O pin active + 30 Total pin current for ports 0, 2–4, and 6 + 100 Total pin current for ports 1 and 5 + 200 Output Current Low Operating Temperature Storage Temperature I OL mA TA – – 40 to + 85 °C TSTG – – 65 to + 150 °C Table 19-2. Input/Output Capacitance (TA = – 40°C to 85°C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance 19-2 Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are tied to VSS Min Typ Max Unit – – 10 pF S3C8465/C8469/P8469 ELECTRICAL DATA Table 19-3. D.C. Electrical Characteristics (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit – VDD V – 0.2 VDD V VIH1 VDD = 2.7 V to 5.5 V 0.8 VDD VIH2 VDD = 4.5 V to 5.5 V XIN and XOUT VDD – 1.0 VIL1 VDD = 2.7 V to 5.5 V – VIL2 VDD = 4.5 V to 5.5 V XIN and XOUT Output High Voltage VOH VDD = 4.5 V to 5.5 V IOH = – 1 mA All Ports VDD – 1.0 – – V Output Low Voltage VOL1 VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 1,5, and 6 – 0.4 2.0 V VOL2 VDD = 4.5 V to 5.5 V IOL = 4 mA Ports 0, 2, 3, and 4 ILIH1 VIN = VDD All input pins except ILIH2 – – 1 µA ILIH2 VIN = VDD XIN, XOUT ILIL1 VIN = 0 V All input pins except and ILIL2 and RESET ILIL2 VIN = 0 V XIN, XOUT Output High Leakage Current ILOH1 VOUT = VDD All output pins – – 2 µA Output Low Leakage Current ILOL VOUT = 0 V All output pins – – –2 µA Input High Voltage Input Low Voltage Input High Leakage Current Input Low Leakage Current All Port and RESET All Ports and RESET 0.1 20 – – –1 µA – 20 19-3 ELECTRICAL DATA S3C8465/C8469/P8469 Table 19-3. D.C. Electrical Characteristics (Continued) (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Parameter Pull-up Resistor Symbol RP1 RP2 Supply Current IDD1 (note) IDD2 IDD3 Conditions Min Typ Max Unit VDD = 5 V; VIN = 0 V 30 47 70 kΩ VDD = 3 V; Ports 0–6 30 – 350 VDD = 5 V; VIN = 0 V 100 200 400 VDD = 3 V; RESET only 200 400 800 – 16 30 VDD = 2.7 V to 3.3 V 8 MHz CPU clock 5.5 12 VDD = 4.5 V to 5.5 V Idle mode 12 MHz CPU clock 3 6 VDD = 2.7 V to 3.3 V 8 MHz CPU clock 1 2.5 VDD = 4.5 V to 5.5 V Stop mode 1 5 VDD = 4.5 V to 5.5 V RUN mode 12 MHz CPU clock mA µA VDD = 2.7 V to 3.3 V Stop mode NOTE: Supply current does not include current drawn through internal pull-up resistors, ZCD, ADC and external output current loads. Table 19-4. A.C. Electrical Characteristics (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Parameter Interrupt Input High, Low Width RESET Input Low Width Symbol tINTH, tINTL tRSL Conditions Min Typ Max Unit Ports 2, 3, and 4 – 270 – ns Input – 1500 – ns tINTL tINTH tRSL 0.8 VDD 0.2 VDD Figure 19-1. Input Timing Measurement Points 19-4 S3C8465/C8469/P8469 ELECTRICAL DATA Table 19-5. Oscillation Characteristics (TA = – 40°C + 85°C) Oscillator Clock Circuit Test Condition Main Crystal or Ceramic XOUT XIN C1 XIN Typ Max Unit VDD = 4.5 V to 5.5 V 1 – 12 MHz VDD = 2.7 V to 4.5 V 1 – 8 VDD = 4.5 V to 5.5 V 1 – 12 VDD = 2.7 V to 4.5 V 1 – 8 C2 External Clock (Main System) Min XOUT MHz Main Oscillator Frequency CPU Clock 12 kHz 8 kHz 1 kHz 1 2 3 4 2.7 V 5 6 7 5.5 V Supply Voltage (V) Figure 19-2. Operating Voltage Range 19-5 ELECTRICAL DATA S3C8465/C8469/P8469 Table 19-6. Oscillation Stabilization Time (TA = – 40°C + 85°C, VDD = 2.7 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit Main Crystal f OSC > 400 kHz; – – 20 ms Main Ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. – – 10 ms External Clock (Main System) XIN input High and Low width (tXH, tXL) 25 – 500 ns Oscillator Stabilization Wait Time tWAIT when released by a reset (1) – 216/fOSC – ms tWAIT when released by an interrupt (2) – – – ms NOTES: 1. fOSC is the oscillator frequency. 2. The duration of the oscillator stabilization wait time, tWAIT, when it is released by an interrupt is determined by the settings in the basic timer control register, BTCON. 19-6 S3C8465/C8469/P8469 ELECTRICAL DATA Table 19-7. Data Retention Supply Voltage in Stop Mode (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Data Retention Supply Voltage VDDDR Stop mode 2 – 5.5 V Data Retention Supply Current IDDDR Stop mode, VDDDR = 2.0 V – – 5 µA NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. RESET occurs ~ ~ Oscillation Stabilzation Time Stop Mode Data Retention Mode ~ ~ VDD Normal Operating Mode VDDDR Execution of STOP Instrction RESET NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC. tWAIT Figure 19-3. Stop Mode Release Timing When Initiated by a Reset 19-7 ELECTRICAL DATA S3C8465/C8469/P8469 Table 19-8. Serial I/O Timing Characteristics (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Parameter Symbol SCK Cycle Time tCKY SCK High, Low Width tKH, tKL SI Setup Time to SCK Low SI Hold Time to SCK High Output Delay for SCK to SO tSIK tKSI tKSO Conditions Min Typ Max Unit External SCK source 1000 – – ns Internal SCK source 1000 External SCK source 500 – – Internal SCK source tKCY/2 – 50 External SCK source 250 – – Internal SCK source 250 External SCK source 400 – – Internal SCK source 400 External SCK source – – 300 Internal SCK source 250 NOTE: "SCK" means serial I/O clock frequency, "SI" means serial data input, and "SO" means serial data output. tKCY tKL tKH SCK 0.8 VDD 0.2 VDD tSIK tKSI 0.8 VDD SI Input Data 0.2 VDD tKSO SO Output Data Figure 19-4. Serial Data Transfer Timing 19-8 S3C8465/C8469/P8469 ELECTRICAL DATA Table 19-9. UART Timing Characteristics in Mode 0 (10 MHz) (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V, Load capacitance = 80 pF) Parameter Symbol Min Typ Max Unit tSCK 500 tCPU × 6 700 ns Output data setup to clock rising edge tS1 300 tCPU × 5 – Clock rising edge to input data valid tS2 – – 300 Output data hold after clock rising edge tH1 tCPU – 50 tCPU – Input data hold after clock rising edge tH2 0 – – Serial port clock High, Low level width tHIGH, tLOW 200 tCPU × 3 400 Serial port clock cycle time NOTES: 1. All timings are in nanoseconds (ns) and assume a 10-MHz CPU clock frequency. 2. The unit tCPU means one CPU clock period. tSCK tHIGH tLOW 0.8 VDD 0.2 VDD Figure 19-5. Waveform for UART Timing Characteristics 19-9 Shift Clock Data Out Data In tS1 D0 tS2 tSCK VALID tH1 D1 tH2 VALID D2 VALID Serial port clock cycle time Output data setup to clock rising edge Clock rising edge to input data valid Output data hold after clock rising edge Input data hold after clock rising edge D3 VALID NOTE: The symbols shown in this diagram are defined as follows: fSCK tS1 tS2 tH1 tH2 D4 VALID D5 VALID D6 VALID D7 VALID 19-10 S3C8465/C8469/P8469 ELECTRICAL DATA Figure 19-6. A.C. Timing Waveform for the UART Module S3C8465/C8469/P8469 ELECTRICAL DATA Table 19-10. A/D Converter Electrical Characteristics (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Symbol Test Conditions Resolution VDD = 5.12 V Total accuracy Min Typ Max Unit – 10 – bit – – ±3 LSB Integral linearity error ILE CPU clock = 10 MHz AVREF = 5.12 V – ±2 Differential linearity error DLE AVSS = 0 V – ±1 Offset error of top EOT ±1 ±3 Offset error of bottom EOB ± 0.5 ±2 Conversion time tCON 10-bit conversion 50 x 4/fOSC (3), fOSC = 10 MHz 20 – – µs Analog input voltage VIAN – AVSS – AVREF V Analog input impedance RAN – 2 – – MΩ Analog reference voltage AVREF – 2.5 – VDD V Analog ground AVSS – VSS – VSS + 0.3 V Analog input current IADIN AVREF = VDD = 5 V conversion time = 20 µs – – 10 µA Analog block current (2) IADC AVREF = VDD = 5 V conversion time = 20 µs 1 3 mA AVREF = VDD = 3 V conversion time = 20 µs 0.5 1.5 mA AVREF = VDD = 5 V when power down mode 100 500 nA (1) NOTES: 1. "Conversion time" is the time required from the moment a conversion operation starts until it ends. 2. IADC is operating current during A/D conversion. 3. fOSC is the main oscillator clock. 19-11 ELECTRICAL DATA S3C8465/C8469/P8469 Table 19-11. Zero Crossing Detector (TA = – 40°C to + 85°C, VDD = 4.5 V to 5.5 V, VSS = 0 V) Parameter Symbol Test Conditions Zero-crossing detection input voltage VZC AC connection c = 0.1 µF Zero-crossing detection accuracy VAZC f ZC = 60 Hz (sine wave) VDD = 5 V f OSC = 10 MHz – f ZC Zero-crossing detection input frequency Min Typ Max Unit 1.0 – 3.0 Vp-p – – ± 150 mV 40 – 200 Hz 1/fzc AC input VAZC ZCINT Figure 19-7. Zero Crossing Waveform Diagram 19-12 VAZ (P-P) S3C8465/C8469/P8469 ELECTRICAL DATA Table 19-12. External Memory Timing Characteristics (8 MHz) (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Number Symbol Parameter Normal Timing (ns) Min Max 1 tdA (AS) Address valid to AS ↑ delay 10 – 2 tdAS (A) AS ↑ to address float delay 35 – 3 tdAS (DR) AS ↑ to read data required valid – 140 4 twAS AS Low width 43.75 (35) – 5 tdA (DS) Address float to DS ↓ 0 – 6a twDS (read) DS (read) Low width 156.25 (125) – 6b twDS (write) DS (write) Low width 81.25 (65) – 7 tdDS (DR) DS ↓ to read data required valid – 80 8 thDS (DR) Read data to DS ↑ hold time 0 – 9 tdDS (A) DS ↑ to address active delay 20 – 10 tdDS (AS) DS ↑ to AS ↓ delay 30 – 11 tdDO (DS) Write data valid to DS (write) ↓ delay 10 – 12 tdRW (AS) R/W valid to AS ↑ delay 20 – 13 tdDS (DW) DS ↑ to write data not valid delay 20 – NOTES: 1. All times are in nanoseconds (ns) and assume an 8-MHz input frequency. 2. Wait states add 100 ns to the time of numbers 3, 6a, 6b, and 7. 3. The values for twAS and twDS that are shown in parentheses "( )" assume a 10-MHz input clock. 19-13 ELECTRICAL DATA S3C8465/C8469/P8469 R/W (P2.2) 12 Port 0 DM (P2.3) A8-A15, DM 3 Port 1 A0-A7 1 AS (P2.0) 9 D0-D7 Out 2 D0-D7 11 Out 10 5 4 In 8 7 DS (P2.1) 6 Figure 19-8. External Memory Read and Write Timing (See Table 19-10 for a description of each timing point.) 19-14 13 S3C8465/C8469/P8469 20 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C8465/C8469/P8469 microcontrollers are available in a 64-SDIP-750, 64-QFP-1420F package. #33 0.2 5 64-SDIP-750 +0 - 0 .10 .05 0-15 19.05 17.00 ± 0.20 #64 0.45 ± 0.10 (1.34) NOTE: 1.00 ± 0.10 1.778 5.08 MAX 57.80 ± 0.20 3.30 ± 0.30 58.20 MAX 4.10 ± 0.20 #32 0.51 MIN #1 Dimensions are in millimeters. Figure 20-1. 64-SDIP-750 Package Dimensions 20-1 MECHANICAL DATA S3C8465/C8469/P8469 23.90 ± 0.30 0-8 20.00 ± 0.20 + 0.10 14.00 ± 0.20 0.10 MAX 64-QFP-1420F 0.80 ± 0.20 17.90 ± 0.30 0.15 - 0.05 #64 #1 1.00 + 0.10 0.40 - 0.05 0.15 MAX 0.05 MIN (1.00) 2.65 ± 0.10 3.00 MAX 0.80 ± 0.20 NOTE: Dimensions are in millimeters. Figure 20-2. 64-QFP-1420F Package Dimensions 20-2 S3C8465/C8469/P8469 21 KS88P4632 OTP S3P8469 OTP OVERVIEW The S3P8469 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C8465/C8469 microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data format. The S3P8469 is fully compatible with the S3C8465/C8469, both in function in D.C. electrical characteristics and in pin configuration. Because of its simple programming requirements, the S3P8469 is ideal as an evaluation chip for the S3C8465/C8469. 21-1 KS88P4632 OTP S3C8465/C8469/P8469 P0.7/A15 P0.6/A14 P0.5/A13 P0.4/A12 P0.3/A11 P0.2/A10 P0.1/A9 P0.0/A8 P4.7/INT11/TDG P4.6/INT10/TCG P4.5/INT9/TDCK P4.4/INT8/TCCK P4.3/INT7/CAPA SDAT/P4.2/INT6 SCLK/P4.1/INT5/RxD VDD/VDD VSS/VSS XOUT XIN VPP/EA P4.0/INT4 P3.7/TxD RESET/RESET RESET P3.6/SO P3.5/SI P3.4/SCK P3.3/T0CK P3.2/T0 P3.1/PWM1 P3.0/PWM0 P2.7/INT3 P2.6/INT2 NOTE: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 S3C8465 S3C8469 (64-SDIP) Top View 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P1.0/AD0 P1.1/AD1 P1.2/AD2 P1.3/AD3 P1.4/AD4 P1.5/AD5 P1.6/AD6 P1.7/AD7 P5.7/ADC7 P5.6/ADC6 P5.5/ADC5 P5.4/ADC4 P5.3/ADC3 P5.2/ADC2 P5.1/ADC1 P5.0/ADC0 AVSS AVREF P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 P2.0/AS P2.1/DS P2.2/R/W P2.3/DM P2.4/ZCD P2.5/BUZ The bolds indicate an OTP pin name. Figure 21-1. S3P8469 Pin Assignments (64-SDIP Package) 21-2 KS88P4632 OTP P0.1/A9 P0.2/A10 P0.3/A11 P0.4/A12 P0.5/A13 P0.6/A14 P0.7/A15 P1.0/AD0 P1.1/AD1 P1.2/AD2 P1.3/AD3 P1.4/AD4 P1.5/AD5 S3C8465/C8469/P8469 P0.0/A8 P4.7/INT11/TDG P4.6/INT10/TCG P4.5/INT9/TDCK P4.4/INT8/TCCK P4.3/INT7CAPA SDAT/P4.2/INT6 SCLK/P4.1/INT5/RxD VDD/VDD VSS/VSS XOUT XIN VPP/EA P4.0/INT4 P3.7/TxD RESET/RESET RESET P3.6/SO P3.5/SI P3.4/SCK S3C8465 S3C8469 (64-QFP) P3.3/T0CK P3.2/T0 P3.1/PWM1 P3.0/PWM0 P2.7/INT3 P2.6/INT2 P2.5/BUZ P2.4/ZCD P2.3/DM P2.2/R/W P2.1/DS P2.0/AS P6.0 Top View P1.6/AD6 P1.7/AD7 P5.7/ADC7 P5.6/ADC6 P5.5/ADC5 P5.4/ADC4 P5.3/ADC3 P5.2/ADC2 P5.1/ADC1 P5.0/ADC0 AVSS AVREF P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 NOTE: The bolds indicate an OTP pin name. Figure 21-2. S3P8469 Pin Assignments (64-QFP Package) 21-3 KS88P4632 OTP S3C8465/C8469/P8469 Table 21-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P4.2 SDAT 14(7) I/O P4.1 SCLK 15(8) I Serial clock pin. Input only pin. EA VPP 20(13) I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is aplied, OTP is in reading mode. (Option) RESET RESET 23(16) I Chip Initialization VDD/VSS VDD/VSS 16(9)/17(10) – Logic power supply pin. VDD should be tied to +5 V during programming. Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. NOTE: ( ) means 64 QFP package. Table 21-2. Comparison of S3P8469 and S3C8465/C8469 Features Characteristic S3P8469 S3C8465/C8469 Program Memory 32K-byte EPROM 16/32K-byte mask ROM Operating Voltage (VDD) 2.7 V to 5.5 V 2.7 V to 5.5 V OTP Programming Mode VDD = 5 V, VPP (EA) = 12.5 V Pin Configuration 64 SDIP/64 QFP 64 SDIP/64 QFP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (EA) pin of the S3P8469, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 21-3 below. Table 21-3. Operating Mode Selection Criteria VDD 5V REG/ MEM ADDRESS (EA) VPP 5V 0 0000H 1 EPROM read 12.5 V 0 0000H 0 EPROM program 12.5 V 0 0000H 1 EPROM verify 12.5 V 1 0E3FH 0 EPROM read protection NOTE: "0" means Low level; "1" means High level. 21-4 R/W MODE (A15–A0)