SAMSUNG S3P7565

S3C7565/P7565
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
OVERVIEW
The S3C7565/P7565 single-chip CMOS microcontroller is designed for high performance in the application for
Caller-ID, Telephone using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangable Microcontrollers).
Featuring a DTMF generator, up-to-960-dot LCD direct drive capability, one 8-bit timer/counter and flexible two
8-bit timer/counters, and serial I/O interface, the S3C7565/P7565 offer an excellent design solution for a wide
variety of applications requiring DTMF, LCD support.
Up to 43 (including COM/SEG) pins in the 100-pin QFP package can be dedicated to I/O. Nine vectored
interrupts provide a fast response to internal and external events. In addition the advanced CMOS technology a
of the S3C7565/P7565 ensures low power consumption with a wide operating voltage range.
OTP
The S3C7565 microcontroller is also available in OTP (One Time Programmable) version, S3P7565.
S3P7565 microcontroller has an on-chip 16 K-byte one-time-programmable EPROM instead of masked ROM.
The S3P7565 is comparable to S3C7565, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C7565/P7565
FEATURES SUMMARY
Memory
•
16K × 8-bit ROM
•
5,120 × 4-bit RAM (excluding LCD RAM)
I/O Pins
•
•
Input only: 4pins (Not including COM/SEG)
6pins (Including COM/SEG)
I/O: 15pins (Not including COM/SEG)
43pins (Including COM/SEG)
Memory-Mapped I/O Structure
•
Data memory bank 15
8-bit Serial I/O Interface
•
•
•
8-bit transmit/receive mode
8-bit receive mode
LSB-first or MSB-first transmission selectable
LCD Controller/Driver
•
•
•
•
•
60 SEG x 16 COM terminals
8, 12 and 16 com selectable
COM 8–15: shared with port
SEG40–59: shared with port
Two kinds of LCD bias resistor value
Bit Sequential Carrier
8-bit Basic Timer
•
•
•
Interrupts
Four interval timer functions
Watchdog timer
8-bit Timer/Counter
•
•
•
•
Programmable 8-bit timer
External event counter
Arbitrary clock frequency output
External clock signal divider
16-Bit Timer/Counter
•
•
•
•
•
•
Programmable 16-bit timer
External event counter
Arbitrary clock frequency output
External clock signal divider
Configurable as two 8-bit Timers
Serial I/O interface clock generator
Watch Timer
•
Time interval generation: 0.5 s, 3.9 ms
at 32.768 kHz
•
4 frequency outputs to BUZ pin (0.5, 1, 2, 4 kHz)
at 32.768 kHz
•
•
•
Supports 16-bit serial data transfer in arbitrary
format
Four external interrupt vectors
Five internal interrupt vectors
Two quasi-interrupts
Power-Down Modes
•
•
•
Idle mode (only CPU clock stops)
Stop mode (main system oscillation stops)
Subsystem clock stop mode
Oscillation Sources
•
•
•
RC, Crystal or Ceramic for system clock
Oscillation frequency: 0.4–6.0 MHz
CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
•
•
•
1.12, 2.23, 17.88 µs at 3.58 MHz
0.67, 1.33, 10.7 µs at 6.0 MHz
122 µs at 32.768 kHz (subsystem)
Operating Temperature
•
– 40 °C to 85 °C
Comparator
Operating Voltage Range
•
•
•
•
•
4-channel mode: Internal reference (4-bit
resolution); 16-step variable reference voltage
3-channel mode: External reference
1.8 V to 5.5 V (except DTMF and Comparator)
2 V to 5.5 V (include DTMF)
4.0 V to 5.5 V (include Comparator)
DTMF Generator
Package Type
•
•
1-2
16 dual-tone for tone dialing
100-pin QFP (1420C)
S3C7565/P7565
PRODUCT OVERVIEW
BLOCK DIAGRAM
P7.0/SEG55/CIN0
P7.1/SEG54/CIN1
P7.2/SEG53/CIN2
P7.3/SEG52/CIN3
Comparator
P1.0-P1.3/
INT0-INT4
Input Port 1
P2.0/CLO
P2.1/VLC1
P2.2
I/O Port 2
P3.0/TCLO0
P3.1/TCLO1
P3.2/TCL0
P3.3/TCL1
I/O Port 3
P4.0-P4.3/
COM8-COM11
I/O Port 4
P5.0-P5.3/
COM12-COM15
I/O Port 5
P6.0-P6.3
SEG59-SEG56/
KS4-KS7
P7.0/SEG55/CIN0
P7.1/SEG54/CIN1
P7.2/SEG53/CIN2
P7.3/SEG52/CIN3
P8.0/SEG51/LCDCK
P8.1/SEG50/LCDSY
P8.2/SEG49
P8.3/SEG48
P9.0-P9.3/
SEG47-SEG44
P10.0-P10.3/
SEG43-SEG40
XIN
RESET
Watchdog
Timer
XT IN XTOUT
Watch
Timer
Interrupt
Control
Block
Clock
VLC1
Program
Counter
Internal
Interrupts
I/O Port 6
Instruction
Register
LCD
Driver/
Controller
Instruction Dcoder
I/O Port 7
Basic
Timer
XOUT
COM0-COM7
P4.0-P5.3/
COM8-COM15
SEG0-SEG39
P10.3-P6.0/
SEG40-SEG59
Serial I/O
Program
Status Word
Arithmetic
and
Logic Unit
Stack
Pointer
I/O Port 0
P0.0/SCK/KO
P0.1/SO/K1
P0.2/SI/K2
P0.3/BUZ/K3
DTMF
Generator
DTMF
I/O Port 8
I/O Port 9
I/O Port 10
8-Bit
Timer/
Counter
16-Bit
Timer/Counter
(Two 8Bit
Timer/Counter)
5K x 4-bit
RAM
16KB ROM
Figure 1-1. S3C7565 Block Diagram
1-3
PRODUCT OVERVIEW
S3C7565/P7565
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
S3C7565
(100-QFP-1420C)
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
DTMF
P0.0/SCK/K0
P0.1/SO/K1
P0.2/SI/K2
P0.3/BUZ/K3
VDD
VSS
XOUT
XIN
TEST
XTIN
XTOUT
RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/CLO
P2.1/VLC1
P2.2
P3.0/TCLO0
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
P10.3/SEG40
P10.2/SEG41
P10.1/SEG42
P10.0/SEG43
P9.3/SEG44
P9.2/SEG45
P9.1/SEG46
P9.0/SEG47
P8.3/SEG48
P8.2/SEG49
P8.1/SEG50/LCDSY
P8.0/SEG51/LCDCK
P7.3/SEG52/CIN3
P7.2/SEG53/CIN2
P7.1/SEG54/CIN1
P7.0/SEG55/CIN0
P6.3/SEG56/K7
P6.2/SEG57/K6
P6.1/SEG58/K5
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P6.0/SEG59/K4
P5.3/COM15
P5.2/COM14
P5.1/COM13
P5.0/COM12
P4.3/COM11
P4.2/COM10
P4.1/COM9
P4.0/COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
P3.3/TCL1
P3.2/TCL0
P3.1/TCLO1
Figure 1-2. S3C7565 Pin Assignments (100-QFP Package)
1-4
S3C7565/P7565
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C7565 Pin Descriptions
Pin Name
Pin Type
Description
P0.0
P0.1
P0.2
P0.3
I/O
4-bit I/O port.
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
Individual pins are software configurable as open-drain or
push-pull output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
SCK/K0
SO/K1
SI/K2
BUZ/K3
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
1-bit and 4-bit read and test is possible.
4-bit pull-up resistors are software assignable.
INT0
INT1
INT2
INT4
P2.0
P2.1
P2.2
I/O
Same as port 0 except that port 2 is a 3-bit I/O port.
CLO
VLC1
P3.0
P3.1
P3.2
P3.3
I/O
Same as port 0.
TCLO0
TCLO1
TCL0
TCL1
P4.0–P4.3
P5.0–P5.3
I/O
4-bit I/O ports.
1-, 4-bit or 8-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
COM8–COM11
COM12–COM15
P6.0–P6.3
I/O
Same as P4, P5.
SEG59–
SEG56/K4–K7
P7.0–P7.3
Share Pin
SEG55/CIN0–
SEG52/CIN3
P8.0–P8.1
I/O
Input ports.
1, 4-bit or 8-bit read and test is possible.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
These pins can not be used as push-pull output. Refer to
the NOTES of table 10-3. Port Mode Group Flags.
SEG51/LCDCK
SEG50/LCDSY
P8.2–P8.3
I/O
Same as P4, P5.
SEG49
SEG48
P9.0–P9.3
SEG47–SEG44
P10.0–P10.3
I/O
Same as P4, P5.
SEG43–SEG40
SCK
I/O
Serial I/O interface clock signal.
P0.0/K0
SO
I/O
Serial data output.
P0.1/K1
1-5
PRODUCT OVERVIEW
S3C7565/P7565
Table 1-1. S3C7565 Pin Descriptions (Continued)
Pin Name
Pin Type
Description
Share Pin
SI
I/O
Serial data input.
P0.2/K2
BUZ
I/O
0.5, 1, 2, or 4 kHz frequency output for buzzer sound.
P0.3/K3
INT0, INT1
I
External interrupts. The triggering edge for INT0 and
INT1 is selectable.
P1.0, P1.1
INT2
I
Quasi-interrupt with detection of rising or falling edges.
P1.2
INT4
I
External interrupt with a detection of rising and falling
edge.
P1.3
CLO
I/O
Clock output .
P2.0
TCLO0
I/O
Timer/counter 0 clock output.
P3.0
TCLO1
I/O
Timer/counter 1 clock output.
P3.1
TCL0
I/O
External clock input for timer/counter 0.
P3.2
TCL1
I/O
External clock input for timer/counter 1.
P3.3
CIN0
CIN1
CIN2
CIN3
I/O
4-Channel comparator input
CIN0–CIN2: comparator input only
CIN3: comparator input or external reference input
P7.0/SEG55
P7.1/SEG54
P7.2/SEG53
P7.3/SEG52
DTMF
O
DTMF output
LCDCK
I/O
LCD clock output
P8.0/SEG51
LCDSY
I/O
LCD synchronization clock output.
P8.1/SEG50
COM0–COM7
O
LCD common signal output.
COM8–COM11
I/O
–
–
P4.0–P4.3
COM12–COM15
P5.0–P5.3
SEG0–SEG39
O
SEG40–SEG59
I/O
K0–K3
I/O
LCD segment signal output.
–
P10.3–P6.0
External interrupt (triggering edge is selectable)
K4–K7
P0.0–P0.3
P6.0–P6.3
VDD
–
Main power supply.
–
VSS
–
Ground.
–
RESET
I
Reset signal.
–
VLC1
–
LCD power supply.
XIN, XOUT
–
Crystal, Ceramic or RC oscillator pins for system clock.
–
XTIN, XTOUT
–
Crystal oscillator pins for subsystem clock.
–
TEST
I
Chip test input pin.
Hold GND when the device is operating.
–
P2.1
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
1-6
S3C7565/P7565
PRODUCT OVERVIEW
Table 1-2. Supplemental S3C7565 Pin Data
Pin Names
Share Pins
I/O Type
RESET Value
Circuit Type
P0.0–P0.3
SCK/K0, SO/K1,
SI/K2, BUZ/K3
I/O
Input
E-4
P1.0–P1.3
INT0, INT1 and
INT2, INT4
I
Input
A-4
P2.0
CLO
I/O
Input
E-4
P2.1
VLC1
I/O
Input
E-7
I/O
Input
E-4
P2.2
–
P3.0–P3.1
TCLO0, TCLO1
I/O
Input
E-2
P3.2–P3.3
TCL0, TCL1
I/O
Input
E-4
P4.0–P4.3
P5.0–P5.3
COM8–COM11
COM12–COM15
I/O
Input
H-24
P6.0–P6.3
SEG59/K4–
SEG56/K7
I/O
Input
H-25
P7.0–P7.2
SEG55/CIN0–
SEG53/CIN2
I/O
Input
H-26
P7.3
SEG52/CIN3
I/O
Input
H-27
P8.0–P8.1
SEG51–SEG50
I/O
Input
H-28
P8.2–P8.3
SEG49–SEG48
I/O
Input
H-24
P9.0–P9.3
SEG47–SEG44
I/O
Input
H-24
P10.0–P10.3
SEG43–SEG40
I/O
Input
H-24
COM0–COM7
–
O
High
H-3
SEG0–SEG39
–
O
High
H-3
DTMF
–
O
High impedance
G-7
VDD
–
–
–
–
VSS
–
–
–
–
RESET
–
I
–
B
VLC1
–
–
–
–
XIN, XOUT
–
–
–
–
XTIN, XTOUT
–
–
–
–
TEST
–
I
–
–
1-7
PRODUCT OVERVIEW
S3C7565/P7565
PIN CIRCUIT DIAGRAMS
VDD
VDD
Pull-Up
Resistor
P-Channel
In
In
N-Channel
Schmitt Trigger
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type B
VDD
VDD
Pull-Up
Resistor
Pull-Up
Resistor
Enable
Data
Out
Output
DIsable
In
P-CH
N-CH
Schmitt Trigger
Figure 1-4. Pin Circuit Type A-4
1-8
Figure 1-6. Pin Circuit Type C
S3C7565/P7565
PRODUCT OVERVIEW
VDD
PNE
Pull-up
Resistor
VDD
Pull-up
Resistor
Enable
P-CH
I/O
Data
N-CH
Output
DIsable
Figure 1-7. Pin Circuit Type E-2
VDD
PNE
Pull-up
Resistor
VDD
P-CH
Pull-up
Resistor
Enable
I/O
Data
N-CH
Output
DIsable
Schmitt Trigger
Figure 1-8. Pin Circuit Type E-4
1-9
PRODUCT OVERVIEW
S3C7565/P7565
VDD
PNE
Pull-up
Resistor
VDD
P-CH
I/O
Data
Output
DIsable
N-CH
Digital
Input
VLCEN
VLC1
Figure 1-9. Pin Circuit Type E-7
1-10
Pull-up
Resistor
Enable
S3C7565/P7565
PRODUCT OVERVIEW
VLC1
VLC2
VLC3
COM/SEG
VLC4
VLC5
VLC6
Figure 1-10. Pin Circuit Type H-3
1-11
PRODUCT OVERVIEW
S3C7565/P7565
VLC1
VLC2
VLC3
SEG/COM
Data
Output
DIsable
VLC4
VLC5
VSS
Figure 1-11. Pin Circuit Type H-23
1-12
Out
S3C7565/P7565
PRODUCT OVERVIEW
VDD
Pull-up
Resistor
Pull-up
Resistor
Enable
COM/SEG
LCD_ON
Circuit
Type H-23
Data
Circuit
Type C
Output
DIsable
I/O
Figure 1-12. Pin Circuit Type H-24
V DD
Pull-up
Resistor
Pull-up
Resistor
Enable
COM/SEG
LCD_ON
Circuit
Type H-23
Data
Output
DIsable
Circuit
Type C
I/O
Figure 1-13. Pin Circuit Type H-25
1-13
PRODUCT OVERVIEW
S3C7565/P7565
VDD
Pull-up
Resistor
Pull-up
Resistor
Enable
COM/SEG
LCD_ON
Data
Output
DIsable
P-CH
Circuit
Type H-23
Circuit
Type C
Analog
Input SEL
Digital In
Analog In
Figure 1-14. Pin Circuit Type H-26
1-14
I/O
S3C7565/P7565
PRODUCT OVERVIEW
VDD
Pull-up
Resistor
Pull-up
Resistor
Enable
COM/SEG
LCD OUT EN
Data
Output
DIsable
P-CH
Circuit
Type H-23
Circuit
Type C
I/O
Analog
Input SEL
Digital In
External
REF SEL
Analog In
External
REF In
Figure 1-15. Pin Circuit Type H-27
1-15
PRODUCT OVERVIEW
S3C7565/P7565
VDD
Pull-up
Resistor
Pull-up
Resistor
Enable
COM/SEG
LCD_ON
Circuit
Type H-23
LCDCK/CLDSY
LCDCK/LCDSY
Enable
Circuit
Type C
Output
DIsable
Figure 1-16. Pin Circuit Type H-28
DTMF Out
+
Disable
Figure 1-17. Pin Circuit Type G-7
1-16
I/O
S3C7565/P7565
16
ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this section, information on S3C7565 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at XIN
— Clock timing measurement at XTIN
— TCL timing
— Input timing for RESET
— Input timing for external interrupts
— Serial data transfer timing
16-1
ELECTRICAL DATA
S3C7565/P7565
Table 16-1. Absolute Maximum Ratings
(TA = 25 °C)
Parameter
Supply Voltage
Symbol
Conditions
Rating
Units
VDD
–
– 0.3 to + 6.5
V
– 0.3 to VDD + 0.3
V
– 0.3 to VDD + 0.3
V
mA
Input Voltage
VI
Output Voltage
VO
–
Output Current High
I OH
One I/O pin active
– 15
All I/O pins active
– 35
One I/O pin active
+ 30 (Peak value)
Output Current Low
Ports 0–10
I OL
mA
+ 15 (note)
Total for ports 0, 2–10
+ 100 (Peak value)
+ 60 (note)
Operating Temperature
Storage Temperature
TA
–
– 40 to + 85
°C
TSTG
–
– 65 to + 150
°C
NOTE: The values for Output Current Low (IOL) are calculated as Peak Value ×
Duty .
Table 16-2. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
–
VDD
V
VIH1
All input pins except those
specified below for VIH2–VIH3
0.7 VDD
VIH2
Ports 0, 1, 2, 6, P3.2, P3.3, and
RESET
0.8 VDD
VDD
VIH3
XIN, XOUT, and XTIN
VDD – 0.1
VDD
VIL1
All input pins except those
specified below for VIL2–VIL3
VIL2
Ports 0, 1, 2, 6, P3.2, P3.3, and
RESET
VIL3
XIN, XOUT, and XTIN
Output High
Voltage
VOH
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
Ports 0, 2–10
VDD – 1.0
–
–
V
Output Low
Voltage
VOL
VDD = 4.5 V to 5.5 V
IOL = 15 mA
–
–
2.0
V
Input High
Voltage
Input Low
Voltage
Ports 0, 2–10
16-2
–
–
0.3VDD
V
0.2VDD
0.1
S3C7565/P7565
ELECTRICAL DATA
Table 16-2. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Input High
Leakage
Current
Input Low
Leakage
Current
Symbol
Conditions
ILIH1
VI = VDD
All input pins except those
specified below for ILIH2
ILIH2
VI = VDD
XIN, XTIN
ILIL1
VI = 0 V
Min
Typ
Max
Units
–
–
3
µA
20
–
–
–3
µA
All input pins except RESET,
XIN, XTIN
ILIL2
VI = 0 V
XIN, XTIN
Output High
Leakage
Current
ILOH
VO = VDD
All output pins
–
–
3
µA
Output Low
Leakage
Current
ILOL
VO = 0 V
All output pins
–
–
–3
µA
Pull-Up
Resistor
RLI
VI = 0 V; VDD = 5 V, Port 0–10
25
47
100
kΩ
VDD = 3 V
50
95
200
VI = 0 V; VDD = 5 V, RESET
100
220
400
VDD = 3 V
200
450
800
40
55
70
20
28
35
RL2
– 20
LCD Voltage
Dividing
RLCD1
Resistor (Note)
RLCD2
|VDD-COMi|
Voltage Drop
(i = 0–15)
VDC
VDD = 2.7 V to 5.5 V
– 15 µA per common pin
–
–
120
|VDD-SEGx|
Voltage Drop
(x = 0–59)
VDS
VDD = 2.7 V to 5.5 V
– 15 µA per segment pin
–
–
120
VLCX Output
Voltage
VLC1
VDD = 2.7 V to 5.5 V
LCD clock = 0 Hz
VDD–0.2
VDD
VDD + 0.2
VLC2
0.8VDD–0.2
0.8VDD
0.8VDD +0.2
VLC3
0.6VDD–0.2
0.6VDD
0.6VDD+0.2
VLC4
0.4VDD–0.2
0.4VDD
0.4VDD+0.2
VLC5
0.2VDD–0.2
0.2VDD
0.2VDD+0.2
–
kΩ
mV
V
NOTE: RLCD1 is the LCD Voltage dividing resistor when LCON.1 = “0”, and RLCD2 when LCON.1 = “1”.
16-3
ELECTRICAL DATA
S3C7565/P7565
Table 16-2. D.C. Electrical Characteristics (Concluded)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Supply
Current (1)
Symbol
Min
Typ
Max
Units
–
3.9
7.0
mA
(DTMF on)
Run mode; VDD = 5 V ± 10 %
3.58 MHz X-tal oscillator,
C1 = C2 = 22 pF
–
2.0
4.0
IDD2
(DTMF off)
VDD = 3 V ± 10 %
Run mode;
VDD = 5 V ± 10%
Crystal oscillator
C1 = C2 = 22pF
–
4.1
2.7
8.0
5.0
1.9
1.2
1.2
0.9
4.0
2.3
2.5
1.8
1.5
1.0
45
µA
µA
IDD1
Conditions
VDD = 3 V ± 10%
IDD3
Idle mode;
VDD = 5 V ± 10 %
Crystal oscillator
C1 = C2 = 22pF
VDD = 3 V ± 10 %
6.0 MHz
3.58 MHz
6.0 MHz
3.58 MHz
6.0 MHz
3.58 MHz
–
IDD4 (2)
Run mode; VDD = 3 V ± 10 %
32 kHz Crystal oscillator
–
0.5
0.4
17.5
IDD5 (2)
Idle mode; VDD = 3 V ± 10 %
32 kHz Crystal oscillator
Stop mode;
SCMOD = 0000
XTIN = 0 V
VDD = 5 V ± 10 %
–
4.8
15
2.0
0.6
5
3
0.2
0.1
3
2
– 16.0
– 14.0
– 11.0
1
2
3
–
–
5
IDD6
6.0 MHz
3.58 MHz
–
VDD = 3 V ± 10 %
Stop mode;
VDD = 5 V ± 10 %
SCMOD = 0100
VDD = 3 V ± 10 %
Row Tone level
Ratio of
Column to Row
tone
Distortion
(Dual tone)
VROW
dBCR
µA
VDD = 2 to 5.5 V
RL = 12 KΩ; Temp = – 30 to 60 °C
VDD = 2 to 5.5 V
dBV
RL = 12 KΩ; Temp = – 30 to 60 °C
THD
VDD = 2 to 5.5 V
1 MHz band
RL = 12 KΩ; Temp = – 30 to 60 °C
%
NOTES:
1. Data includes power consumption for subsystem clock oscillation.
2. When the system clock control register, SCMOD, is set to 1001B, the main system clock oscillation stops and the
subsystem clock is used.
3. Currents in the following circuits are not included: on-chip pull-up resistors, internal LCD voltage dividing resistors, and
output port drive currents.
16-4
S3C7565/P7565
ELECTRICAL DATA
Table 16-3. Main System Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Ceramic
Oscillator
Clock
Configuration
XIN
XOUT
C1
Crystal
Oscillator
XIN
Parameter
Test Condition
Min
Typ
Max
Units
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
0.4
–
6.0
MHz
VDD = 1.8 V to 5.5 V
0.4
–
3
Stabilization time (2)
Stabilization occurs
when VDD is equal to
the minimum
oscillator voltage
range; VDD = 3.0 V
–
–
4
ms
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
0.4
–
6.0
MHz
VDD = 1.8 V to 5.5 V
0.4
–
3
VDD = 3 V
–
–
10
VDD = 1.8 V to 5.5 V
–
–
30
VDD = 2.7 V to 5.5 V
0.4
–
6.0
VDD = 1.8 V to 5.5 V
0.4
–
3
–
83.3
–
1,250
ns
R = 25 kΩ, VDD = 5 V
–
2
–
MHz
R = 40 kΩ, VDD = 3 V
–
1
–
C2
XOUT
C1
C2
Stabilization time (2)
External
Clock
XIN
XOUT
XIN input frequency (1)
XIN input high and low
level width (tXH, tXL)
RC
Oscillator
XIN
XOUT
Frequency
ms
MHz
R
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
16-5
ELECTRICAL DATA
S3C7565/P7565
Table 16-4. Recommended Oscillator Constants
(TA = – 40 °C to + 85 °C)
Manufacturer
TDK
Series
Number (1)
Frequency Range
Load Cap (pF)
Oscillator Voltage
Range (V)
C1
C2
MIN
MAX
Remarks
FCR
M5
3.58 MHz–6.0 MHz
33
33
2.0
5.5
Leaded Type
FCR
MC5
3.58 MHz–6.0 MHz
(2)
(2)
2.0
5.5
On-chip C
Leaded Type
CCR
MC3
3.58 MHz–6.0 MHz
(3)
(3)
2.0
5.5
On-chip C
SMD Type
NOTES:
1. Please specify normal oscillator frequency.
2. On-chip C: 30pF built in.
3. On-chip C: 38pF built in.
Table 16-5. Subsystem Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Crystal
Oscillator
Clock
Configuration
XTIN XTOUT
C1
External
Clock
Parameter
Test Condition
Min
Typ
Max
Units
Oscillation frequency (1) VDD = 1.8 V to 5.5 V
32
32.768
35
kHz
Stabilization time (2)
VDD = 2.7 V to 5.5 V
–
1.0
2
s
VDD = 1.8 V to 5.5 V
–
–
10
XTIN input frequency (1) VDD = 1.8 V to 5.5 V
32
–
100
kHz
XTIN input high and low
level width (tXTL, tXTH)
5
–
15
µs
C2
XTIN XTOUT
Open
–
NOTES:
1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
16-6
S3C7565/P7565
ELECTRICAL DATA
Table 16-6. Input/output Capacitance
(TA = 25 °C, VDD = 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
Capacitance
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
Output
Capacitance
COUT
–
–
15
pF
CIO
–
–
15
pF
I/O Capacitance
Table 16-7. Comparator Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 4.0 V to 5.5 V, VSS = 0 V)
Parameter
Symbol
Condition
Min
Typ
Max
Units
–
–
0
–
VDD
V
Reference Voltage Range
VREF
–
0
–
VDD
V
Input Voltage Accuracy
VCIN
–
–
–
± 150
mV
Input Leakage Current
ICIN, IREF
–
–3
–
3
µA
Input Voltage Range
16-7
ELECTRICAL DATA
S3C7565/P7565
Table 16-8. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Instruction Cycle
Time (note)
TCL0, TCL1 Input
Frequency
Symbol
tCY
f TI0, f TI1
Conditions
Min
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 1.8 V to 5.5 V
1.33
VDD = 2.7 V to 5.5 V
0
64
–
VDD = 1.8 V to 5.5 V
TCL0, TCL1 Input
High, Low Width
SCK Cycle Time
tTIH0, tTIL0
tTIH1, tTIL1
tKCY
MHz
1
VDD = 2.7 V to 5.5 V
0.48
VDD = 1.8 V to 5.5 V
1.8
VDD = 2.7 V to 5.5 V
800
Internal SCK source
650
VDD = 1.8 V to 5.5 V
3200
Internal SCK source; Output
3800
External SCK source
External SCK source
16-8
1.5
–
–
µs
–
–
ns
S3C7565/P7565
ELECTRICAL DATA
Table 16-8. A.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
SCK High, Low
Width
tKH, tKL
VDD = 2.7 V to 5.5 V
325
–
–
ns
–
–
ns
–
–
ns
–
300
ns
External SCK source
Internal SCK source
TkCY/
2–50
VDD = 1.8 V to 5.5 V
1600
Internal SCK source
tKCY/
2–150
External SCK source
SI Setup Time to
SCK High
SI Hold Time to
SCK High
Output Delay for
SCK to SO
Interrupt Input
High, Low Width
RESET Input Low
Width
tSIK
tKSI
tKSO
tINTH, tINTL
tRSL
VDD = 2.7 V to 5.5 V; Input
100
VDD = 2.7 V to 5.5 V; Output
150
VDD = 1.8 V to 5.5 V; Input
150
VDD = 1.8 V to 5.5 V; Output
500
VDD = 2.7 V to 5.5 V; Input
400
VDD = 2.7 V to 5.5 V; Output
400
VDD = 1.8 V to 5.5 V; Input
600
VDD = 1.8 V to 5.5 V; Output
500
VDD = 2.7 V to 5.5 V; Input
–
VDD = 2.7 V to 5.5 V; Output
250
VDD = 1.8 V to 5.5 V; Input
1000
VDD = 2.7 V to 5.5 V; Output
1000
INT0–INT2, INT4, KS0–KS7
10
–
–
µs
Input
10
–
–
µs
NOTE: Unless specified the otherwise, Instruction Cycle Time condition values assume a main system clock (fx) source.
16-9
ELECTRICAL DATA
S3C7565/P7565
Main Os. Freq. (Divided by 4)
CPU Clock
1.5MHz
6MHz
4.2MHz
1.05MHz
0.75kHz
3MHz
15.625kHz
1
2
1.8
3
4
5
6
7
2.7
Supply Voltage (V)
CPU Clock = 1/n x oscillator frequency (n =4, 8 or 64)
Figure 16-1. Standard Operating Voltage Range
Table 16-9. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
VDDDR
–
1.8
–
5.5
V
Data retention supply current
IDDDR
–
0.1
10
µA
Release signal set time
tSREL
0
–
–
µs
Oscillator stabilization wait
time (1)
tWAIT
Released by RESET
–
217 / fx
–
ms
Released by interrupt
–
(2)
–
VDDDR = 1.8 V
–
NOTES:
1. During the oscillator stabilization wait time, all the CPU operations must be stopped to avoid instability that can occur
during the oscillator start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay an execution of CPU instructions during the wait time.
16-10
S3C7565/P7565
ELECTRICAL DATA
TIMING WAVEFORMS
Internal Reset
Operation
~
~
Idle Mode
Stop Mode
Operating
Mode
Data Retention Mode
~
~
VDD
VDDDR
Execution of
STOP Instruction
RESET
tWAIT
tSREL
Figure 16-2. Stop Mode Release Timing When Initiated by RESET
Idle Mode
~
~
Normal
Operating
Mode
Stop Mode
Data Retention Mode
~
~
VDD
VDDDR
Execution of
STOP Instrction
tSREL
tWAIT
Power-down Mode Terminating Signal
(Interrupt Request)
Figure 16-3. Stop Mode Release Timing When Initiated by Interrupt Request
16-11
ELECTRICAL DATA
S3C7565/P7565
0.8 VDD
0.8 VDD
Measurement
Points
0.2 VDD
0.2 VDD
Figure 16-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx
tXL
tXH
XIN
VDD - 0.1 V
0.1 V
Figure 16-5. Clock Timing Measurement at XIN
1/fxt
tXTL
tXTH
XTIN
VDD - 0.1 V
0.1 V
Figure 16-6. Clock Timing Measurement at XTIN
16-12
S3C7565/P7565
ELECTRICAL DATA
1/fTI
tTIL
tTIH
TCL0
0.8 VDD
0.2 VDD
Figure 16-7. TCL Timing
tRSL
RESET
0.2 VDD
Figure 16-8. Input Timing for RESET Signal
16-13
ELECTRICAL DATA
S3C7565/P7565
tINTL
tINTH
INT0, 1, 2, 4
K0 to K7
0.8 VDD
0.2 VDD
Figure 16-9. Input Timing for External Interrupts and Quasi-Interrupts
tKCY
tKL
tKH
SCK
0.8 VDD
0.2 VDD
tSIK
tKSI
0.8 VDD
SI
Input Data
0.2 VDD
tKSO
SO
Output Data
Figure 16-10. Serial Data Transfer Timing
16-14
S3C7565/P7565
17
MECHANICAL DATA
MECHANICAL DATA
This section contains the following information about the device package:
— Package dimensions in millimeters
— Pad diagram
— Pad/pin coordinate data table
23.90 ± 0.3
0-8
0.15
0.10 MAX
100-QFP-1420C
(0.83)
#100
#1
0.30 ± 0.1
+0.10
_0.05
0.65
(0.58)
0.10 MAX
0.80 ± 0.20
14.00 ± 0.2
17.00 ± 0.3
20.00 ± 0.2
O
0.05 MIN
2.65 ± 0.10
3.00 MAX
NOTE: Dimensions are in millimeters.
0.80 ± 0.20
Figure 17-1. 100-QFP Package Dimensions
17-1
MECHANICAL DATA
S3C7565/P7565
NOTES
17-2
S3C7565/P7565
18
S3P7565 OTP
S3P7565 OTP
OVERVIEW
The S3P7565 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C7565
microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data
format.
The S3P7565 is fully compatible with the S3C7565, both in function and in pin configuration. Because of its
simple programming requirements, the S3P7565 is ideal for use as an evaluation chip for the S3C7565.
18-1
S3C7565/P7565
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
S3P7565 OTP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
S3C7565
(100-QFP-1420C)
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
DTMF
P0.0/SCK/K0
P0.1/SO/K1
SDAT/P0.2/SI/K2
SCLK/P0.3/BUZ/K3
VDD/VDD
VSS/VSS
XOUT
XIN
VPP/TEST
XTIN
XTOUT
RESET/RESET
RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/CLO
P2.1/VLC1
P2.2
P3.0/TCLO0
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
P10.3/SEG40
P10.2/SEG41
P10.1/SEG42
P10.0/SEG43
P9.3/SEG44
P9.2/SEG45
P9.1/SEG46
P9.0/SEG47
P8.3/SEG48
P8.2/SEG49
P8.1/SEG50/LCDSY
P8.0/SEG51/LCDCK
P7.3/SEG52/CIN3
P7.2/SEG53/CIN2
P7.1/SEG54/CIN1
P7.0/SEG55/CIN0
P6.3/SEG56/K7
P6.2/SEG57/K6
P6.1/SEG58/K5
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P6.0/SEG59/K4
P5.3/COM15
P5.2/COM14
P5.1/COM13
P5.0/COM12
P4.3/COM11
P4.2/COM10
P4.1/COM9
P4.0/COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
P3.3/TCL1
P3.2/TCL0
P3.1/TCLO1
Figure 18-1. S3P7565 Pin Assignments (100-QFP Package)
18-2
S3C7565/P7565
S3P7565 OTP
Table 18-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P0.2
SDAT
13
I/O
Serial data pin. Output port when reading and input
port when writing. Can be assigned as a Input/pushpull output port.
P0.3
SCLK
14
I/O
Serial clock pin. Input only pin.
TEST
VPP (TEST)
19
I
Power supply pin for EPROM cell writing (indicates
that OTP enters into the writing mode). When 12.5
V is applied, OTP is in writing mode and when 5 V
is applied, OTP is in reading mode. When OTP is
operating, hold GND. (Option)
RESET
RESET
22
I
Chip initialization
VDD/VSS
VDD/VSS
15/16
I
Logic power supply pin. VDD should be tied to + 5 V
during programming.
Table 18-2. Comparison of S3P7565 and S3C7565 Features
Characteristic
S3P7565
S3C7565
Program Memory
16-Kbyte EPROM
16-Kbyte mask ROM
Operating Voltage (VDD)
1.8 V to 5.5 V
1.8 V to 5.5 V
OTP Programming Mode
VDD = 5 V, VPP (TEST) = 12.5V
Pin Configuration
100 QFP
100 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (TEST) pin of the S3P7565, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 18-3 below.
Table 18-3. Operating Mode Selection Criteria
VDD
5V
VPP
(TEST)
REG/MEM
Address
R/W
Mode
5V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
(A15–A0)
NOTE: "0" means Low level; "1" means High level.
18-3
S3P7565 OTP
S3C7565/P7565
Table 18-4. Absolute Maximum Ratings
(TA = 25 °C)
Parameter
Supply Voltage
Symbol
Conditions
VDD
–
Rating
– 0.3 to + 6.5
V
– 0.3 to VDD + 0.3
V
– 0.3 to VDD + 0.3
V
Input Voltage
VI
Output Voltage
VO
–
Output Current High
I OH
One I/O pin active
– 15
All I/O pins active
– 35
One I/O pin active
+ 30 (Peak value)
Output Current Low
I OL
Ports 0–10
Units
mA
mA
+ 15 (note)
Total for ports 0, 2–10
+ 100 (Peak value)
+ 60 (note)
Operating Temperature
Storage Temperature
TA
–
– 40 to + 85
°C
TSTG
–
– 65 to + 150
°C
NOTE: The values for Output Current Low (IOL) are calculated as Peak Value ×
18-4
Duty .
S3C7565/P7565
S3P7565 OTP
Table 18-5. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
–
VDD
V
VIH1
All input pins except those
specified below for VIH2–VIH3
0.7 VDD
VIH2
Ports 0, 1, 2, 6, P3.2, P3.3, and
RESET
0.8 VDD
VDD
VIH3
XIN, XOUT, and XTIN
VDD – 0.1
VDD
VIL1
All input pins except those
specified below for VIL2–VIL3
VIL2
Ports 0, 1, 2, 6, P3.2, P3.3,
and RESET
VIL3
XIN, XOUT, and XTIN
Output High
Voltage
VOH
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
Ports 0, 2–10
VDD – 1.0
–
–
V
Output Low
Voltage
VOL
VDD = 4.5 V to 5.5 V
IOL = 15 mA
–
–
2.0
V
–
–
3
µA
Input High
Voltage
Input Low
Voltage
–
–
0.3 VDD
V
0.2 VDD
0.1
Ports 0, 2–10
Input High
Leakage
Current
Input Low
Leakage
Current
ILIH1
VI = VDD
All input pins except those
specified below for ILIH2
ILIH2
VI = VDD
XIN, XTIN
ILIL1
VI = 0 V
20
–
–
–3
µA
All input pins except RESET,
XIN, XTIN
ILIL2
VI = 0 V
XIN, XTIN
Output High
Leakage
Current
ILOH
VO = VDD
All output pins
–
–
3
µA
Output Low
Leakage
Current
ILOL
VO = 0 V
All output pins
–
–
–3
µA
– 20
18-5
S3P7565 OTP
S3C7565/P7565
Table 18-5. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Pull-up Resistor
RLI
RL2
Conditions
Min
Typ
Max
Units
VI = 0 V; VDD = 5 V,
Port 0–10
25
47
100
kΩ
VDD = 3 V
50
95
200
VI = 0 V; VDD = 5 V, RESET
100
220
400
VDD = 3 V
200
450
800
40
55
70
20
28
35
LCD Voltage
Dividing
RLCD1
Resistor (note)
RLCD2
|VDD–COMi|
Voltage Drop
(i = 0–15)
VDC
VDD = 2.7 V to 5.5 V
– 15 µA per common pin
–
–
120
|VDD–SEGx|
Voltage Drop
(x = 0–59)
VDS
VDD = 2.7 V to 5.5 V
– 15 µA per segment pin
–
–
120
VLCX Output
Voltage
VLC1
VDD = 2.7 V to 5.5 V
LCD clock = 0 Hz
VDD–0.2
VDD
VDD+0.2
VLC2
0.8VDD–0.2
0.8VDD
0.8VDD+0.2
VLC3
0.6VDD–0.2
0.6VDD
0.6VDD+0.2
VLC4
0.4VDD–0.2
0.4VDD
0.4VDD+0.2
VLC5
0.2VDD–0.2
0.2VDD
0.2VDD+0.2
–
NOTE: RLCD1 is the LCD Voltage dividing resistor when LCON.1 = “0”, and RLCD2 is the one when LCON.1 = “1”.
18-6
kΩ
mV
V
S3C7565/P7565
S3P7565 OTP
Table 18-5. D.C. Electrical Characteristics (Concluded)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Supply Current (1)
Symbol
Conditions
Min
Typ
Max
Units
Run mode; VDD = 5 V ± 10 %
(DTMF on) 3.58 MHz X-tal oscillator,
C1 = C2 = 22 pF
–
3.9
7.0
mA
VDD = 3 V ± 10%
–
2.0
4.0
IDD1
IDD2
Run mode;
(DTMF off) VDD = 5 V ± 10 %
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
3.58 MHz
4.1
2.7
8.0
5.0
VDD = 3 V ± 10 %
6.0 MHz
3.58 MHz
1.9
1.2
4.0
2.3
Idle mode;
VDD = 5 V ± 10 %
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
3.58 MHz
1.2
0.9
2.5
1.8
VDD = 3 V ± 10 %
6.0 MHz
3.58 MHz
0.5
0.4
1.5
1.0
IDD3
–
IDD4 (2)
Run mode; VDD = 3 V ± 10 %
32 kHz Crystal oscillator
–
17.5
45
µA
IDD5 (2)
Idle mode; VDD = 3 V ± 10 %
32 kHz Crystal oscillator
–
y
15
µA
Stop mode;
VDD = 5 V ± 10 %
VDD = 3 V ± 10 %
SCMOD = 0000
XTIN = 0 V
–
2.0
0.6
5
3
µA
Stop mode;
VDD = 5 V ± 10 %
VDD = 3 V ± 10 %
SCMOD = 0100
0.2
0.1
3
2
IDD6
Row Tone Level
VROW
VDD = 2 to 5.5 V
RL = 12 KΩ; Temp = – 30 to 60 °C
– 16.0
– 14.0
– 11.0
Ratio of Column to
Row tone
dBCR
VDD = 2 to 5.5 V
RL = 12 KΩ; Temp = – 30 to 60 °C
1
2
3
Distortion
(Dual tone)
THD
VDD = 2 to 5.5 V
1 MHz band
RL = 12 KΩ; Temp = – 30 to 60 °C
–
–
5
dBV
%
NOTES:
1. Data includes power consumption for subsystem clock oscillation.
2. When the system clock control register, SCMOD, is set to 1001B, the main system clock oscillation stops and the
subsystem clock is used.
3. Currents in the following circuits are not included: on-chip pull-up resistors, internal LCD voltage dividing resistors, and
output port drive currents.
18-7
S3P7565 OTP
S3C7565/P7565
Table 18-6. Main System Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Ceramic
Oscillator
Clock
Configuration
XIN
XOUT
C1
Crystal
Oscillator
XIN
Parameter
Min
Typ
Max
Unit
s
VDD = 2.7 V to 5.5 V
0.4
–
6.0
MHz
VDD = 1.8 V to 5.5 V
0.4
–
3.0
Stabilization time (2)
Stabilization occurs
when VDD is equal to
the minimum
oscillator voltage
range; VDD = 3.0 V
–
–
4
ms
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
0.4
–
6.0
MHz
VDD = 1.8 V to 5.5 V
0.4
–
3.0
VDD = 3 V
–
–
10
VDD = 1.8 V to 5.5 V
–
–
30
VDD = 2.7 V to 5.5 V
0.4
–
6.0
VDD = 1.8 V to 5.5 V
0.4
–
3.0
XIN input high and low
level width (tXH, tXL)
–
83.3
–
1,250
ns
Frequency
R = 25 kΩ, VDD = 5 V
–
2
–
MHz
R = 40 kΩ, VDD = 3 V
–
1
–
Oscillation frequency (1)
C2
XOUT
C1
C2
Stabilization time (2)
External
Clock
RC
Oscillator
Test Condition
XIN
XOUT
XIN
XOUT
XIN input frequency (1)
R
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
18-8
ms
MHz
S3C7565/P7565
S3P7565 OTP
Table 18-7. Subsystem Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Configuration
Crystal
Oscillator
XTIN XTOUT
C1
External
Clock
Parameter
Test Condition
Min
Typ
Max
Units
Oscillation frequency (1)
VDD = 1.8 V to 5.5 V
32
32.768
35
kHz
Stabilization time (2)
VDD = 2.7 V to 5.5 V
–
1.0
2
s
VDD = 1.8 V to 5.5 V
–
–
10
XTIN input frequency (1)
VDD = 1.8 V to 5.5 V
32
–
100
kHz
XTIN input high and low
level width (tXTL, tXTH)
–
5
–
15
µs
C2
XTIN XTOUT
Open
NOTES:
1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
Table 18-8. Input/Output Capacitance
(TA = 25 °C, VDD = 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
Capacitance
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
Output
Capacitance
COUT
–
–
15
pF
CIO
–
–
15
pF
I/O Capacitance
18-9
S3P7565 OTP
S3C7565/P7565
Main Os. Freq. (Divided by 4)
CPU Clock
1.5MHz
6MHz
4.2MHz
1.05MHz
0.75kHz
3MHz
15.625kHz
1
2
1.8
3
4
5
6
7
2.7
Supply Voltage (V)
CPU Clock = 1/n x oscillator frequency (n =4, 8 or 64)
Figure 18-2. Standard Operating Voltage Range
18-10