S3C7544/P7544 1 PRODUCT OVERVIEW PRODUCT OVERVIEW OVERVIEW The S3C7544 single-chip CMOS microcontroller is designed for high-performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With a versatile 8-bit timer/counter and a D/A converter, the S3C7544 offers an excellent design solution for a wide variety of telecommunication applications. Up to 17 pins of the 24-pin SDIP package can be dedicated to I/O. Four vectored interrupts provide fast response to internal and external events. In addition, the S3C7544’s advanced CMOS technology has realized substantially lower power consumption with a wide operating voltage range — all at a substantially lower cost. OTP The S3C7544 microcontroller is also available in OTP (One Time Programmable) version, S3P7544. S3P7544 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM. The S3P7544 is comparable to S3C7544, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C7544/P7544 FEATURES SUMMARY Memory Bit Sequential Carrier • 512 × 4-bit RAM • • 4096 × 8-bit ROM I/O Pins • 17 pins I/O • N-channel open-drain I/O: 8 pins 8-Bit Basic Timer • Programmable interval timer • Watchdog timer Supports 16-bit serial data transfer in arbitrary format Power-Down Modes • Idle mode (only CPU clock stops) • Stop mode (system clock stops) Oscillation Sources • Crystal, or ceramic for system clock • Crystal, ceramic: 0.4–6.0 MHz • CPU clock divider circuit (by 4, 8, or 64) Interval 8-Bit Timer/Counter • Programmable interval timer • External event counter function • Timer/counter clock output to TCLO0 pin Buzzer Output • Four frequency output to BUZ pin Instruction Execution Times • 0.95, 1.91, and 15.3 µs at 4.19 MHz • 0.67, 1.33, 10.7 µs at 6.0 MHz Operating Temperature • – 40 °C to 85 °C D/A Converter Operating Voltage Range • • 1.8 V to 5.5 V (at 3 MHz) • 2.7 V to 5.5 V (at 6 MHz) 8-bit D/A converter Interrupts • Two external interrupt vectors Package Types • Two internal interrupt vectors • 24-pin SOP-375 • One quasi-interrupt • 24-pin SDIP-300 Memory-Mapped I/O Structure • 1-2 Data memory bank 15 S3C7544/P7544 PRODUCT OVERVIEW BLOCK DIAGRAM Watchdog Timer INT0, INT1 8-bit Timer/ Counter DAO RESET XIN Basic Timer Interrupt Control Block Clock D/A Converter Internal Interrupts P4.0–P4.3 I/O Port 4 Instruction Decoder P5.0–P5.3 XOUT I/O Port 5 Arithmetic Logic Unit 512 x 4-bit Data Memory Stack Pointer Buzzer Program Counter Program Status Word I/O Port 0 P0.0/INT0 P0.1/INT1 P0.2/KS0 P0.3/KS1 I/O Port 1 P1.0/TCL0 P1.1/TCLO0 P1.2/CLO P1.3/BUZ I/O Port 2 P2.0 Flags 4 K byte Program Memory Figure 1-1. S3C7544 Simplified Block Diagram 1-3 PRODUCT OVERVIEW S3C7544/P7544 PIN ASSIGNMENTS S3C7544 1 2 3 4 5 6 7 8 9 10 11 12 24 SOP-375 24 SDIP-300 VSS XOUT XIN TEST P0.0/INT0 DAO P0.1/INT1 RESET P0.2/KS0 P0.3/KS1 P1.0/TCL0 P1.1/TCLO0 24 23 22 21 20 19 18 17 16 15 14 13 VDD P5.3 P5.2 P5.1 P5.0 P4.3 P4.2 P4.1 P4.0 P2.0 P1.3/BUZ P1.2/CLO Figure 1-2. S3C7544 Pin Assignment Diagrams 1-4 S3C7544/P7544 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. S3C7544 Pin Descriptions Pin Name Pin Type Description Share Pin P0.0 P0.1 P0.2 P0.3 I 4-bit I/O port. 1- or 4-bit read/write and test is possible. Pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. Pins are individually configurable as input or output. INT0 INT1 KS0 KS1 P1.0 P1.1 P1.2 P1.3 I/O 4-bit I/O port. 1- or 4-bit read/write and test is possible. Pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. Pins are individually configurable as input or output. TCL0 TCLO0 CLO BUZ P2.0 I/O 1-bit I/O port. 1- or 4-bit read/write and test is possible. Pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. – P4.0–P4.3 I/O 4-bit I/O port. 1- or 4-bit read/write and test is possible. Pins are individually configurable as input or output. Pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. The N-channel open drain or push-pull output can be selected by software (1-bit unit). – INT0 I/O External interrupts with rising/falling edge detection P0.0 INT1 I/O External interrupts with rising/falling edge detection P0.1 KS0 KS1 I/O Quasi-interrupt input with falling edge detection P0.2 P0.3 TCL0 I/O External clock input for timer/counter P1.0 TCLO0 I/O Timer/counter clock output P1.1 CLO I/O CPU clock output P1.2 BUZ I/O 0.5, 1, 2, or 4 kHz frequency output at 4.19 MHz for buzzer sound P1.3 DAO O 8-bit D/A converter output – VDD – Main power supply – VSS – Ground – RESET I Reset signal – TEST I Chip test input pin. Hold GND when the device is operating. – XIN, XOUT – Crystal, ceramic oscillator signal for system clock – P5.0–P5.3 1-5 PRODUCT OVERVIEW S3C7544/P7544 Table 1-2. Overview of S3C7544 Pin Data SDIP Pin Numbers Share Pins I/O Type Reset Value Circuit Type VSS – – – – XOUT, XIN – – – – TEST – I – – INT0, INT1 I/O Input D-4 – I – B P0.2 P0.3 KS0 KS1 I/O Input D-4 P1.0 P1.1 P1.2 P1.3 TCL0 TCLO0 CLO BUZ I/O Input D-2 P2.0 – I/O Input D-2 DAO – O Output – P4.0–P4.3 – I/O Input E-2 P5.0–P5.3 – I/O Input E-2 VDD – – – – P0.0, P0.1 RESET 1-6 S3C7544/P7544 PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD VDD P-Channel P-Channel Data IN Out N -Channel N -Channel Output Disable Figure 1-3. Pin Circuit Type A Figure 1-5. Pin Circuit Type C VDD VDD Pull-up Resistor Pull-up Enable Data IN Output Disable P-Channel Circuit Type C In/Out Schmitt Trigger Figure 1-4. Pin Circuit Type B Figure 1-6. Pin Circuit Type D-2 1-7 PRODUCT OVERVIEW S3C7544/P7544 VDD VDD PNE Pull-up Enable Pull-Up Resistor VDD Resistor Enable P-Channel In/Out Data Output Disable Circuit Type C Data In/Out Figure 1-7. Pin Circuit Type D-4 1-8 Output Disable Figure 1-8. Pin Circuit Type E-2 S3C7544/P7544 14 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, S3C7544 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: Standard Electrical Characteristics — Absolute maximum ratings — D.C. electrical characteristics — Main system clock oscillator characteristics — Subsystem clock oscillator characteristics — I/O capacitance — A.C. electrical characteristics — Operating voltage range Miscellaneous Timing Waveforms — A.C timing measurement point — Clock timing measurement at Xin — Clock timing measurement at XTin — TCL timing — Input timing for RESET — Input timing for external interrupts — Serial data transfer timing Stop Mode Characteristics and Timing Waveforms — RAM data retention supply voltage in stop mode — Stop mode release timing when initiated by RESET — Stop mode release timing when initiated by an interrupt request 14-1 ELECTRICAL DATA S3C7544/P7544 Table 14-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Supply Voltage Symbol Conditions Rating Units VDD – – 0.3 to + 6.5 V – 0.3 to VDD + 0.3 V – 0.3 to VDD + 0.3 V One I/O port active –5 mA All I/O ports active – 35 One I/O port active + 30 (peak) Input Voltage VI Output Voltage VO Output Current High I OH I OL Output Current Low All I/O ports – mA + 15 (note) All I/O ports active + 100 (peak) + 60 (note) Operating Temperature TA – – 40 to + 85 °C Storage Temperature Tstg – – 65 to + 150 °C NOTE: The values for output current low (IOL) are calculated as peak value × Duty . Table 14-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Input Low Voltage 14-2 Symbol Conditions Min Typ Max Units V VIH1 All input pins except VIH2–VIH3 0.7 VDD – VDD VIH2 P0 and RESET 0.8 VDD – VDD VIH3 XIN and XOUT VDD – 0.1 – VDD VIL1 All input pins except VIH2–VIH3 – – 0.3 VDD VIL2 P0 and RESET VIL3 XIN and XOUT 0.2 VDD 0.1 V S3C7544/P7544 ELECTRICAL DATA Table 14-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Symbol Output High Voltage VOH Output Low Voltage VOL1 Conditions VDD = 4.5 V to 5.5 V Min Typ Max Units VDD – 1.0 – – V – – 2 V IOH = – 1 mA VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 4, 5 VOL2 VDD = 1.8 V to 5.5 V IOL = 1.6 mA 0.4 VDD = 4.5V to 5.5 V 2 IOL = 4 mA All out ports except ports 4, 5 VDD = 1.8 V to 5.5 V IOL = 1.6 mA Input High Leakage Current Input Low Leakage Current ILIH1 VIN = VDD All input pins except XIN and XOUT ILIH2 VIN = VDD XIN and XOUT ILIL1 VIN = 0 V All input pins except XIN, XOUT 0.6 – – 3 µA 20 – – –3 µA and RESET ILIL2 VIN = 0 V XIN and XOUT Output High Leakage Current ILOH VO = VDD All output pins – – 3 µA Output Low Leakage Current ILOL VO = 0 V – – –3 µA Pull-up Resistor RL1 VDD = 5 V; VI = 0 V except RESET 25 45 100 kΩ VDD = 3 V 50 90 200 VDD = 5 V; VI = 0 V; RESET 100 220 400 VDD = 3 V 200 450 800 – 20 All output pins RL2 14-3 ELECTRICAL DATA S3C7544/P7544 Table 14-2. D.C. Electrical Characteristics (Concluded) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 (DAC on) IDD2 (DAC off) Conditions Run mode; VDD = 5.0 V ± 10% Crystal oscillator; C1 = C2 = 22pF Run mode; VDD = 5.0 V ± 10% Max – 3.4 10.0 2.7 8.0 2.3 8.0 4.19MHz 1.7 5.5 6.0MHz 1.1 4.0 4.19MHz 0.8 3.0 0.7 2.5 4.19MHz 0.5 1.8 6.0MHz 0.3 1.5 4.19MHz 0.2 1.0 0.2 3.0 0.1 2.0 4.19MHz 6.0MHz Crystal oscillator; C1 = C2 = 22pF Idle mode; VDD = 5.0 V ± 10% 6.0MHz Crystal oscillator; C1 = C2 = 22pF VDD = 3 V ± 10% IDD4 Typ 6.0MHz VDD = 3 V ± 10% IDD3 Min Stop mode; VDD = 5.0 V ± 10% – – – Stop mode; VDD = 3.0 V ± 10% NOTES: 1. D.C. electrical values for supply current (IDD1 to IDD3) do not include the current drawn through internal pull-up 2. resistors. IDD1 typical values are measured when DADATA register value is 055H. Main Osc. Freq. CPU CLOCK 1.5 MHz 6 MHz 0.75 MHz 3 MHz 15.625 kHz 400 kHz 1 1.8 2 2.7 3 4 5 6 7 SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64) Figure 14-1. Standard Operating Voltage Range 14-4 Units mA mA mA µA S3C7544/P7544 ELECTRICAL DATA Table 14-3. Oscillators Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration Xin Xout C1 Crystal Oscillator Xin External Clock Xin Oscillation frequency (1) Test Condition Min Typ Max Units VDD = 2.7 V to 5.5 V 0.4 – 6.0 MHz VDD = 1.8 V to 5.5 V 0.4 – 3 – – 4 ms MHz C2 Xout C1 Parameter Stabilization time (2) VDD = 3.0 V Oscillation frequency (1) VDD = 2.7 V to 5.5 V 0.4 – 6.0 VDD = 1.8 V to 5.5 V 0.4 – 3 – – 10 ms MHz C2 Xout Stabilization time (2) VDD = 3.0 V XIN input frequency (1) VDD = 2.7 V to 5.5 V 0.4 – 6.0 VDD = 1.8 V to 5.5 V 0.4 – 3 83.3 – 1250 XIN input high and low level width (tXH, tXL) – ns NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated. 14-5 ELECTRICAL DATA S3C7544/P7544 Table 14-4. Recommended Oscillator Constants (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Manufacturer TDK Series Number (1) Frequency Range Load Cap (pF) Oscillator Voltage Range (V) C1 C2 MIN MAX Remarks M5 3.58 MHz–6.0 MHz 33 33 2.0 5.5 Leaded Type FCR MC5 3.58 MHz–6.0 MHz (2) (2) 2.0 5.5 On-chip C Leaded Type CCR MC3 3.58 MHz–6.0 MHz (3) (3) 2.0 5.5 On-chip C SMD Type FCR NOTES: 1. Please specify normal oscillator frequency. 2. On-chip C: 30pF built in. 3. On-chip C: 38pF built in. Table 14-5. Input/Output Capacitance (TA = 25 °C, VDD = 0 V ) Parameter Symbol Condition Min Typ Max Units Input Capacitance CIN f = 1 MHz; Unmeasured pins are returned to VSS – – 15 pF Output Capacitance COUT 15 pF CIO 15 pF I/O Capacitance Table 14-6. D/A Converter Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 3.5 V to 5.5 V, VSS = 0 V) Parameter Symbol Condition Min Typ Max Units Resolution – – – – 8 bits Absolute Accuracy – –3 – 3 LSB DLE –1 – 1 LSB Setup Time tsu – – 5 µs Output Resistance RO 4.5 5 5.5 KΩ Differential Linearity Error 14-6 S3C7544/P7544 ELECTRICAL DATA Table 14-7. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Symbol tCY Instruction Cycle Time f TI TCL0 Input Frequency Conditions Min Typ Max Units VDD = 2.7 V to 5.5 V 0.67 – 64 µs VDD = 1.8 V to 5.5 V 1.33 VDD = 2.7 V to 5.5 V 0 – 1.5 MHz 1 MHz – – µs VDD = 1.8 V to 5.5 V TCL0 Input High, Low Width Interrupt Input High, Low Width tTIH, tTIL tINTH, tINTL RESET Input Low Width tRSL VDD = 2.7 V to 5.5 V 0.48 VDD = 1.8 V to 5.5 V 1.8 INT0, INT1, KS0–KS1 10 – – µs Input – – 10 µs Table 14-8. RAM Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR – 1.8 – 5.5 V Data retention supply current IDDDR – 0.1 10 µA Release signal set time tSREL 0 – – µs Oscillator stabilization wait time (1) tWAIT Released by RESET – 217/fx – ms Released by interrupt – (2) – ms VDDDR = 1.8 V – NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay the execution of CPU instructions during the wait time. 14-7 ELECTRICAL DATA S3C7544/P7544 TIMING WAVEFORMS ~ INTERNAL RESET OPERATION IDLE MODE OPERATING MODE STOP MODE DATA RETENTION MODE ~ VDD V DDDR RESET EXECUTION OF STOP INSTRUCTION tWAIT t SREL Figure 14-2. Stop Mode Release Timing When Initiated by RESET ~ IDLE MODE NORMAL OPERATING MODE STOP MODE ~ DATA RETENTION VDD VDDDR EXECUTION OF STOP INSTRUCTION POWER-DOWN MODE TERMINATING (INTERRUPT REQUEST) tSREL t WAIT Figure 14-3. Stop Mode Release Timing When Initiated by Interrupt Request 14-8 S3C7544/P7544 ELECTRICAL DATA 0.8 V DD 0.2 V DD MEASUREMENT POINTS 0.8 VDD 0.2 VDD Figure 14-4. A.C. Timing Measurement Points (Except for XIN) 1/f x tXL t XH XIN VDD – 0.1 V 0.1 V Figure 14-5. Clock Timing Measurement at XIN 14-9 ELECTRICAL DATA S3C7544/P7544 1 / f TI tTIL tTIH TCL 0.7 V DD 0.3 V DD Figure 14-6. TCL Timing tRSL RESET 0.2 V DD Figure 14-7. Input Timing for RESET Signal tINTL INT0, 1 KS0 to KS1 t INTH 0.8 VDD 0.2 V DD Figure 14-8. Input Timing for External Interrupts 14-10 S3C7544/P7544 MECHANICAL DATA 15 MECHANICAL DATA This section contains the following information about the device package: — Package dimensions in millimeters — Pad diagram — Pad/pin coordinate data table 0 ~ 15 ° 16 10.16 30-SDIP-400 0.56 ± 0.1 1.12 ± 0.1 1.778 5.08MAX (1.30) 3.30 ± 0.3 27.48 ± 0.2 3.81 ± 0.2 15 0.51MIN #1 0.25 +0.1 – 0.0 5 8.94 ± 0.2 30 NOTE: Typical dimensions are in millimeters. Figure 15-1. 30-SDIP-400 Package Dimensions 15–1 S3C7544/P7544 S3P7544 OTP 16 S3P7544 OTP OVERVIEW The S3P7544 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C7544 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P7544 is fully compatible with the S3C7544, both in function and in pin configuration. Because of its simple programming requirements, the S3P7544 is ideal for use as an evaluation chip for the S3C7544. S3P7544 1 2 3 4 5 6 7 8 9 10 11 12 24 SOP-375 24 SDIP-300 VSS/VSS XOUT XIN VPP/TEST P0.0/INT0 DAO P0.1/INT1 RESET /RESET P0.2/KS0 P0.3/KS1 P1.0/TCL0 P1.1/TCLO0 24 23 22 21 20 19 18 17 16 15 14 13 VDD /VDD P5.3/ SCLK P5.2/ SDAT P5.1 P5.0 P4.3 P4.2 P4.1 P4.0 P2.0 P1.3/BUZ P1.2/CLO Figure 16-1. S3P7544 Pin Assignments (24 SOP-375, 24 SDIP-300 Package) 16-1 S3P7544 OTP S3C7544/P7544 Table 16-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P5.2 SDAT 22 I/O Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input / push-pull output port. P5.3 SCLK 23 I/O Serial clock pin. Input only pin. TEST TEST 4 I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Hold GND when OTP is operating. RESET RESET 8 I Chip initialization VDD/VSS VDD/VSS 24/1 – Logic power supply pin. VDD should be tied to +5 V during programming. NOTE: ( ) means the 32-SOP OTP pin number. Table 16-2. Comparison of S3P7544 and S3C7544 Features Characteristic S3P7544 S3C7544 Program Memory 4 K-byte EPROM 4 K-byte mask ROM Operating Voltage (VDD) 1.8 V (3 MHz) to 5.5 V 1.8 V (3 MHz) to 5.5 V OTP Programming Mode VDD = 5 V, VPP (TEST) = 12.5 V Pin Configuration 24 SOP, 24 SDIP 24 SOP, 24 SDIP EPROM Programmability User Program one time Programmed at the factory – OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3P7544, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-3 below. Table 16-3. Operating Mode Selection Criteria VDD VPP (TEST) REG/ MEM Address (A15-A0) R/W 5V 5V 0 0000H 1 EPROM read 12.5 V 0 0000H 0 EPROM program 12.5 V 0 0000H 1 EPROM verify 12.5 V 1 0E3FH 0 EPROM read protection NOTE: "0" means Low level; "1" means High level. 16-2 Mode S3C7544/P7544 S3P7544 OTP OTP ELECTRICAL DATA Table 16-4. Absolute Maximum Ratings (TA = 25 °C) Parameter Supply Voltage Symbol Conditions Rating Units VDD – – 0.3 to + 6.5 V – 0.3 to VDD + 0.3 V – 0.3 to VDD + 0.3 V One I/O port active –5 mA All I/O ports active – 35 One I/O port active + 30 (peak) Input Voltage VI Output Voltage VO Output Current High I OH Output Current Low I OL All I/O ports – mA + 15 (note) All I/O ports active + 100 (peak) + 60 (note) Operating Temperature TA – – 40 to + 85 °C Storage Temperature Tstg – – 65 to + 150 °C NOTE: The values for output current low (IOL) are calculated as peak value × Duty . Table 16-5. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Input Low Voltage Symbol Conditions Min Typ Max Units V VIH1 All input pins except VIH2–VIH3 0.7 VDD – VDD VIH2 P0 and RESET 0.8 VDD – VDD VIH3 XIN and XOUT VDD – 0.1 – VDD VIL1 All input pins except VIH2–VIH3 – – 0.3 VDD VIL2 P0 and RESET VIL3 XIN and XOUT V 0.2 VDD 0.1 16-3 S3P7544 OTP S3C7544/P7544 Table 16-5. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Symbol Output High Voltage VOH Output Low Voltage VOL1 Conditions VDD = 4.5 V to 5.5 V Min Typ Max Units VDD – 1.0 – – V – – 2 V IOH = – 1 mA VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 4, 5 VOL2 VDD = 1.8 V to 5.5 V IOL = 1.6 mA 0.4 VDD = 4.5V to 5.5 V 2 IOL = 4 mA All out ports except ports 4, 5 VDD = 1.8 V to 5.5 V IOL = 1.6 mA Input High Leakage Current Input Low Leakage Current ILIH1 VIN = VDD All input pins except XIN and XOUT ILIH2 VIN = VDD XIN and XOUT ILIL1 VIN = 0 V All input pins except XIN, XOUT 0.6 – – 3 µA 20 – – –3 µA and RESET ILIL2 VIN = 0 V XIN and XOUT Output High Leakage Current ILOH VO = VDD All output pins – – 3 µA Output Low Leakage Current ILOL VO = 0 V – – –3 µA Pull-up Resistor RL1 VDD = 5 V; VI = 0 V except RESET 25 50 100 kΩ VDD = 3 V 50 100 200 VDD = 5 V; VI = 0 V; RESET 100 250 400 VDD = 3 V 200 500 800 All output pins RL2 16-4 – 20 S3C7544/P7544 S3P7544 OTP Table 16-5. D.C. Electrical Characteristics (Concluded) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 (DAC on) IDD2 (DAC off) Conditions Min Typ Max – 3.4 10.0 2.7 8.0 2.3 8.0 4.19MHz 1.7 5.5 6.0MHz 1.1 4.0 4.19MHz 0.8 3.0 0.7 2.5 4.19MHz 0.5 1.8 6.0MHz 0.3 1.5 4.19MHz 0.2 1.0 0.2 3.0 0.1 2.0 Run mode; VDD = 5.0 V ± 10% 6.0MHz Crystal oscillator; C1 = C2 = 22pF 4.19MHz Run mode; VDD = 5.0 V ± 10% 6.0MHz Crystal oscillator; C1 = C2 = 22pF VDD = 3 V ± 10% IDD3 Idle mode; VDD = 5.0 V ± 10% 6.0MHz Crystal oscillator; C1 = C2 = 22pF VDD = 3 V ± 10% IDD4 Stop mode; VDD = 5.0 V ± 10% – – – Stop mode; VDD = 3.0 V ± 10% Units mA mA mA µA NOTES: 1. D.C. electrical values for supply current (IDD1 to IDD3) do not include the current drawn through internal pull-up 2. resistors. IDD1 typical values are measured when DADATA register value is 055H . Main Osc. Freq. CPU CLOCK 1.5 MHz 6 MHz 0.75 MHz 3 MHz 15.625 kHz 400 kHz 1 1.8 2 2.7 3 4 5 6 7 SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64) Figure 16-2. Standard Operating Voltage Range 16-5 S3P7544 OTP S3C7544/P7544 Table 16-6. Oscillators Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration Xin Xout C1 Crystal Oscillator Xin External Clock Xin Test Condition Min Typ Max Units Oscillation frequency (1) VDD = 2.7 V to 5.5 V 0.4 – 6.0 MHz VDD = 1.8 V to 5.5 V 0.4 – 3 – – 4 ms MHz C2 Xout C1 Parameter Stabilization time (2) VDD = 3.0 V Oscillation frequency (1) VDD = 2.7 V to 5.5 V 0.4 – 6.0 VDD = 1.8 V to 5.5 V 0.4 – 3 – – 10 ms MHz C2 Xout Stabilization time (2) VDD = 3.0 V XIN input frequency (1) VDD = 2.7 V to 5.5 V 0.4 – 6.0 VDD = 1.8 V to 5.5 V 0.4 – 3 – 83.3 – 1250 XIN input high and low level width (tXH, tXL) NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated. 16-6 ns S3C7544/P7544 S3P7544 OTP Table 16-7. Input/Output Capacitance (TA = 25 °C, VDD = 0 V ) Parameter Symbol Condition Min Typ Max Units Input Capacitance CIN f = 1 MHz; Unmeasured pins are returned to VSS – – 15 pF Output Capacitance COUT 15 pF CIO 15 pF I/O Capacitance Table 16-8. Comparator Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 3.5 V to 5.5 V, VSS = 0 V) Parameter Symbol Condition Min Typ Max Units Resolution – – – – 8 bits Absolute Accuracy – –3 – 3 LSB DLE –1 – 1 LSB Setup Time tsu – – 5 µs Output Resistance RO 4.5 5 5.5 KΩ Min Typ Max Units VDD = 2.7 V to 5.5 V 0.67 – 64 µs VDD = 1.8 V to 5.5 V 1.33 VDD = 2.7 V to 5.5 V 0 – 1.5 MHz 1 MHz – – µs Differential Linearity Error Table 16-9. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time TCL0 Input Frequency Symbol tCY f TI Conditions VDD = 1.8 V to 5.5 V TCL0 Input High, Low Width Interrupt Input High, Low Width RESET Input Low Width tTIH, tTIL tINTH, tINTL tRSL VDD = 2.7 V to 5.5 V 0.48 VDD = 1.8 V to 5.5 V 1.8 INT0, INT1, KS0–KS1 10 – – µs Input – – 10 µs 16-7 S3P7544 OTP S3C7544/P7544 Table 16-10. RAM Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR – 1.8 – 5.5 V Data retention supply current IDDDR – 0.1 10 µA Release signal set time tSREL 0 – – µs Oscillator stabilization wait time (1) tWAIT Released by RESET – 217/fx – ms Released by interrupt – (2) – ms VDDDR = 1.8 V – NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay the execution of CPU instructions during the wait time. 16-8