SAMSUNG KS57P21632

KS57C21632/P21632
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
OVERVIEW
The KS57C21632 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With an up-to-896-dot LCD direct drive capability, and flexible 8-bit timer/counters, the KS57C21632 offers an
excellent design solution for a high-end LCD game.
Up to 12 pins of the 100-pin QFP package can be dedicated to I/O. Seven vectored interrupts provide fast
response to internal and external events. In addition, the KS57C21632's advanced CMOS technology provides for
low power consumption.
OTP
The KS57C21632 microcontroller is also available in OTP (One Time Programmable) version, KS57P21632.
KS57P21632 microcontroller has an on-chip 32 K-byte one-time-programmable EPROM instead of masked ROM.
The KS57P21632 is comparable to KS57C21632, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
KS57C21632/P21632
FEATURES
Memory
Interrupts
•
768 × 4-bit RAM (excluding LCD display RAM)
•
Three Internal vectored interrupt
•
32,768 × 8-bit ROM
•
Four external vectored interrupts
•
Two quasi-interrupts
12 I/O Pins
•
I/O: 12 pins
Memory-Mapped I/O Structure
•
Data memory bank 15
LCD Controller/Driver
56 segments and 16 common terminals
Power-Down Modes
(8, 12 and 16 common selectable)
•
Idle mode (only CPU clock stops)
•
Capacitor bias for LCD output.
•
Stop mode (main system oscillation stops)
•
Voltage booster and regulator
•
Subsystem clock stop mode
•
All dots can be switched on/off
•
Oscillation Sources
8-bit Basic Timer
•
Crystal, ceramic, or RC for main system clock
•
4 interval timer functions
•
Crystal oscillator for subsystem clock
•
Watch-dog timer
One 16-bit Timer/Counter 1
•
Main system clock frequency: 0.4-4.19 MHz
•
Subsystem clock frequency: 32.768 kHz
•
CPU clock divider circuit (by 4, 8, or 64)
•
Programmable 16-bit timer
•
Arbitrary clock output (TCLO1)
Instruction Execution Times
•
Inverted clock output (TCLO1)
•
0.95, 1.91, 15.3 µs at 4.19 MHz (main)
•
Configurable two 8-bit timer/counters
•
122 µs at 32.768 kHz (subsystem)
Watch Timer
Operating Temperature
•
Time interval generation: 0.5 s, 3.9 ms
at 32768 Hz
•
•
Four frequency outputs to BUZ pin and BUZ pin
Operating Voltage Range
•
Clock source generation for LCD
•
– 40 °C to 85 °C
2.2 V to 3.4 V (0.4 MHz to 4.19 MHz)
Battery Level Detector
Package Type
•
Programmable low voltage detector
•
•
One criteria voltage (2.4 V)
1-2
100-pin QFP or pellet
KS57C21632/P21632
PRODUCT OVERVIEW
BLOCK DIAGRAM
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
I/O Port 1
P0.3/BUZ/K3
P0.2/ BUZ/K2
P0.1/TCLO1/K1
P0.0/TCLO1/K0
I/O Port 0
P2.0/CLO
P2.1/TCL1
P2.2
P2.3
8-bit Timer
Counter 1A
8-bit Timer
Counter 1B
RESET
XIN XOUT
XTIN XTOUT
Interrupt
Control
Block
Clock
Internal
Interrupts
I/O Port 2
Instruction Decoder
16-bit
Timer
Counter 1
Arithmetic
and
Logic Unit
768 x 4-bit
Data
Memory
Basic
(Watchdog)
Timer
Instruction
Register
Program
Counter
Program
Status Word
Watch
Timer
Voltage
Regulator/
Booster
LCD Driver/
Controller
Stack
Pointer
TEST 2
CA
CB
SEG0-SEG55
COM0-COM15
VLC1-VLC5
Battery
Level
Detector
32-Kbyte
Program
Memory
Figure 1-1. KS57C21632 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
KS57C21632/P21632
PIN ASSIGNMENTS
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VLC1
VLC2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
100-QFP 1420 C
RESET
CLO/P2.0
TCL1/P2.1
P2.2
P2.3
COM15
COM14
COM13
COM12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
KS57C21632
VLC3
VLC4
VLC5
CA
CB
TEST2
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
BUZ/P0.3/K3
BUZ/P0.2/K2
TCLO1/P0.1/K1
TCLO1/P0.0/K0
VDD
VSS
XOUT
XIN
TEST1
XTIN
XTOUT
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG18
SEG19
SEG21
SEG22
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
Figure 1-2. KS57C21632 100-QFP Pin Assignment Diagram
1-4
KS57C21632/P21632
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. KS57C21632 Pin Descriptions
Pin Type
Description
Number
Share Pin
P0.0
P0.1
P0.2
P0.3
Pin Name
I/O
4-bit I/O port.
1-bit and 4-bit read/write and test are possible.
Individual pins are software configurable as input or
output.
Individual pins are software configurable as opendrain or push-pull output.
Individual pull-up resistors are software assignable;
pull-up resistors are automatically disabled for output
pins.
14
13
12
11
TCLO1/K0
TCLO1/K1
BUZ/K2
BUZ/K3
P1.0
P1.1
P1.2
P1.3
I/O
Same as port 0
10
9
8
7
INT0
INT1
INT2
INT4
P2.0
P2.1
P2.2
P2.3
I/O
Same as port 0
23
24
25
26
CLO
TCL1
INT0, INT1
I/O
External interrupts. The triggering edge for INT0 and
INT1 is selectable.
10, 9
P1.0, P1.1
INT2
I/O
Quasi-interrupt with detection of rising or falling
edges.
8
P1.2
INT4
I/O
External interrupt with detection of rising and falling
edges.
7
P1.3
BUZ
I/O
2 kHz, 4 kHz, 8 kHz or 16 kHz frequency output for
buzzer signal.
11
P0.3/K3
BUZ
I/O
Inverted BUZ signal
12
P0.2/K2
CLO
I/O
Clock output
23
P2.0
TCL1
I/O
External clock input for timer/counter 1
24
P2.1
TCLO1
I/O
Timer/counter 1 inverted clock output
13
P0.1/K1
TCLO1
I/O
Timer/counter 1 clock output
14
P0.0/K0
COM0–COM15
O
LCD common signal output
42-27
–
SEG0–SEG55
O
LCD segment signal output
98-43
–
1-5
PRODUCT OVERVIEW
KS57C21632/P21632
Table 1-1. KS57C21632 Pin Descriptions (Continued)
Pin Name
K0–K3
Pin Type
I/O
Description
External interrupt (triggering edge is selectable)
Number
Share Pin
14–11
P0.0–P0.3
VDD
–
Main power supply
15
–
VSS
–
Ground
16
–
RESET
I
Reset signal
22
–
CA, CB
–
Capacitor terminal for voltage boosting
4, 5
–
VCL1–VCL2
VCL3–VCL5
–
LCD power supply
99–100
1–3
–
TEST2
I
Test input (must be connected VSS)
6
–
XIN, XOUT
–
Crystal, ceramic or RC oscillator pins for system
clock
18, 17
–
XTIN, XTOUT
–
Crystal oscillator pins for subsystem clock
20, 21
–
TEST1
I
Test input (must be connected to VSS) (2)
19
–
NOTES
1. Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
2. Refer to chapter 16 for OTP version.
Table 1-2. Overview of KS57C21632 Pin Data
Pin Name
Share Pins
I/O Type
Reset Value
Circuit Type
P0.0–P0.3
TCLO1/K0, TCLO1/K1
BUZ/K2, BUZ/K3
I/O
Input
E-2
P1.0–P1.3
INT0, INT1, INT2, INT4
I/O
Input
E-2
P2.0–P2.1
CLO, TCL1
I/O
Input
E-2
P2.2–P2.3
–
I/O
Input
E-2
COM0–COM15
–
O
Low
H-6
SEG0–SEG55
–
O
Low
H-6
VDD
–
–
–
–
VSS
–
–
–
–
RESET
–
I
–
B
CA
–
–
–
–
CB
–
–
–
–
VLC1–VLC5
–
–
–
–
XIN, XOUT
–
–
–
–
XTIN, XTOUT
–
–
–
–
TEST1, 2
–
I
–
–
1-6
KS57C21632/P21632
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
PNE
VDD
Pull-up
Resistor
VDD
P-Channel
Data
N-Channel
Output
Disable
Resistor
Enable
I/O
In
Schmitt Trigger
Figure 1-5. Pin Circuit Type E-2
Figure 1-3. Pin Circuit Type A
VLC1
VLC2
VDD
VLC3/VLC4
Pull-up Resistor
SEG/COM Data
Out
IN
Schmitt Trigger
VLC3/VLC4
VLC5
VSS
Figure 1-4. Pin Circuit Type B
Figure 1-6. Pin Circuit Type H-6
1-7
PRODUCT OVERVIEW
KS57C21632/P21632
NOTES
1-8
KS57C21632/P21632
14
ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this section, information on KS57C21632 electrical characteristics is presented as tables and graphics.
The information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— Battery level detector characteristics
— Voltage booster characteristics
— A.C. electrical characteristics
— Operating voltage range
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at XIN
— Clock timing measurement at XTIN
— Input timing for RESET signal
— Input timing for external interrupts and quasi-interrupts
14-1
ELECTRICAL DATA
KS57C21632/P21632
Table 14-1. Absolute Maximum Ratings
(TA = 25 °C)
Parameter
Supply Voltage
Symbol
Conditions
Rating
Units
VDD
–
– 0.3 to + 4.5
V
– 0.3 to VDD + 0.3
V
– 0.3 to VDD + 0.3
V
mA
Input Voltage
VI
Output Voltage
VO
–
Output Current High
I OH
One I/O pin active
– 15
All I/O pins active
– 30
One I/O pin active
+ 30 (Peak value)
Output Current Low
Ports 0–2
I OL
mA
+ 15 (note)
Total for pins 0, 1
+ 100 (Peak value)
+ 60 (note)
Operating Temperature
TA
–
– 40 to + 85
°C
Storage Temperature
Tstg
–
– 65 to + 150
°C
NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value ×
Duty .
Table 14-2. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.2 V to 3.4 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
0.8 VDD
–
VDD
V
VIH1
Ports 0, 1, 2, and RESET
VIH2
XIN, XOUT, and XTIN
VIL1
Ports 0, 1, 2, and RESET
VIL2
XIN, XOUT, and XTIN
Output High
Voltage
VOH
VDD = 2.2 V to 3.4 V
IOH = – 1 mA
Ports 0, 1, 2
VDD – 1.0
–
–
V
Output Low
Voltage
VOL
VDD = 2.2 V to 3.4 V
IOL = 5 mA
Ports 0, 1, 2
–
–
1.0
V
Input High
Voltage
Input Low
Voltage
14-2
VDD – 0.1
–
VDD
–
0.2 VDD
V
0.1
KS57C21632/P21632
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 2.2 V to 3.4 V)
Parameter
Symbol
Input High
Leakage Current
ILIH1
VI = VDD
All input pins except those specified
below for ILIH2
ILIH2
VI = VDD
RESET, XIN, XOUT, XTIN and XTOUT
ILIL1
VI = 0 V
All input pins except RESET, XIN,
XOUT, XTIN and XTOUT
ILIL2
VI = 0 V
XIN, XOUT, XTIN and XTOUT
Output High
Leakage Current
ILOH
VO = VDD
All output pins
–
–
3
µA
Output Low
Leakage Current
ILOL
VO = 0 V
All output pins
–
–
–3
µA
Pull-up Resistor
RL1
VI = 0 V; VDD = 3 V, Ports 0–2
50
100
200
kΩ
RL2
VI = 0 V; VDD = 3 V, RESET
200
450
800
|VLCD–COMi|
Voltage Drop
(i = 0–15)
VDC
VLCD = 5.0 V
– 15 µA per common pin
–
–
120
|VLCD–SEGx|
Voltage Drop
(i = 0–55)
VDS
VLCD = 5.0 V
– 15 µA per common pin
–
–
120
Input Low
Leakage Current
Conditions
Min
Typ
Max
Units
–
–
3
µA
20
–
–
–3
µA
– 20
mV
14-3
ELECTRICAL DATA
KS57C21632/P21632
Table 14-2. D.C. Electrical Characteristics (Concluded)
(TA = – 40 °C to + 85 °C, VDD = 2.2 V to 3.4 V)
Parameter
Supply
Current (1)
Symbol
Conditions
Min
Typ
Max
Units
IDD1
VDD = 3 V ± 10%
crystal oscillator
C1 = C2 = 22 pF
4.19 MHz
(PCON = 3H)
–
1.2
3
mA
IDD2
Idle mode; VDD = 3 V ± 10%
crystal oscillator
C1 = C2 = 22 pF
4.19 MHz
(PCON = 3H)
–
0.4
1
mA
IDD3 (2)
VDD = 3 V ± 10%
32 kHz crystal oscillator
–
15
30
µA
IDD4 (2)
Idle mode; VDD = 3 V ± 10%
32 kHz crystal oscillator (LCD off)
–
6
15
µA
Stop mode; VDD = 3 V ± 10% SCMOD =
0000B,
XTIN = 0 V
–
0.5
3
µA
0.2
2
IDD5
Stop mode; VDD = 3 V ± 10% SCMOD =
0000B
NOTES:
1. Data includes power consumption for subsystem clock oscillation.
2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
3. Current in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage booster circuit, and
port drive currents.
14-4
output
KS57C21632/P21632
ELECTRICAL DATA
Table 14-3. Main System Clock Oscillator Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.2 V to 3.4 V)
Oscillator
Ceramic
Oscillator
Clock
Configuration
XIN
XOUT
C1
Parameter
Test Condition
Min
Typ
Max
Units
Oscillation frequency (1)
–
0.4
–
4.19
MHz
Stabilization occurs
when VDD is equal
to the minimum
oscillator voltage
range; VDD = 3 V
–
–
4
ms
–
0.4
–
4.19
MHz
–
–
10
ms
C2
Stabilization time (2)
Crystal
Oscillator
XIN
XOUT
C1
Oscillation frequency (1)
C2
Stabilization time (2)
External
Clock
RC
Oscillator
XIN
XOUT
XIN
XOUT
VDD = 3 V
XIN input frequency (1)
–
0.4
–
4.19
MHz
XIN input high and low
level width (tXH, tXL)
–
83.3
–
1250
ns
VDD = 3 V
0.4
–
2
MHz
Frequency
R
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
14-5
ELECTRICAL DATA
KS57C21632/P21632
Table 14-4. Recommended Oscillator Constants
(TA = – 40 °C + 85 °C, VDD = 2.2 V to 3.4 V)
Manufacturer
TDK
Series
Number (1)
Frequency Range
Load Cap (pF)
Oscillator Voltage
Range (V)
C1
C2
MIN
MAX
Remarks
M5
3.58 MHz–6.0 MHz
33
33
2.2
3.4
Leaded Type
FCR
MC5
3.58 MHz–6.0 MHz
(2)
(2)
2.2
3.4
On-chip C
Leaded Type
CCR
MC3
3.58 MHz–6.0 MHz
(3)
(3)
2.2
3.4
On-chip C
SMD Type
FCR
NOTES:
1. Please specify normal oscillator frequency.
2. On-chip C: 30pF built in.
3. On-chip C: 38pF built in.
Table 14-5. Subsystem Clock Oscillator Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.2 V to 3.4 V)
Oscillator
Crystal
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max
Units
XTIN XTOUT
Oscillation frequency (1)
–
32
32.768
35
kHz
–
1.0
3
s
C1
C2
Stabilization time (2)
External
Clock
XT IN XT OUT
VDD = 3.0 V
(1)
–
32
–
100
kHz
XTIN input high and low
level width (tXTL, tXTH)
–
5
–
15
µs
XTIN input frequency
NOTES:
1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only.
2.
14-6
Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
KS57C21632/P21632
ELECTRICAL DATA
Table 14-6. Input/Output Capacitance
(TA = 25 °C, VDD = 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
Capacitance
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
Output
Capacitance
COUT
–
–
15
pF
CIO
–
–
15
pF
I/O Capacitance
Table 14-7. Battery Level Detector Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.2 V to 3.4 V)
Parameter
Symbol
Condition
BLD Voltage
VB0
BLC = 0
(when BREF = #05H)
BLD Circuit
Response Time
TB
fw = 32.768 kHz
BLD Operating
Current
IBL
–
Min
Typ
Max
Units
2.2
2.4
2.6
V
–
–
1
ms
–
–
10
µA
14-7
ELECTRICAL DATA
KS57C21632/P21632
Table 14-8. Voltage Booster Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.2 V to 3.4 V, C1 = C2 = C3 = C4 = 0.1 µF, CA/CB = 0.1 µF)
Parameter
Liquid Crystal
Drive Voltage (1)
Voltage Regulator
& Booster
Consumed
Current
Symbol
VLC5
Conditions
Connect a 1 MΩ load
resistance between VSS and
VLC5 (2) (no panel load)
LCR = 0
Min
Typ
Max
Units
Typ
× 0.9
0.85
Typ
× 1.1
V
LCR = 1
0.90
LCR = 2
0.95
LCR = 3
1.00
LCR = 4
1.05
LCR = 5
1.10
LCR = 6
1.15
LCR = 7
1.20
VLC4/3
Connect a 1 MΩ load resistance between 2 × VLC5
VSS and VLC4/3 (2) (no panel load)
× 0.9
–
2 × VLC5
× 1.1
VLC2
Connect a 1 MΩ load resistance between 3 × VLC5
VSS and VLC2 (2) (no panel load)
× 0.9
–
3 × VLC5
× 1.1
VLC1
Connect a 1 MΩ load resistance between 4 × VLC5
VSS and VLC1 (2) (no panel load)
× 0.9
–
4 × VLC5
× 1.1
IVB
VDD = 3 V
LCR = 7
Display on (LCON = 3H)
5.0
10
–
µA
NOTES:
1. The operating voltage of booster ranges from 2.4 V to 3.4 V.
2. The 1 MΩ load resistance is connected only to selected symbol (VLC1–VLC5) conditions to measure the properties
of the circuit.
Table 14-9. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.2 V to 3.4 V)
Parameter
Instruction Cycle
Time (note)
Symbol
tCY
Interrupt Input
High, Low Width
fINTH, fINTL
RESET Input Low
tRSL
Conditions
Min
Typ
Max
Units
VDD = 2.2 V to 3.4 V
0.95
–
64
µs
With subsystem clock (fxt)
114
122
125
INT0–INT2, INT4
K0–K3, TLC1
10
–
–
µs
Input
10
–
–
µs
Width
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
14-8
KS57C21632/P21632
ELECTRICAL DATA
Main Oscillator Frequency
(Divided by 4)
CPU Clock
1.05 MHz
4.2 MHz
15.6 kHz
1
2
3
2.2
4
5
6
7
3.4
Supply Voltage (V)
CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 14-1. Standard Operating Voltage Range
Table 14-10. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
VDDDR
–
2.2
–
3.4
V
Data retention supply current
IDDDR
–
0.1
10
µA
Release signal set time
tSREL
0
–
–
µs
Oscillator stabilization wait
time (1)
tWAIT
Released by RESET
–
217/fx
–
ms
Released by interrupt
–
(2)
–
VDDDR = 2.2 V
–
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
14-9
ELECTRICAL DATA
KS57C21632/P21632
TIMING WAVEFORMS
Internal RESET
Operation
~
~
Idle Mode
Stop Mode
Normal Mode
Data Retention Mode
~
~
VDD
VDDDR
Execution of
STOP Instrction
RESET
tWAIT
tSREL
Figure 14-2. Stop Mode Release Timing When Initiated by RESET
Idle Mode
~
~
Normal
Mode
Stop Mode
Data Retention Mode
~
~
VDD
VDDDR
Execution of
STOP Instrction
tSREL
tWAIT
Power-down Mode Terminating Signal
(Interrupt Request)
Figure 14-3. Stop Mode Release Timing When Initiated by Interrupt Request
14-10
KS57C21632/P21632
ELECTRICAL DATA
0.8 V DD
0.8 VDD
Measurement
Points
0.2 V DD
0.2 VDD
Figure 14-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx
tXL
tXH
XIN
VDD - 0.1 V
0.1 V
Figure 14-5. Clock Timing Measurement at XIN
1/fxt
tXTL
tXTH
XTIN
VDD - 0.1 V
0.1 V
Figure 14-6. Clock Timing Measurement at XTIN
14-11
ELECTRICAL DATA
KS57C21632/P21632
tRSL
RESET
0.2 VDD
Figure 14-7. Input Timing for RESET Signal
tINTL
INT0, 1, 2, 4,
K0 to K3
TCL1
tINTH
0.8 VDD
0.2 VDD
Figure 14-8. Input Timing for External Interrupts
14-12
KS57C21632/P21632
15
MECHANICAL DATA
MECHANICAL DATA
OVERVIEW
This section contains the following information about the device package:
— Package dimensions in millimeters
15-1
MECHANICAL DATA
KS57C21632/P21632
23.90
0-8
20.00
+ 0.10
- 0.05
0.10 MAX
100-QFP-1420C
14.00
17.90
0.15
0.80
#100
#1
0.65
0.30
+ 0.10
- 0.05
0.05 MIN
0.15 MAX
(0.58)
2.65
3.00 MAX
0.80
NOTE: Dimensions are in millimeters.
Figure 15-1. 100-QFP-1420C Package Dimensions
15-2
KS57C21632/P21632
16
KS57P21632 OTP
KS57P21632 OTP
OVERVIEW
The KS57P21632 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
KS57C21632 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by
serial data format.
The KS57P21632 is fully compatible with the KS57C21632, both in function and in pin configuration.
Because of its simple programming requirements, the KS57P21632 is ideal for use as an evaluation chip for the
KS57C21632.
16-1
KS57P21632 OTP
KS57C21632/P21632
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VLC1
VLC2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
100-QFP 1420 C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
KS57P21632
VLC3
VLC4
VLC5
CA
CB
TEST2
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
BUZ/P0.3/K3
BUZ/P0.2/K2
SDAT /TCLO1/P0.1/K1
SCLK /TCLO1/P0.0/K0
VDD/VDD
VSS/VSS
XOUT
XIN
VPP/TEST1
XTIN
XTOUT
RESET /RESET
CLO/P2.0
TCL1/P2.1
P2.2
P2.3
COM15
COM14
COM13
COM12
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
Figure 16-1. KS57P21632 Pin Assignments (100-QFP Package)
16-2
SEG18
SEG19
SEG21
SEG22
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
KS57C21632/P21632
KS57P21632 OTP
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P0.1
SDAT
13
I/O
Serial data pin. Output port when reading and input
port when writing. Can be assigned as a Input/pushpull output port.
P0.0
SCLK
14
I/O
Serial clock pin. Input only pin.
TEST
VPP (TEST1)
19
I
Power supply pin for EPROM cell writing (indicates
that OTP enters into the writing mode). When 12.5
V is applied, OTP is in writing mode and when 5 V
is applied, OTP is in reading mode. (Option)
RESET
RESET
22
I
Chip initialization
VDD/VSS
VDD/VSS
15/16
I
Logic power supply pin. VDD should be tied to +5 V
during programming.
Table 16-2. Comparison of KS57P21632 and KS57C21632 Features
Characteristic
KS57P21632
KS57C21632
Program Memory
32 Kbyte EPROM
32 Kbyte mask ROM
Operating Voltage (VDD)
2.2 V to 3.4 V
2.2 V to 3.4 V
OTP Programming Mode
VDD = 5 V, VPP (TEST1) = 12.5 V
Pin Configuration
100 QFP
100 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
–
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST1) pin of the KS57P21632, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 16-3 below.
Table 16-3. Operating Mode Selection Criteria
VDD
VPP
(TEST1)
REG/MEM
Address
(A15–A0)
R/W
Mode
5V
5V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
16-3
KS57P21632 OTP
KS57C21632/P21632
Table 16-4. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.2 V to 3.4 V)
Parameter
Supply
Current (1)
Symbol
Conditions
IDD1
VDD = 3 V ± 10%
4.19 MHz (PCON = 3H) crystal oscillator
C1 = C2 = 22 pF
IDD2
Idle mode; VDD = 3 V ± 10%
4.19 MHz (PCON = 3H) crystal oscillator
C1 = C2 = 22 pF
Min
Typ
Max
Units
–
1.2
3.0
mA
0.4
1.0
15
30
6
1.5
IDD3 (2)
VDD = 3 V ± 10%
32 kHz crystal oscillator
IDD4 (2)
Idle mode; VDD = 3 V ± 10%
32 kHz crystal oscillator
IDD5
Stop mode; VDD = 3 V ± 10%
SCMOD = 0000B,
XTIN = 0 V
0.5
3
Stop mode; VDD = 3 V ± 10%
SCMOD = 0100B
0.2
2
–
NOTES:
1. Data includes power consumption for subsystem clock oscillation.
2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
3. Current in the following circuits are not included; on-chip pull-up resistors, voltage boosting capacitors, and output
port drive currents.
16-4
µA
KS57C21632/P21632
KS57P21632 OTP
Main Oscillator Frequency
(Divided by 4)
CPU Clock
1.05 MHz
4.2 MHz
15.6 kHz
1
2
3
2.2
4
5
6
7
3.4
Supply Voltage (V)
CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 16-2. Standard Operating Voltage Range
16-5