S3C72C8/P72C8 1 PRODUCT OVERVIEW PRODUCT OVERVIEW OVERVIEW The S3C72C8 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With an up-to-96-dot LCD direct drive capability flexible 16-bit timer/counter, and 4-chanel comparator, the S3C72C8 offers an excellent design solution for a low CDP and a card reader. Up to 28 pins of the 44-pin QFP or up to 26 pins of the 42-pin SDIP package can be dedicated to I/O. Eight vectored interrupts provide fast response to internal and external events. In addition, the S3C72C8's advanced CMOS technology provides for low power consumption. OTP The S3C72C8 microcontroller is also available in OTP (One Time Programmable) version, S3P72C8. S3P72C8 microcontroller has an on-chip 8K-byte one-time-programable EPROM instead of masked ROM. The S3P72C8 is comparable to S3C72C8, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C72C8/P72C8 FEATURES Memory Interrupts • 512 × 4-bit RAM (including LCD display RAM) • Four internal vectored interrupts • 8,192 × 8-bit ROM • Five external vectored interrupts • Two quasi-interrupts 28 I/O Pins • I/O: 26 pins (44-pin QFP, 42-pin SDIP) Bit Sequential Carrier • Output only: 2 pins (44-pin QFP) • Supports 16-bit serial data transfer in arbitrary format LCD Controller/Driver • 12 segments and 8 common terminals Memory-Mapped I/O Structure (3, 4, and 8 common selectable) • Data memory bank 15 • Internal resistor circuit for LCD bias Power-Down Modes • All dot can be switched on/off • Idle mode (only CPU clock stops) 8-bit Basic Timer • Stop mode (main system oscillation stops) • 4 interval timer functions • Sub system clock stop mode • Watch-dog timer Oscillation Sources 16-bit Timer/Counter 1 • Crystal, ceramic, or RC for main system clock • Programmable 16-bit timer/counter • Crystal oscillator for subsystem clock • Arbitrary clock output • Main system clock frequency: 0.4 MHz-6 MHz • External event counter • Subsystem clock frequency: 32.768 kHz • External clock signal divider • CPU clock divider circuit (by 4, 8, or 64) • Configurable as two 8-bit timer/counters Instruction Execution Times • Serial I/O interface clock generator • 0.67, 1.33, 10.7 µs at 6 MHz (main) Watch Timer • 0.95, 1.91, 15.3 µs at 4.19 MHz (main) • Time interval generation: 0.5 s, 3.9 ms at 32768 Hz • 122 µs at 32.768 kHz (subsystem) • Four frequency outputs to BUZ pin • Clock source generation for LCD 8-bit Serial I/O Interface Operating Temperature • – 40 °C to 85 °C Operating Voltage Range • 1.8 V to 5.5 V • 8-bit transmit/receive mode • 8-bit receive mode Package Type • LSB-first or MSB-first transmission selectable • • Internal or external clock source Comparator • 4 channel mode: internal reference (4-bit resolution) • 3 channel mode: external reference 1-2 44-pin QFP, 42-pin SDIP S3C72C8/P72C8 PRODUCT OVERVIEW BLOCK DIAGRAM 8-Bit Timer/ Counter1A 8-Bit Timer/ Counter1B Watch Dog Timer 16-Bit Timer/ Counter XIN RESET Basic Timer XOUT XTIN XTOUT Watch Timer P2.0/CIN0/K0 P2.1/CIN1/K1 P2.2/CIN2/K2 P2.3/CIN3/K3 P3.0/INTP30 P3.1/INTP31 P5.0-P5.3/ SEG0-SEG3 I/O Port 2 Interrupt Control Block COM0-COM3 Clock P7.0-P7.3/ SEG8-SEG11 P4.0 P4.1 LCD Driver/ Controller I/O Port 3 Internal Interrupts Program Counter I/O Port 5 Instruction Decoder P6.0-P6.3/ SEG4-SEG7 Instruction Register I/O Port 7 SIO I/O Port 0 Stack Pointer I/O Port 1 Output Port 4 512 x 4-Bit Data Memory SEG0-SEG3/ P5.0-P5.3 SEG4-SEG7/ P6.0-P6.3 SEG8-SEG11/ P7.0-P7.3 Program Status Word I/O Port 6 Arithmetic and Logic Unit COM4-COM7/ SEG15-SEG12 8 K Byte Program Memory P0.0/SCK P0.1/SO P0.2/SI P0.3/BTCO P1.0/TCLO1/INT0 P1.1/TCL1/INT1 P1.2/CLO/INT2 P1.3/BUZ/INT4 Comparator 44 QFP Only Figure 1-1. S3C72C8 Simplified Block Diagram 1-3 PRODUCT OVERVIEW S3C72C8/P72C8 44 43 42 41 40 39 38 37 36 35 34 P4.0 P4.1 P1.3/BUZ/INT4 P1.2/CLO/INT2 P1.1/TCL1/INT1 P1.0/TCLO1/INT0 COM0 COM1 COM2 COM3 COM4/SEG15 PIN ASSIGNMENTS 1 2 3 4 5 6 7 8 9 10 11 S3C72C8 (44-QFP-1010B) 33 32 31 30 29 28 27 26 25 24 23 COM5/SEG14 COM6/SEG13 COM7/SEG12 SEG11/P7.3 SEG10/P7.2 SEG9/P7.1 SEG8/P7.0 SEG7/P6.3 SEG6/P6.2 SEG5/P6.1 SEG4/P6.0 RESET P0.3/BTCO P0.2/SI P0.1/SO P0.0/SCK P3.1/INTP31 P3.0/INTP30 SEG0/P5.0 SEG1/P5.1 SEG2/P5.2 SEG3/P5.3 12 13 14 15 16 17 18 19 20 21 22 P2.0/CIN0/K0 P2.1/CIN1/K1 P2.2/CIN2/K2 P2.3/CIN3/K3 VDD VSS XOUT XIN TEST XTIN XTOUT Figure 1-2. S3C72C8 44-QFP Pin Assignment Diagram 1-4 S3C72C8/P72C8 PRODUCT OVERVIEW S3C72C8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 (42-SDIP-600) COM1 COM0 P1.0/TCLO1/INT0 P1.1/TCL1/INT1 P1.2/CLO/INT2 P1.3/BUZ/INT4 P2.0/CIN0/K0 P2.1/CIN1/K1 P2.2/CIN2/K2 P2.3/CIN3/K3 VDD VSS XOUT XIN TEST XTIN XTOUT RESET P0.3/BTCO P0.2/SI P0.1/SO 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 COM2 COM3 COM4/SEG15 COM5/SEG14 COM6/SEG13 COM7/SEG12 SEG11/P7.3 SEG10/P7.2 SEG9/P7.1 SEG8/P7.0 SEG7/P6.3 SEG6/P6.2 SEG5/P6.1 SEG4/P6.0 SEG3/P5.3 SEG2/P5.2 SEG1/P5.1 SEG0/P5.0 P3.0/INTP30 P3.1/INTP31 P0.0/SCK Figure 1-3. S3C72C8 42-SDIP Pin Assignment Diagram 1-5 PRODUCT OVERVIEW S3C72C8/P72C8 Table 1-1. S3C72C8 Pin Descriptions 1-6 Pin Name Pin Type P0.0 P0.1 P0.2 P0.3 I/O P1.0 P1.1 P1.2 P1.3 Description Circuit Type Number Share Pin 4-bit I/O port. 1-bit and 4-bit read/write and test are possible. Individual pins are software configurable as input or output; Individual pins are software configurable as open-drain or push-pull output; Individual pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. E–1 16 (22) 15 (21) 14 (20) 13 (19) SCK SO SI BTCO I/O Same as port 0. E–1 39 (3) 40 (4) 41 (5) 42 (6) TCLO1/INT0 TCL1/INT1 CLO/INT2 BUZ/INT4 P2.0 P2.1 P2.2 P2.3 I/O Same as port 0 except that port 2 is not configurable as n-channel open drain and is configurable as analog input pin. F–8 1 (7) 2 (8) 3 (9) 4 (10) K0/CIN0 K1/CIN1 K2/CIN2 K3/CIN3 P3.0 P3.1 I/O 2-bit I/O port 1-bit and 4-bit read/write and test is possible. Individual pins are software configurable as input or output; Individual pins are software configurable as open-drain or push-pull output; 2-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. E–3 18 (24) 17 (23) INTP30 INTP31 P4.0 P4.1 O 2-bit output port. 1-bit and 4-bit read/write and test is possible. Individual pins are software configurable as open-drain or push-pull output. E-2 44 43 P5.0-P5.3 I/O 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. Individual pins are software configurable as input or output; Individual pins are software configurable as open-drain or push-pull output; 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. H-13 19-22 (25-28) SEG0-SEG3 P6.0-P6.3 I/O Same as port5 H-13 23-26 (29-32) SEG4-SEG7 P7.0-P7.3 I/O Same as port5 H-13 27-30 (33-36) SEG8-SEG11 S3C72C8/P72C8 PRODUCT OVERVIEW Table 1-1. S3C72C8 Pin Descriptions (Continued) Pin Name Pin Type SEG0-SEG3 I/O Description Circuit Type Number Share Pin H–13 19-22 (25-28) P5.0-P5.3 SEG4-SEG7 23-26 (29-32) P6.0-P6.3 SEG8-SEG11 27-30 (33-36) P7.0-P7.3 LCD segment display signal output pins SEG12-SEG15 O LCD segment display output pins H–6 31-34 (37-40) COM7-COM4 COM0-COM3 O LCD common signal output pins H–4 38-35 (2-1, – 42-41) COM4-COM7 I/O LCD common signal output pins H–6 34-31 (40-37) SEG12– SEG15 SCK I/O Serial interface clock signal E–1 16 (22) P0.0 SO I/O Serial data output E–1 15 (21) P0.1 SI I/O Serial data input E–1 14 (20) P0.2 BTCO I/O Basic timer overflow signal E–1 13 (19) P0.3 TCLO1 I/O Timer/counter external clock output E–1 39 (3) P1.0/INT0 TCL1 I/O Timer/counter external clock input E–1 40 (4) P1.1/INT1 CLO I/O Clock output E–1 41 (5) P1.2/INT2 BUZ I/O Frequency output to buzzer E–1 42 (6) P1.3/INT4 RESET I System RESET pin B 12 (18) – Xin, Xout – Clock input and output pins for main system clock – 8-7 (14-13) – XTin, XTout – Clock input and output pins for subsystem clock – 10-11 (16-17) – CIN0–CIN3 I Analog input port for Comparator F–8 1-4 (7-10) P2.0/K0 -P2.3/K3 K0–K3 I/O External interrupts. The triggering edge is selectable. F–8 1-4 (7-10) P2.0/CIN0 -P2.3/CIN3 INT0 INT1 I External interrupts. The triggering edge for INT0 and INT1 is selectable. E–1 39 (3) 40 (4) P1.0/TCLO1 -P1.1/TCL1 1-7 PRODUCT OVERVIEW S3C72C8/P72C8 Table 1-1. S3C72C8 Pin Descriptions (Continued) Pin Name Pin Type INT2 I INT4 Description Circuit Type Number Share Pin Quasi-interrupt with detection of rising or falling edges. E-1 41 (5) P1.2/CLO I External interrupt with detection of rising or falling edges. E-1 42 (6) P1.3/BUZ INTP30 INTP31 I Key scan interrupts inputs. E-3 18-17 (24-23) P3.0, P3.1 TEST I System test pin – 9 (15) – VDD – Power supply pin – 5 (11) – VSS – Ground pin – 6 (12) – NOTES: 1. Parentheses indicate pin number for 42-SDIP package. 2. Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode. 1-8 S3C72C8/P72C8 PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD Pull-Up Resistor In Schmitt Trigger Input Figure 1-4. Pin Circuit Type B VDD Pull-up Resistor Pull-Up Resistor Enable P-CH VDD PNE Data I/O Output DIsable Figure 1-5. Pin Circuit Type E-1 1-9 PRODUCT OVERVIEW S3C72C8/P72C8 VDD PNE Out Data Figure 1-6. Pin Circuit Type E-2 VDD Pull-Up Resistor Pull-Up Resistor Enable P-CH PNE Ouput Disable Data Circuit Type E-4 I/O LCON.1 Figure 1-7. Pin Circuit Type E-3 1-10 S3C72C8/P72C8 PRODUCT OVERVIEW VDD PNE Out Data Figure 1-8. Pin Circuit Type E-4 VDD VLC1 COM Data Out LPOT.3 VLC4 VSS Figure 1-9. Pin Circuit Type H-4 1-11 PRODUCT OVERVIEW S3C72C8/P72C8 VDD VLC1 VLC2 SEG/COM Data Out LPOT.3 VLC3 VLC4 VSS Figure 1-10. Pin Circuit Type H-6 1-12 S3C72C8/P72C8 PRODUCT OVERVIEW VDD VLC2 SEG Data Output Disable Out VLC3 VSS Figure 1-11. Pin Circuit Type H-7 1-13 PRODUCT OVERVIEW S3C72C8/P72C8 VDD Pull-Up Resistor Enable SEG Output DIsable Data P-CH Circuit Type H-7 Circuit Type E-4 PNE Figure 1-12. Pin Circuit Type H-13 1-14 S3C72C8/P72C8 PRODUCT OVERVIEW VDD Pull-up Resistor Pull-Up Resistor Enable P-CH VDD Data I/O Output DIsable (Digital) INTK (Analog) External REF (P2.3 only) + Comparator REF Digital or Analog can be seleted by software. Figure 1-13. Pin Circuit Type F-8 1-15 S3C72C8/P72C8 15 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, information on S3C72C8 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics — Absolute maximum ratings — D.C. electrical characteristics — Main system clock oscillator characteristics — Subsystem clock oscillator characteristics — I/O capacitance — Comparator electrical characteristics — A.C. electrical characteristics — Operating voltage range Stop Mode Characteristics and Timing Waveforms — RAM data retention supply voltage in stop mode — Stop mode release timing when initiated by RESET — Stop mode release timing when initiated by an interrupt request Miscellaneous Timing Waveforms — A.C timing measurement points — Clock timing measurement at Xin — Clock timing measurement at XTin — TCL1 timing — Input timing for RESET signal — Input timing for external interrupts and quasi-interrupts — Serial data transfer timing 15-1 ELECTRICAL DATA S3C72C8/P72C8 Table 15-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Supply Voltage Symbol Conditions Rating Units VDD – – 0.3 to + 6.5 V Input Voltage VI All I/O pins active – 0.3 to VDD + 0.3 V Output Voltage VO – – 0.3 to VDD + 0.3 V Output Current High I OH One I/O pin active – 15 mA All I/O pins active – 35 One I/O pin active + 30 (Peak value) Output Current Low I OL mA + 15 * Total for ports 0, 2–9 + 100 (Peak value) + 60 * Operating Temperature TA – – 40 to + 85 °C Storage Temperature Tstg – – 65 to + 150 °C * The values for Output Current Low ( IOL ) are calculated as Peak Value × Duty . Table 15-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Symbol Conditions Input High VIH1 Ports 0, 1, 2, 3, 5, 6, 7, RESET Voltage VIH2 Xin, Xout, XTin, and XTout Input Low VIL1 Ports 0, 1, 2, 3, 5, 6, 7, RESET Voltage VIL2 Xin, Xout, XTin, and XTout Output High Voltage VOH VDD = 4.5 V to 5.5 V IOH = – 1 mA Ports 0, 1, 2, 3, 4, 5, 6, 7 Output Low Voltage VOL VDD = 4.5 V to 5.5 V IOL = 15 mA Min Typ Max Units 0.8 VDD – VDD V VDD – 0.1 – VDD – 0.2 VDD 0.1 VDD – 1.0 – – V – – 2.0 V Ports 0, 1, 2, 3, 4, 5, 6, 7 VDD = 1.8 V to 5.5 V IOL = 1.6 mA 15-2 V 0.4 S3C72C8/P72C8 ELECTRICAL DATA Table 15-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Input High Leakage Current Input Low Leakage Current Output High Leakage Current Output Low Leakage Current Pull-Up Resistor Symbol Conditions ILIH1 VI = VDD All input pins except those specified below for ILIH2 ILIH2 VI = VDD Xin, Xout, XTin, and XTout ILIL1 VI = 0 V Min Typ Max Units – – 3 µA 20 – – –3 µA All input pins except RESET, Xin, Xout, XTin, and XTout ILIL2 VI = 0 V Xin, Xout, XTin, and XTout ILOH VO = VDD All output pins – – 3 µA ILOL VO = 0 V All output pins – – –3 µA RLI VI = 0 V; VDD = 5 V Ports 0-3, 5-7 expect 25 47 100 kΩ 50 95 200 VI = 0 V; VDD = 5 V, RESET 100 220 400 VDD = 3 V 200 450 800 RESET VDD = 3 V RL2 – 20 LCD Voltage Dividing Resistor |VLC1-COMi| Voltage Drop (i = 0–7 |VLC1-SEGx| Voltage Drop (x = 0–15) VLC1 Output Voltage RLCD Ta = 25 °C 60 80 100 kΩ VDC – 15 µA per common pin – – 120 mV VDS – 15 µA per segment pin – – 120 VLC1 VDD = 1.8 V to 5.5 V, 1/5 bias LCD clock = 0 Hz, VLCD = VDD 0.8 VDD – 0.2 0.8 VDD 0.8 VDD + 0.2 VLC2 Output Voltage VLC3 Output Voltage VLC4 Output Voltage VLC2 0.6 VDD – 0.2 0.4 VDD – 0.2 0.2 VDD – 0.2 0.6 VDD 0.6 VDD + 0.2 0.4 VDD + 0.2 0.2 VDD + 0.2 VLC3 VLC4 0.4 VDD 0.2 VDD V 15-3 ELECTRICAL DATA S3C72C8/P72C8 Table 15-2. D.C. Electrical Characteristics (Concluded) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 (2) IDD2 (2) Conditions Min Typ Max Units – 3.0 2.3 8.0 5.5 mA VDD = 5 V ± 10% Crystal oscillator C1 = C2 = 22 pF 6.0 MHz 4.19 MHz VDD = 3 V ± 10% 6.0 MHz 4.19 MHz 1.5 1.0 4.0 3.0 Idle mode VDD = 5 V ± 10% Crystal oscillator C1 = C2 = 22 pF 6.0 MHz 4.19 MHz 1.3 1.2 2.5 1.8 VDD = 3 V ± 10% 6.0 MHz 4.19 MHz 0.5 0.44 1.5 1.0 15.0 30 IDD3 (3) VDD = 3 V ± 10% 32 kHz crystal oscillator IDD4 (3) Idle mode; VDD = 3 V ± 10% 32 kHz crystal oscillator 5.0 15 Stop mode; VDD = 5 V ± 10% 2.5 5 0.5 3 0.2 3 0.1 2 IDD5 SCMOD = 0000B XTin = 0V Stop mode; VDD = 3 V ± 10% VDD = 5 V ± 10% VDD = 3 V ± 10% SCMOD = 0100B – µA NOTES: 1. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, comparator, output port drive currents. 2. Data includes power consumption for subsystem clock oscillation. 3. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the subsystem clock is used. 4. Every values in this table is measured when the power control register (PCON) is set to "0011B". 15-4 S3C72C8/P72C8 ELECTRICAL DATA Table 15-3. Main System Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration Xin Xout C1 Parameter Test Condition Min Typ Max Units Oscillation frequency (1) – 0.4 – 6.0 MHz Stabilization occurs when VDD is equal to the minimum oscillator voltage range; VDD = 3.0 V. – – 4 ms – 0.4 – 6.0 MHz VDD = 2.7 V to 5.5 V – – 10 ms VDD = 1.8 V to 5.5 V – – 30 Xin input frequency (1) – 0.4 – 6.0 MHz Xin input high and low level width (tXH, tXL) – 83.3 – 1250 ns R = 25 kΩ, VDD = 5 V – 2 – MHz R = 40 kΩ, VDD = 3 V – 1 – C2 Stabilization time (2) Crystal Oscillator Xin Xout C1 Oscillation frequency (1) C2 Stabilization time (2) External Clock RC Oscillator Xin Xout Xin Xout R Frequency NOTES: 1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated. 15-5 ELECTRICAL DATA S3C72C8/P72C8 Table 15-4. Recommended Oscillator Constants (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Manufacturer TDK Series Number (1) FCR M5 Frequency Range Load Cap (pF) Oscillator Voltage Range (V) Remarks C1 C2 MIN MAX 3.58 MHz–6.0 MHz 33 33 2.0 5.5 Leaded Type (2) 2.0 5.5 On-chip C Leaded Type (3) 2.0 5.5 On-chip C SMD Type FCR MC5 3.58 MHz–6.0 MHz (2) CCR MC3 3.58 MHz–6.0 MHz (3) NOTES: 1. Please specify normal oscillator frequency. 2. On-chip C: 30pF built in. 3. On-chip C: 38pF built in. Table 15-5. Subsystem Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Clock Configuration Crystal Oscillator XTin XTout Parameter Oscillation frequency Min Typ Max Units – 32 32.768 35 kHz VDD = 2.7 V to 5.5 V – 1.0 2 s VDD = 1.8 V to 5.5 V – – 10 – 32 – 100 kHz – 5 – 15 µs (1) C1 C2 Stabilization time (2) External Clock Test Condition XTin XTout XTin input frequency (1) XTin input high and low level width (tXTL, tXTH) NOTES: 1. Oscillation frequency and XTin input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs. 15-6 S3C72C8/P72C8 ELECTRICAL DATA Table 15-6. Input/Output Capacitance (TA = 25 °C, VDD = 0 V ) Parameter Symbol Condition Min Typ Max Units Input Capacitance CIN f = 1 MHz; Unmeasured pins are returned to VSS – – 15 pF Output Capacitance COUT – – 15 pF CIO – – 15 pF I/O Capacitance Table 15-7. Comparator Electrical Characteristics (TA = – 40 °C + 85 °C, VDD = 4.0 V to 5.5 V, VSS = 0 V) Parameter Symbol Condition Min Typ Max Units – – 0 – VDD V VREF – 0 – VDD V Internal VCIN1 – – – ± 150 mV External VCIN2 – – – ± 150 mV ICIN, IREF – –3 – 3 µA Input Voltage Range Reference Voltage Range Input Voltage Accuracy Input Leakage Current 15-7 ELECTRICAL DATA S3C72C8/P72C8 Table 15-8. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time (note) TCL1 Input Frequency Symbol tCY f TI1 Conditions Min Typ Max Units VDD = 2.7 V to 5.5 V 0.67 – 64 µs VDD = 1.8 V to 5.5 V 1.33 VDD = 2.7 V to 5.5 V 0 64 – VDD = 1.8 V to 5.5 V TCL1 Input High, Low Width SCK Cycle Time SCK High, Low Width tTIH1, tTIL1 tKCY tKH, tKL 0.48 VDD = 1.8 V to 5.5 V 1.8 VDD = 2.7 V to 5.5 V; Input 800 Output 650 VDD = 1.8 V to 5.5 V; Input 3200 Output 3800 VDD = 2.7 V to 5.5 V; Input 325 VDD = 1.8 V to 5.5 V; Input Output SI Setup Time to SCK High SI Hold Time to SCK High tSIK tKSI MHz 1 VDD = 2.7 V to 5.5 V Output 1.5 – – µs – – ns – – ns – – ns – – ns tKCY/2 – 50 1600 tKCY/2 – 150 VDD = 2.7 V to 5.5 V; Input 100 VDD = 2.7 V to 5.5 V; Output 150 VDD = 1.8 V to 5.5 V; Input 150 VDD = 1.8 V to 5.5 V; Output 500 VDD = 2.7 V to 5.5 V; Input 400 VDD = 2.7 V to 5.5 V; Output 400 VDD = 1.8 V to 5.5 V; Input 600 VDD = 1.8 V to 5.5 V; Output 500 NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source. 15-8 S3C72C8/P72C8 ELECTRICAL DATA Table 15-8. A.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Symbol Output Delay for SCK to SO Interrupt Input High, Low Width Conditions tKSO VDD = 2.7 V to 5.5 V; Input tINTH, tINTL RESET Input Low Width tRSL Min Typ Max Units – – 300 ns VDD = 2.7 V to 5.5 V; Output 250 VDD = 1.8 V to 5.5 V; Input 1000 VDD = 1.8 V to 5.5 V; Output 1000 INT0, INT1, INT2, INT4, K0– K3, INTP30, INTP31 10 – – µs Input 10 – – µs NOTE: Minimum value for INT0 is based on a clock of 2tCY or 128 / fx as assigned by the IMOD0 register setting. Main Oscillator Frequency (Divided by 4) CPU CLOCK 1.5 MHz 6 MHz 1.05 MHz 4.2 MHz 0.75 MHz 3.0 MHz 15.6 kHz 1 2 3 4 5 6 7 1.8 SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, or 64) Figure 15-1. Standard Operating Voltage Range 15-9 ELECTRICAL DATA S3C72C8/P72C8 Table 15-9. RAM Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR – 1.8 – 5.5 V Data retention supply current IDDDR – 0.1 10 µA Release signal set time tSREL 0 – – µs Oscillator stabilization wait time (1) tWAIT Released by RESET – 217 / fx – ms Released by interrupt – (2) – VDDDR = 1.8 V – NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time. 15-10 S3C72C8/P72C8 ELECTRICAL DATA TIMING WAVEFORMS Internal Reset Operation ~ ~ Idle Mode Stop Mode Operating Mode Data Retention Mode ~ ~ VDD VDDDR Execution of STOP Instruction RESET tWAIT tSREL Figure 15-2. Stop Mode Release Timing When Initiated By RESET Idle Mode ~ ~ Normal Operating Mode Stop Mode Data Retention Mode ~ ~ VDD VDDDR Execution of STOP Instruction tSREL tWAIT Power-down Mode Terminating Signal (Interrupt Request) Figure 15-3. Stop Mode Release Timing When Initiated By Interrupt Request 15-11 ELECTRICAL DATA S3C72C8/P72C8 0.8 VDD 0.8 VDD Measurement Points 0.2 VDD 0.2 VDD Figure 15-4. A.C. Timing Measurement Points (Except for XIN and XTIN) 1/fx tXL tXH XIN VDD - 0.1 V 0.1 V Figure 15-5. Clock Timing Measurement at XIN 1/fxt tXTL tXTH XTIN VDD - 0.1 V 0.1 V Figure 15-6. Clock Timing Measurement at XTIN 15-12 S3C72C8/P72C8 ELECTRICAL DATA 1/fTI tTIL tTIH TCL1 0.7 VDD 0.3 VDD Figure 15-7. TCL1 Timing tRSL RESET 0.2 VDD Figure 15-8. Input Timing for RESET Signal tINTL INT0, 1, 2, 4 K0 to K3 INTP30, INTP31 tINTH 0.8 VDD 0.2 VDD Figure 15-9. Input Timing for External Interrupts and Quasi-Interrupts 15-13 ELECTRICAL DATA S3C72C8/P72C8 tKCY tKL tKH SCK 0.8 VDD 0.2 VDD tSIK tKSI 0.8 VDD SI Input Data 0.2 VDD tKSO SO Output Data Figure 15-10. Serial Data Transfer Timing 15-14 S3C72C8/P72C8 16 MECHANICAL DATA MECHANICAL DATA OVERVIEW This section contains the following information about the device package: — Package dimensions in millimeters — Pad diagram #22 0.2 5 42-SDIP-600 +0 - 0 .1 .05 0-15 15.24 14.00 ± 0.2 #42 (1.77) NOTE: 1.00 ± 0.1 5.08 MAX 39.10 ± 0.2 0.1 3.30 ± 0.3 0.2 39.50 MAX 0.50 ± 3.50 ± #21 0.51 MIN #1 1.78 Dimensions are in millimeters. Figure 16-1. 42-SDIP-600 Package Dimensions 16-1 MECHANICAL DATA S3C72C8/P72C8 13.20 ± 0.3 0-8 10.00 ± 0.2 10.00 ± 0.2 + 0.10 - 0.05 0.10 MAX 44-QFP-1010B 0.80 ± 0.20 13.20 ± 0.3 0.15 #44 #1 + 0.10 0.35 - 0.05 0.80 0.05 MIN (1.00) 2.05 ± 0.10 2.30 MAX NOTE: Dimensions are in millimeters. Figure 16-1. 44-QFP-1010B Package Dimensions 16-2 S3C72C8/P72C8 17 S3P72C8 OTP S3P72C8 OTP OVERVIEW The S3P72C8 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C72C8 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. 44 43 42 41 40 39 38 37 36 35 34 P4.0 P4.1 P1.3/BUZ/INT4 P1.2/CLO/INT2 P1.1/TCL1/INT1 P1.0/TCLO1/INT0 COM0 COM1 COM2 COM3 SEG15/COM4 The S3P72C8 is fully compatible with the S3C72C8, both in function and in pin configuration. Because of its simple programming requirements, the S3P72C8 is ideal for use as an evaluation chip for the S3C72C8. 1 2 3 4 5 6 7 8 9 10 11 S3P72C8 33 32 31 30 29 28 27 26 25 24 23 COM5/SEG14 COM6/SEG13 COM7/SEG12 SEG11/P7.3 SEG10/P7.2 SEG9/P7.1 SEG8/P7.0 SEG7/P6.3 SEG6/P6.2 SEG5/P6.1 SEG4/P6.0 RESET/RESET RESET BTCO/P0.3 SI/P0.2 SO/P0.1 SCK/P0.0 INTP31/P3.1 INTP30/P3.0 P5.0/SEG0 P5.1/SEG1 P5.2/SEG2 P5.3/SEG3 12 13 14 15 16 17 18 19 20 21 22 P2.0/CIN0/K0 P2.1/CIN1/K1 SDAT/P2.2/CIN2/K2 SCLK/P2.3/CIN3/K3 VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT Figure 17-1. S3P72C8 44-QFP Pin Assignments 17-1 S3P72C8 OTP S3C72C8/P72C8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S3P72C8 COM1 COM2 P1.0/TCLO1/INT0 P1.1/TCL1/INT1 P1.2/CLO/INT2 P1.3/BUZ/INT4 P2.0/CIN0/K0 P2.1/CIN1/K1 SDAT/P2.2/CIN2/K2 SCLK/P2.3/CIN3/K3 VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT RESET/RESET RESET P0.3/BTCO P0.2/SI P0.1/SO 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 COM2 COM3 COM4/SEG15 COM5/SEG14 COM6/SEG13 COM7/SEG12 SEG11/P7.3 SEG10/P7.2 SEG9/P7.1 SEG8/P7.0 SEG7/P6.3 SEG6/P6.2 SEG5/P6.1 SEG4/P6.0 SEG3/P5.3 SEG2/P5.2 SEG1/P5.1 SEG0/P5.1 P3.0/INTP30 P3.1/INTP31 P0.0/SCK Figure 17-2. S3P72C8 42-SDIP Pin Assignments 17-2 S3C72C8/P72C8 S3P72C8 OTP Table 17-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P2.2 SDAT 3 (9) I/O Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. P2.3 SCLK 4 (10) I/O Serial clock pin. Input only pin. TEST VPP(TEST) 9 (15) I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) RESET RESET 12 (18) I Chip initialization VDD/VSS VDD/VSS 5/6 (11/12) I Logic power supply pin. VDD should be tied to + 5 V during programming. NOTE: Parentheses indicate pin number for 42-SDIP package. Table 17-2. Comparison of S3P72C8 and S3C72C8 Features Characteristic S3P72C8 S3C72C8 Program Memory 8 Kbyte EPROM 8 Kbyte mask ROM Operating Voltage (VDD) 1.8 V to 5.5 V 1.8 V to 5.5 V OTP Programming Mode VDD = 5 V, VPP(TEST)=12.5V Pin Configuration 44-QFP, 42-SDIP 44-QFP, 42-SDIP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3P72C8, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 17-3 below. Table 17-3. Operating Mode Selection Criteria VDD VPP (TEST) REG/MEM Address (A15-A0) R/W Mode 5V 5V 0 0000H 1 EPROM read 12.5 V 0 0000H 0 EPROM program 12.5 V 0 0000H 1 EPROM verify 12.5 V 1 0E3FH 0 EPROM read protection NOTE: "0" means Low level; "1" means High level. 17-3 S3P72C8 OTP S3C72C8/P72C8 Table 17-4. D.C. Electrical Characteristics (TA = - 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 (2) IDD2 (2) Conditions Min Typ Max Units – 3.0 2.3 8.0 5.5 mA VDD = 5 V ± 10% Crystal oscillator C1 = C2 = 22 pF 6.0 MHz 4.19 MHz VDD = 3 V ± 10% 6.0 MHz 4.19 MHz 1.5 1.0 4.0 3.0 Idle mode VDD = 5 V ± 10% Crystal oscillator C1 = C2 = 22 pF 6.0 MHz 4.19 MHz 1.3 1.2 2.5 1.8 VDD = 3 V ± 10% 6.0 MHz 4.19 MHz 0.5 0.44 1.5 1.0 15.0 30 IDD3 (3) VDD = 3 V ± 10% 32 kHz crystal oscillator IDD4 (3) Idle mode; VDD = 3 V ± 10% 32 kHz crystal oscillator 5.0 15 Stop mode; VDD = 5 V ± 10% 2.5 5 0.5 3 0.2 3 0.1 2 IDD5 SCMOD = 0000B XTIN = 0V Stop mode; VDD = 3 V ± 10% VDD = 5 V ± 10% VDD = 3 V ± 10% SCMOD = 0100B – µA NOTES: 1. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, comparator, output port drive currents. 2. Data includes power consumption for subsystem clock oscillation. 3. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the subsystem clock is used. 4. Every values in this table is measured when the power control register (PCON) is set to "0011B". 17-4 S3C72C8/P72C8 S3P72C8 OTP Main Oscillator Frequency (Divided by 4) CPU CLOCK 6 MHz 1.5 MHz 1.05 MHz 4.2 MHz 0.75 MHz 3.0 MHz 15.6 kHz 1 2 3 4 5 6 7 1.8 SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, or 64) Figure 17-3 Standard Operating Voltage Range 17-5 S3P72C8 OTP S3C72C8/P72C8 NOTES 17-6