Ordering number : ENN*6714 CMOS IC LC875064B/56B/48B 8-Bit Single Chip Microcontroller with 64/56/48K-Byte EPROM and 2048-Byte RAM On Chip Preliminary Overview The LC875064B/56B/48B microcontroller is 8-bit single chip microcontroller with the following on-chip functional blocks: - CPU: Operable at a minimum bus cycle time of 100ns - 64K/56K/48K bytes ROM - 2048 byte RAM - two high performance 16 bit timer/counters (can be divided into 8 bit units) - two 8 bit timers with prescalers - timer for use as date/time clock - one synchronous serial I/O ports (with automatic block transmit/receive function) - one asynchronous/synchronous serial I/O port - 12-bit PWM × 2 - 3-channel × 8-bit AD converter - high speed 8-bit parallel interface - 16-source 10-vectored interrupt system All of the above functions are fabricated on a single chip. Features (1) Read Only Memory (ROM) - 65535 × 8 bits (LC875064B) - 57343 × 8 bits (LC875056B) - 49151 × 8 bits (LC875048B) Ver.1.03 12500 91400 RM (IM) HK / SY No.6714-1/26 LC875064B/56B/48B (2) Random Access Memory (RAM) - 2048 × 8 bits (LC875064B/56B/48B) (3) Bus Cycle Time - 100ns (10MHz) Note: The bus cycle time indicates ROM read time. (4) Minimum Instruction Cycle Time : 300ns (10MHz) (5) Ports - Input/output ports Each bit data direction programmable Nibble data direction programmable - Input ports - PWM Output ports - Oscillator pins - Reset pin - Power supply 51 (P1n, P2n, P70 to P73, P80 to P82, PA2 to PA5, PBn, PCn) 8 (P0n) 2 (XT1,XT2) 2 (PWM0,PWM1) 2 (CF1,CF2) 1 ( RES ) 6 (VSS1 to 3,VDD1 to 3) (6) Timers - Timer0: 16 bit timer/counter with capture register Mode 0: 2 channel 8 bit timer with programmable 8 bit prescaler and 8 bit capture register Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit counter with 8 bit capture register Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register Mode 3: 16 bit counter with 16 bit capture register - Timer1: PWM/16 bit timer/counter (with toggle output) Mode 0: 8 bit timer (with toggle output) + 8 bit timer counter (with toggle output) Mode 1: 2 channel 8 bit PWM Mode 2: 16 bit timer/counter (with toggle output) Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM output. - Base timer 1. The clock signal can be selected from any of the following: sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output for timer 0. 2. Interrupts can be selected to occur at one of five different times. (7) SIO - SIO0: 8 bit synchronous serial interface 1. LSB first/MSB first function available 2. Internal 8-bit baud-rate generator (maximum transmit clock period 4/3 TCYC) 3. Continuous automatic data communications (1 - 256 bits) - SIO1: 8 bit asynchronous/synchronous serial interface Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 - 512 T CYC) Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 - 2048 TCYC) Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 - 512 TCYC) Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection) (8) AD converter - 8-bits × 3-channels (9) PWM - 2 channel synchronous variable 12 bit PWM (10) Parallel interface - RS, RD , WR , CS0 - CS2 Outputs (reversible polarity) - read/write possible in 1 TCYC No.6714-2/26 LC875064B/56B/48B (11) Remote control receiver circuit (connected to P73/INT3/T0IN terminal) - Noise rejection function (noise rejection filter time constant can selected from 1/32/128 TCYC) (12) Watchdog timer - The watchdog timer period set by external RC. - Watchdog timer can be set to produce interrupt, system reset (13) Interrupts - 16-source, 10-vectored interrupts: 1. Three level (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower level interrupt request is refused. 2. If interrupt requests to two or more vector addresses occur at once, the higher level interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence. No. Vector Selectable Level Interrupt signal 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4 4 0001BH H or L INT3/INT5/Base timer 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0 8 0003BH H or L SIO1 9 00043H H or L ADC 10 0004BH H or L Port 0/PWM0, 1 • Priority Level: X > H > L • For equal priority levels, vector with lowest address takes precedence. (14) Subroutine stack levels - 1024 levels max. Stack is located in RAM (15) Multiplication and division - 16 bit × 8 bit (executed in 5 cycles) - 24 bit × 16 bit (12 cycles ) - 16 bit ÷ 8 bit (8 cycles) - 24 bit ÷ 16 bit (12 cycles) (16) Oscillation circuits - On-chip RC oscillation circuit used for system clock - On-chip CF oscillation circuit used for system clock - On-chip Crystal oscillation circuit used for system clock and time-base clock (17) Standby function - HALT mode HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral circuits still operate. 1. Oscillation circuits are not stopped automatically 2. Release on system reset - HOLD mode HOLD mode is used to reduce the power dissipation. Both program execution and peripheral circuits are stopped. 1. CF, RC and crystal oscillation circuits stop automatically 2. Release occurs on any of the following conditions •input to the reset pin goes low •a specified level is input to at least one of INT0, INT1, INT2, INT4, INT5 •an interrupt condition arises at port 0 No.6714-3/26 LC875064B/56B/48B - X’tal HOLD mode X’tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits except the base timer are stopped. 1. CF and RC oscillation circuits stop automatically 2. Crystal oscillator is maintained in its state at HOLD mode inception. 3. Release occurs on any of the following conditions •input to the reset pin goes low •a specified level is input to at least one of INT0, INT1, INT2, INT4, INT5 •an interrupt condition arises at port 0 •an interrupt condition arises at the base-timer (18) Factory shipment - delivery form QIP64E - delivery form DIP64S (19) Development Tools - Evaluation chip - Emulator : LC876098 : EVA87000 + ECB875000 (Evaluation chip board) + POD875000 (POD) No.6714-4/26 LC875064B/56B/48B PB1/D1 PB0/D0 VSS3 VDD3 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PA2/CS0# PA3/WR# PA4/RD# PA5/RS Pin Assignment 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P70/INT0/T0LCP 49 32 PB2/D2 P71/INT1/T0HCP 50 31 PB3/D3 P72/INT2/T0IN 51 30 PB4/D4 P73/INT3/T0IN 52 29 PB5/D5 RES# 53 28 PB6/D6 XT1 54 27 PB7/D7 XT2 55 26 P27/INT5/T1IN VSS1 56 25 P26/INT5/T1IN CF1 57 24 P25/INT5/T1IN CF2 58 23 P24/INT5/T1IN LC875064B/56B/48B QIP 19 P20/INT4/T1IN P10/SO0 63 18 P07 P11/SI0/SB0 64 17 P06 9 10 11 12 13 14 15 16 P05 8 P04 7 P03 6 P02 5 P01 4 P00 3 VSS2 2 VDD2 1 PWM0 P21/INT4/T1IN 62 PWM1 20 P82/AN2 P17/T1PWMH/BUZ 61 P15/SCK1 P22/INT4/T1IN P81/AN1 P16/T1PWML P23/INT4/T1IN 21 P14/SI1/SB1 22 60 P13/SO1 59 P12/SCK0 VDD1 P80/AN0 Package Dimension (unit : mm) 3159 SANYO : QIP-64E No.6714-5/26 LC875064B/56B/48B QIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ PWM1 PWM0 VDD2 VSS2 P00 P01 P02 P03 P04 P05 P06 P07 P20/INT4/T1IN P21/INT4/T1IN P22/INT4/T1IN P23/INT4/T1IN P24/INT5/T1IN P25/INT5/T1IN P26/INT5/T1IN P27/INT5/T1IN PB7/D7 PB6/D6 PB5/D5 PB4/D4 PB3/D3 PB2/D2 QIP 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME PB1/D1 PB0/D0 VSS3 VDD3 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PA2/CS0# PA3/WR# PA4/RD# PA5/RS P70/INT0/T0LCP P71/INT1/T0HCP P72/INT2/T0IN P73/INT3/T0IN RES# XT1 XT2 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P10/SO0 P11/SI0/SB0 No.6714-6/26 LC875064B/56B/48B System Block Diagram IR Interrupt control PLA ROM CF RC Xtal Clock Generator Standby control PC SIO0 Bus Interface ACC SIO1 Port 0 B Register Port 1 C Register Timer 0 ALU Port 7 Timer 1 Port 8 PSW ADC RAR PWM0 PWM1 INT0-3 Noise Rejection Filter Port 2 RAM INT4,,5 Stack Pointer Base Timer Parallel interface Port A Port B Port C Watch Dog Timer No.6714-7/26 LC875064B/56B/48B Pin Assignment Pin Name VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 Port 0 P00 - P07 I/O Pin Function Option - Negative power supply No - Positive power supply No •8-bit Input/output port •Data direction can be specified in nibble units •Use of pull-up resistor can be specified in nibble units •HOLD-release input •Input for port 0 interrupt •8-bit Input/output port •Data direction can be specified for each bit •Use of pull-up resistor can be specified for each bit •Other functions P10: SIO0 data output P11: SIO0 data input/bus input/output P12: SIO0 clock input/output P13: SIO1 data output P14: SIO1 data input/bus input/output P15: SIO1 clock input/output P16: Timer 1 PWML output P17: Timer 1 PWMH output/Buzzer output •8-bit Input/output port •Data direction can be specified for each bit •Use of pull-up resistor can be specified for each bit •Other functions P20-P23: INT4 input/HOLD release input/timer 1 event input /Timer 0L capture input/Timer 0H capture input P24-P27: INT5 input/HOLD release input/timer 1 event input /Timer 0L capture input /Timer 0H capture input Interrupt receiver format Rising Falling Rising/ H level falling INT4 Yes Yes Yes No INT5 Yes Yes Yes No Yes I/O Port 1 P10 - P17 I/O Port 2 P20 - P27 I/O Yes Yes L level No No (Continued) No.6714-8/26 LC875064B/56B/48B Name Port 7 I/O I/O P70 - P73 Port 8 P80 - P82 I/O Port A PA2 - PA5 I/O Function description •4-bit Input/output port •Data direction can be specified for each bit •Use of pull-up resistor can be specified for each bit •Other functions P70: INT0 input/HOLD release input/Timer0L capture input /Output for watchdog timer P71: INT1 input/HOLD release input/Timer0H capture input P72: INT2 input/HOLD release input/timer 0 event input /Timer0L capture input P73: INT3 input(noise rejection filter attached input) /timer 0 event input/Timer0H capture input Interrupt receiver format Rising Falling Rising/ H level falling Yes No Yes Yes INT0 Yes No Yes Yes INT1 No Yes Yes Yes INT2 No Yes Yes Yes INT3 •3-bit Input/output port •Data direction can be specified for each bit •Other functions P80-P82: AD input port •4-bit Input/output port •Data direction can be specified for each bit •Use of pull-up resistor can be specified for each bit •Other functions PA2: Parallel interface output CS0 Option No L level Yes Yes No No No Yes PA3: Parallel interface output WR Port B PB0 - PB7 I/O Port C PC0 - PC7 I/O PWM0 PWM1 RES O O I XT1 I XT2 I/O CF1 CF2 I O PA4: Parallel interface output RD PA5: Parallel interface output RS •8-bit Input/output port •Data direction can be specified for each bit •Use of pull-up resistor can be specified for each bit •Other functions PB0-PB7: Parallel interface data input/output; address output •8-bit Input/output port •Data direction can be specified for each bit •Use of pull-up resistor can be specified for each bit •Other functions PC0-PC7: Parallel interface address output PWM0 output port PWM1 output port Reset terminal •Input for 32.768kHz crystal oscillation •Other function Input port When not in use, connect to VDD1. •Output for 32.768kHz crystal oscillation •Other function General purpose input port When not in use, set to oscillation mode and leave open circuit Input terminal for ceramic oscillator Output terminal for ceramic oscillator Yes Yes No No No No No No No No.6714-9/26 LC875064B/56B/48B Port Output Configuration Output configuration and pull-up resistor options are shown in the following table. Input is possible even when port is set to output mode. Terminal P00-P07 P10-P17 P20-P27 PA2-PA5 PB0-PB7(*) PC0-PC7 P70 P71-P73 P80-P82 PWM0, PWM1 XT1 XT2 Option applies to: 1 bit units Option Output Format Pull-up resistor 1 2 1 2 1 2 CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Programmable (Note 1) None Programmable Programmable Programmable Programmable - None None None None Nch-open drain CMOS Nch-open drain CMOS Programmable Programmable None None - None None Input only Output for 32.768kHz crystal oscillation None None each bit each bit Note 1 Programmable pull-up resisters of Port 0 can be attatched in nibble units (P00-03, P04-07). (*) When in parallel interface mode, PB0-PB7 output format is CMOS, regardless of any selected option. Note: Connect as follows to reduce noise on VDD and increase the back-up time. VSS1, VSS2 and VSS3 must be connected together and grounded. Example 1 : In hold mode, during backup, port output ‘H’ level is supplied from the back-up capacitor. LSI VDD1 Power Supply Back-up capacitor VDD2 VDD3 VSS1 VSS2 VSS3 Example 2 : During backup in hold mode output is not held high and its value in unsettled. LSI VDD1 Power Supply Back-up capacitor VDD2 VDD3 VSS1 VSS2 VSS3 No.6714-10/26 LC875064B/56B/48B 1. Absolute Maximum Ratings at Ta=25°C, VSS1=VSS2=VSS3=0V Parameter Symbol Supply voltage VDDMAX Input voltage Output voltage Input/output voltage VI(1) VO(1) VIO(1) High level output current Peak output current Total output current Low level output current Peak output current Total output current Maximun power dissipation Operating temperature range Storage temperature range IOPH(1) IOPH(2) ΣIOAH(1) ΣIOAH(2) ΣIOAH(3) ΣIOAH(4) ΣIOAH(5) ΣIOAH(6) IOPL(1) IOPL(2) IOPL(3) ΣIOAL(1) ΣIOAL(2) ΣIOAL(3) ΣIOAL(4) ΣIOAL(5) ΣIOAL(6) Pdmax Pins VDD1, VDD2, VDD3 XT1, XT2, CF1 PWM0, PWM1 Ports 0, 1, 2 Ports 7, 8 Ports A, B, C PWM0, PWM1 Ports 0, 1, 2 Ports A, B, C PWM0, PWM1 Port 7 Port 7 Port 8 Port 1 PWM0, PWM1 Port 0 Ports 2, B Ports A, C P02-P07 Ports 1, 2 Ports A, B, C PWM0, PWM1 P00, P01 Ports 7, 8 Port 7 Port 8 Port 1 PWM0, PWM1 Port 0 Ports 2, B Ports A, C QFP64E Conditions VDD1=VDD2 =VDD3 VDD[V] min. -0.3 -0.3 -0.3 -0.3 •CMOS output •For each pin. Ratings typ. max. +7.0 -5 -5 -5 -20 The total of all pins. The total of all pins. The total of all pins. For each pin. -20 -20 -20 V VDD+0.3 VDD+0.3 VDD+0.3 mA -10 For each pin. The total of all pins. The total of all pins. The total of all pins. unit 20 For each pin. For each pin. The total of all pins. The total of all pins. The total of all pins. 30 15 5 5 40 The total of all pins. The total of all pins. The total of all pins. Ta=-30 to +70°C 70 40 40 430 mW °C Topg -20 70 Tstg -65 150 No.6714-11/26 LC875064B/56B/48B 2. Recommended Operating Range at Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Parameter Symbol Pins Operating supply voltage range VDD(1) HOLD voltage VHD VDD1=VDD2 =VDD3 Input high voltage VIH(1) •Ports 1, 2 •P71-P73 •P70 port input /interrupt •Ports 0, 8 •Ports A, B, C Port 70 Watchdog timer input XT1, XT2, CF1, RES •Ports 1, 2 •P71-P73 •P70 port input /interrupt •Ports 0, 8 •Ports A, B, C Port 70 Watchdog timer input XT1, XT2, CF1, RES VIH(2) VIH(3) VIH(4) Input low voltage VIL(1) VIL(2) VIL(5) VIL(6) Operation cycle time tCYC External system clock frequency FEXCF(1) VDD1=VDD2 =VDD3 CF1 Conditions 0.294µs ≤ tCYC ≤ 200µs 0.588µs ≤ tCYC ≤ 200µs RAM and the register data are kept in HOLD mode. •CF2 open circuit •system clock divider set to 1/1 •external clock DUTY=50±5% •CF2 open circuit •system clock divider set to 1/2 (Note 1) VDD[V] min. 4.5 Ratings typ. max. 6.0 2.5 6.0 2.0 6.0 2.5 - 6.0 0.3VDD +0.7 VDD 2.5 - 6.0 0.3VDD +0.7 VDD 2.5 - 6.0 0.9VDD VDD 2.5 - 6.0 0.75VDD VDD 2.5 - 6.0 VSS 0.1VDD +0.4 2.5 - 6.0 VSS 0.15VDD +0.4 2.5 - 6.0 VSS 0.8VDD -1.0 2.5 - 6.0 VSS 0.25VDD 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 0.294 0.588 0.1 200 200 10 2.5 - 6.0 0.1 5 4.5 - 6.0 0.2 20.4 2.5 - 6.0 0.1 10 unit V µs MHz The oscillation constant is shown in Tables 1 and 2. No.6714-12/26 LC875064B/56B/48B 3. Electrical Characteristics at Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Parameter Input high current Input low current Output high current Symbol Pins Conditions IIH(1) •Ports 0, 1, 2 •Ports 7, 8 •Ports A, B, C • RES •PWM0, PWM1 IIH(2) XT1, XT2 IIH(3) CF1 •Output disable •Pull-up resistor off •VIN=VDD (including off state leak current of output Tr.) When specified as an input port. VIN=VDD VIN=VDD IIL(1) •Ports 0, 1, 2 •Ports 7, 8 •Ports A, B, C • RES •PWM0, PWM1 IIL(2) XT1, XT2 IIL(3) CF1 VOH(1) VOH(2) •Ports 0, 1, 2 •Ports B, C •PWM0, PWM1 Port A VOH(3) VOH(4) VOH(5) Port 7 VDD[V] 2.5 - 6.0 min. Ratings typ. max. 1 2.5 - 6.0 1 2.5 - 6.0 15 2.5 - 6.0 -1 2.5 - 6.0 -1 2.5 - 6.0 -15 •Output disable •Pull-up resistor off •VIN=VSS (including off state leak current of output Tr.) When specified as an input port VIN=VSS VIN=VSS IOH=-1.0mA IOH=-0.1mA 4.5 - 6.0 VDD-1 2.5 - 6.0 VDD-0.5 IOH=-5.0mA IOH=-0.4mA IOH=-0.4mA 4.5 - 6.0 VDD-1 2.5 - 6.0 VDD-0.5 2.5 - 6.0 VDD-1 unit µA V (Continued) No.6714-13/26 LC875064B/56B/48B Parameter Output low current Symbol VOL(1) VOL(2) Pins •Ports 0, 1, 2 •Ports B, C •PWM0, PWM1 VOL(3) Conditions min. Ratings typ. IOL=10mA VDD[V] 4.5 - 6.0 max. 1.5 IOL=1.6mA 2.5 - 6.0 0.4 IOL=1.0mA 2.5 - 6.0 0.3 VOL(4) P00, P01 IOL=30mA 4.5 - 6.0 1.5 VOL(5) Ports 7, 8 IOL=1mA 4.5 - 6.0 0.4 IOL=0.5mA 2.5 - 6.0 0.3 IOL=15mA 4.5 - 6.0 1.5 IOL=2mA 2.5 - 6.0 0.4 VOH=0.9VDD 2.5 - 6.0 VOL(6) VOL(7) Port A VOL(8) Pull-up resistor Rpu •Ports 0, 1, 2 •Port 7 •Ports A, B, C Hysteresis voltage VHIS Pin capacitance CP •Ports 1, 2 •Port 7 • RES All pins •Every other terminal connected to VSS. •f=1MHz •Ta=25°C 15 40 70 unit V kΩ 2.5 - 6.0 0.1VDD V 2.5 - 6.0 10 pF No.6714-14/26 LC875064B/56B/48B 4. Serial Input/Output Characteristics at Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Serial clock Input clock Parameter Symbol Pins SCK0(P12) Output clock Serial input Refer to figure 6 VDD[V] 2.5 - 6.0 min. 2 Cycle tSCK(1) Low level pulse width tSCKL(1) 1 tSCKLA(1) 1 tSCKH(1) 1 High level pulse width Cycle tSCKHA(1) tSCK(2) SCK1(P15) Refer to figure 6 2.5 - 6.0 tSCKL(2) 1 tSCKH(2) 1 Low level pulse width tSCKL(3) tSCK(3) SCK0(P12) High level pulse width •Use pull-up resistor (1kΩ) when output is open drain. •Refer to figure 6 SCK0(P12) SIO0 2.5 - 6.0 Ratings typ. unit tCYC 4/3 tSCK 1/2 3/4 tSCKH(3) 1/2 tSCKHA(2) SCK0(P12) SIO0 •CMOS output option •Refer to figure 6 2 Cycle tSCK(4) Low level pulse width High level pulse width Data set-up time tSCKL(4) 1/2 tSCKH(4) 1/2 Data hold time thDI Output delay time tdD0 tsDI max. 3(SIO0) 2 Low level pulse width High level pulse width Cycle tSCKLA(2) Serial output Conditions SCK1(P15) SB0(P11), SB1(P14), SI0, SI1 SO0(P10), SO1(P13), SB0(O11), SB1(P14) •Data set-up to SI0CLK •Refer to figure 6 •Data set-up to SI0CLK •When port is open drain: Time delay from SI0CLK trailing edge to the SO data change. •Refer to figure 6 2.5 - 6.0 2 4.5 - 6.0 0.03 2.5 - 6.0 0.03 4.5 - 6.0 0.03 2.5 - 6.0 0.03 tCYC tSCK µs 4.5 - 6.0 1/3tCYC +0.05 2.5 - 6.0 1/3tCYC +0.05 No.6714-15/26 LC875064B/56B/48B 5. Parallel Input/Output Characteristics at Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format. Please refer to figures 8 and 9 for parallel output timing waveforms. Parameter Write cycle, Read cycle Address set-up time Symbol Pins Conditions VDD[V] 2.5 - 6.0 min. From address set-up until control signal changes 2.5 - 6.0 1/3tCYC -30ns 2.5 - 6.0 tC(1) tsA(1) • WR (PA3), PB0-PB7 • RD (PA4), PC0-PC7 Ratings typ. 1 max. unit tCYC tCYC & ns tsA(2) RD (PA4), PC0-PC7 Address hold time thA(1) RD (PA4), PC0-PC7 From change of RD until address change 2.5 - 6.0 2/3tCYC -30ns 1/6tCYC thA(2) WR (PA3), PC0-PC7 2.5 - 6.0 5 ns tsRS(1) WR (PA3), RS(PA5), From change of WR until address change From change of RS, CS until change in 2.5 - 6.0 1/6tCYC -15ns tCYC & ns 2.5 - 6.0 1/6tCYC -15ns 1/3tCYC -15ns 1/3tCYC -15ns RS set-up tie CS (PAX) CS set-up time WR from change of RS until change in RD tsRS(2) RD (PA4), RS(PA5) tsRS(3) RD (PA4), RS(PA5) tsCS(1) RD (PA4), CS (PAX) From change in CS tsCS(2) WR (PA3), CS (PAX) From change in CS thRS(1) WR (PA3), RS(PA5) thRS(2) RD (PA4), RS(PA5), CS (PAX) 2.5 - 6.0 2.5 - 6.0 until change in RD 2.5 - 6.0 2/3tCYC -15ns From change in WR until change in RS 2.5 - 6.0 0 ns From change in RD until change in RS, CS 2.5 - 6.0 1/6tCYC tCYC & ns 2.5 - 6.0 0 ns From change in RD until change in CS 2.5 - 6.0 1/6tCYC tCYC & ns From change in WR 2.5 - 6.0 0 ns 1/6tCYC -5ns 2/3tCYC -5ns 1/6tCYC -5ns 1/3tCYC -5ns until change in WR RS hold time thRS(3) RD (PA4), RS(PA5), CS (PAX) CS hold time thCS(1) RD (PA4), RS(PA5) thCS(2) WR (PA3), RS(PA5) until change in CS WR ’H’ pulse width WR ’L’ pulse width tWRH(1) WR (PA3) 2.5 - 6.0 tWRH(2) WR (PA3) 2.5 - 6.0 tWRL(1) WR (PA3) 2.5 - 6.0 tWRL(2) WR (PA3) 2.5 - 6.0 1/6 tCYC 2/3 tCYC 1/6 tCYC 1/3 tCYC tCYC & ns (Continued) No.6714-16/26 LC875064B/56B/48B Parameter Symbol Pins Conditions tRDH(1) RD (PA4) VDD[V] 2.5 - 6.0 tRDH(2) RD (PA4) 2.5 - 6.0 tRDL(1) RD (PA4) 2.5 - 6.0 tRDL(2) RD (PA4) 2.5 - 6.0 tdDT(1) RD (PA4), PB0-PB7 tdDT(2) RD (PA4), PB0-PB7 Input data set-up time tsDTR(1) RD (PA4), PB0-PB7 Input data hold time thDTR(1) RD (PA4), PB0-PB7 Output data set-up time Output data set-up time tsDTW(1) RD (PA4), PB0-PB7 tsDTW(2) RD (PA4), PB0-PB7 Output data hold time thDTW(1) RD (PA4), PB0-PB7 RD ’H’ pulse width RD ’L’ pulse width Data write permission delay thDTW(2) min. 1/6tCYC -5ns 1/3tCYC -5ns 1/3tCYC -5ns 1/2tCYC -5ns Ratings typ. 1/6 tCYC 1/3 tCYC 1/3 tCYC 1/2 tCYC max. unit tCYC & ns Time for permission, from RD leading edge until input data set-up (Note 1) From input data setup to RD leading edge. (Note 2) 2.5 - 6.0 2.5 - 6.0 40 ns From RD leading edge until input data hold From output data setup until WR leading edge 2.5 - 6.0 0 ns 2.5 - 6.0 1/3tCYC -30ns 1/3tCYC -30ns tCYC & ns 2.5 - 6.0 0 ns 2.5 - 6.0 0 From WR leading edge until output data hold 1/6tCYC -15ns 1/3tCYC -15ns 2.5 - 6.0 2.5 - 6.0 Note 1 : Time until incorrect data of Low is disappeared. Note 2 : Incorrect data of Low is not output in the period between tRDL(1) - tdDT(1). 6. Pulse Input Conditions at Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Parameter Symbol Pins High/low level pulse width tPIH(1) tPIL(1) INT0(P70), INT1(P71), INT2(P72) INT4(P20-P23) INT5(P24-P27) INT3(P73) (The noise rejection clock select to 1/1.) INT3(P73) (The noise rejection clock select to 1/32.) INT3(P73) (The noise rejection clock select to 1/128.) •Interrupt acceptable •Events to timer 0 and 1 can be input. RES tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) Conditions VDD[V] 2.5 - 6.0 min. 1 •Interrupt acceptable •Events to timer 0 can be input. 2.5 - 6.0 2 •Interrupt acceptable •Events to timer 0 can be input. 2.5 - 6.0 64 •Interrupt acceptable •Events to timer 0 can be input. 2.5 - 6.0 256 Reset acceptable 2.5 - 6.0 200 Ratings typ. max. unit tCYC µs No.6714-17/26 LC875064B/56B/48B 7. AD Converter Characteristics at Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Parameter Resolution Absolute precision Conversion time Analog input voltage range Analog port input current Symbol N ET TCAD Pins AN0(P80) - AN2(P82) Conditions (Note 2) AD conversion time =32 × tCYC (ADCR2=0) (Note 3) AD conversion time =64 × tCYC (ADCR2=1) (Note 3) VAIN IAINH IAINL VAIN=VDD VAIN=VSS VDD[V] 4.5 - 5.5 4.5 - 5.5 min. 4.5 - 5.5 15.10 (tCYC= 0.588µs) Ratings typ. 8 max. unit ±1.5 bit LSB 97.92 µs (tCYC= 3.06µs) 15.10 97.92 (tCYC= 0.294µs) (tCYC= 1.53µs) 4.5 - 5.5 VSS VDD V 4.5 - 5.5 4.5 - 5.5 1 µA -1 4.5 - 5.5 (Note 2) Absolute precision not including quantizing error (±1/2 LSB). (Note 3) Conversion time means time from executing AD conversion instruction to loading complete digital value to register. No.6714-18/26 LC875064B/56B/48B 8. Current Dissipation Characteristics atTa=-20°C to +70°C, VSS1=VSS2=VSS3=0V Parameter Current flow during basic operation (Note 4) Symbol IDDOP(1) IDDOP(2) IDDOP(3) IDDOP(4) IDDOP(5) IDDOP(6) IDDOP(7) Pins VDD Conditions •FmCF=10MHz for Ceramic resonator oscillation •FsX’tal=32.768kHz for crystal oscillation •System clock: CF oscillation •Internal RC oscillation stopped. •FmCF=5MHz for Ceramic resonator oscillation •FsX’tal=32.768kHz for crystal oscillation •System clock: CF oscillation •Internal RC oscillation stopped. •FmCF=0Hz (oscillation stops) •FsX’tal=32.768kHz for crystal oscillation •System clock: Internal RC oscillation •FmCF=0Hz (oscillation stops) •FsX’tal=32.768kHz for crystal oscillation •System clock: X’tal oscillation •Internal RC oscillation stopped. Ratings typ. 15 max. 27 4.5 - 6.0 6 11 2.5 - 4.5 3 8 4.5 - 6.0 1 2.5 2.5 - 4.5 0.5 2 4.5 - 6.0 35 70 2.5 - 4.5 15 45 VDD[V] 4.5 - 6.0 min. unit mA µA (Continued) No.6714-19/26 LC875064B/56B/48B Parameter Symbol Pins Current flow: IDDHALT(1) VDD HALT mode (Note 4) IDDHALT(2) IDDHALT(3) IDDHALT(4) IDDHALT(5) IDDHALT(6) IDDHALT(7) Current flow: IDDHOLD(1) VDD1 HOLD mode IDDHOLD(2) (Note 4) IDDHOLD(2) VDD1 Current flow: Date/time clock HOLD mode Conditions •HALT mode •FmCF=10MHz for ceramic resonator oscillation •FsX’tal=32.768kHz for crystal oscillation •System clock: CF oscillation •Internal RC oscillation stopped. •HALT mode •FmCF=5MHz for Ceramic resonator oscillation •FsX’tal=32.768kHz for crystal oscillation •System clock: CF oscillation •Internal RC oscillation stopped. •HALT mode •FmCF=0Hz (oscillation stops) •FsX’tal=32.768kHz for crystal oscillation •System clock: Internal RC oscillation •HALT mode •FmCF=0Hz (oscillation stops) •FsX’tal=32.768kHz for crystal oscillation •System clock: X’tal oscillation •Internal RC oscillation stopped. HOLD mode Date/time clock HOLD mode •CF1=VDD or open circuit (when using external clock) •FmX’tal=32.768kHz for crystal oscillation Ratings typ. 5 max. 11 4.5 - 6.0 2.5 - 4.5 3 1.0 5 2.5 4.5 - 6.0 2.5 - 4.5 400 250 1300 800 4.5 - 6.0 2.5 - 4.5 23 8 60 30 4.5 - 6.0 2.5 - 4.5 0.01 0.01 30 30 µA 4.5 - 6.0 2.5 - 4.5 45 6 100 36 µA VDD[V] 4.5 - 6.0 min. unit mA µA (Note 4) The currents of output transistors and pull-up MOS transistors are ignored. No.6714-20/26 LC875064B/56B/48B Main system clock oscillation circuit characteristics The characteristics in the table bellow is based on the following conditions: 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer. Table 1. Main system clock oscillation circuit characteristics using ceramic resonator Circuit Parameters Frequency Manufacturer Kyocera Murata 5MHz C2 Rd1 0Ω 0Ω 0Ω 0Ω 0Ω Operating supply voltage range 4.5 - 6.0V 4.5 - 6.0V 4.5 - 6.0V 4.5 - 6.0V 4.5 - 6.0V CSA4.00MG 33pF 33pF 0Ω CST4.00MGW (30pF) (30pF) 0Ω KBR-4.0MSA 33pF 33pF 0Ω Murata 4MHz C1 CSA10.0MTZ 33pF 33pF CST10.0MTW (30pF) (30pF) KBR-10.0M 33pF 33pF CSA5.00MG 33pF 33pF CST5.00MGW (30pF) (30pF) Murata 10MHz Oscillator Kyocera 4.5 - 6.0V 4.5 - 6.0V 4.5 - 6.0V Oscillation stabilizing time Notes typ max 0.05ms 0.05ms 0.05ms 0.05ms 0.05ms 0.50ms 0.50ms 0.50ms 0.50ms 0.50ms 0.05ms 0.05ms 0.05ms 0.50ms 0.50ms 0.50ms Built in C1,C2 Built in C1,C2 Built in C1,C2 *The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (Refer to Figure4) Subsystem clock oscillation circuit characteristics The characteristics in the table bellow is based on the following conditions: 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer. Table 2. Subsystem clock oscillation circuit characteristics using crystal oscillator Frequency Manufacturer 32.768kHz Oscillator Seiko EPSON C-002Rx Circuit Parameters Operating supply voltage range C3 C4 Rf Rd2 12pF 15pF OPEN 300kΩ 4.5 - 6.0V Oscillation stabilizing time typ max Notes *The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the HOLD mode. (Refer to Figure4) (Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. CF1 CF2 XT1 Rd1 XT2 Rf Rd2 C1 CF Figure 1 C4 C3 C2 X’tal Ceramic oscillation circuit Figure 2 Crystal oscillation circuit 0.5VDD Figure 3 AC timing measurement point No.6714-21/26 LC875064B/56B/48B VDD Power Supply VDD limit GND Reset time RES# Internal RC Resonator oscillation tmsCF CF1,CF2 tmsXtal XT1,XT2 Operation mode Reset Unfixed Instruction execution mode Reset time and oscillation stable time HOLD release signal Without HOLD Release signal HOLD release signal VALID Internal RC Resonator oscillation tmsCF CF1,CF2 tmsXtal XT1,XT2 Operation mode HOLD HALT HOLD release signal and oscillation stable time Figure 4 Oscillation stabilizing time No.6714-22/26 LC875064B/56B/48B VDD RRES (Note) Set CRES, RRES values such that reset time exceeds 200µs. RES CRES Figure 5 Reset circuit SI0CLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 Data RAM transmission period (only SIO0,2) tSCK tSCKL tSCKH SI0CLK: tsDI thDI DATAIN: tdDO DATAOUT: Data RAM transmission period (only SIO0,2) tSCKLA tSCKHA SI0CLK: tsDI thDI DATAIN: tdDO DATAOUT: Figure 6 Serial input/output test condition tPIL Figure 7 tPIH Pulse input timing condition No.6714-23/26 LC875064B/56B/48B • Parallel Input/Output timing waveform : Indirect Setting, Read Mode tC(1) read cycle addr ADR/DATA: tsA(1) CS#: thRS(1) tsRS(1) RS: tWRH(1) tWRL(1) tsRS(2) tRDL(1) thRS(2) WR#: tsDTR(1) tRDH(1) RD#: tdDT(1) DATAin: thDTR(1) H data Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format. • Parallel Input/Output timing waveform : Indirect Setting, Write Mode tC(1) write cycle ADR/DATA: addr data tsA(1) thDTW(1) CS#: tsRS(1) thRS(3) thRS(1) RS: tWRH(1) tWRL(1) tsRS(3) tsDTW(1) WR#: tWRL(2) RD#: DATAin: Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format. Figure 8 Indirect mode: Parallel Timing Waveforms No.6714-24/26 LC875064B/56B/48B • Parallel Input/Output timing waveform : Direct Setting, Read Mode tC(1) read cycle ADR: addr tsA(1) thA(1) tsCS(1) thCS(1) CS#: DATA: tRDL(2) WR#: tsDTR(1) tRDH(2) RD#: thDTR(1) tdDT(2) DATAin: H data Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format. • Parallel Input/Output timing waveform : Direct Setting, Write Mode tC(1) write cycle ADR: addr tsA(2) thA(2) tsCS(2) thCS(2) CS#: data DATA: tsDTW(2) thDTW(2) WR#: tWRH(2) tWRL(2) RD#: DATAin: Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format. Figure 9 Direct Mode: Parallel Input/Output Timing Diagrams No.6714-25/26 LC875064B/56B/48B memo: PS No.6714-26/26