Ordering number : ENN7825 LC87F74C8A CMOS IC FROM 128K-byte, RAM 4096-byte on chip 8-bit 1-chip Microcontroller Overview The LC87F74C8A is an 8-bit single chip microcontroller with the following on-chip functional blocks : • CPU : operable at a minimum bus cycle time of 100ns • 128K-bytes flash ROM (on-board rewritable) • On-chip RAM : 4096-bytes • LCD controller/driver • Two high performance 16-bit timer/counters (can be divided into 8-bit units) • 16-bit timer/PWM (can be divided into two 8-bit timers) • Four 8-bit timer with prescalers • Timer for use as date/time clock • Synchronous serial I/O port (with automatic block transmit/receive function) • Asynchronous/synchronous serial I/O port • 15-channel × 8-bit AD converter • High-speed clock counter • System clock divider • Small signal detector • 20-source 10-vectored interrupt system All of the above functions are fabricated on a single chip. Features ■Flash ROM • Single 5V power supply, on-board writable • Block erase in 128-byte units • 131072 × 8-bits (LC87F74C8A) ■Random access memory (RAM) • 4096 × 9-bits (LC87F74C8A) ■Minimum bus cycle time • 100ns (10MHz) Note : The bus cycle time indicates ROM read time. Ver.1.02 82202 83004 JO IM No.7825-1/21 LC87F74C8A ■Minimum instruction cycle time • 300ns (10MHz) ■Ports • Input/output ports Data direction programmable for each bit individually : 26 (P1n, P30 to P35, P70 to P73, P8n) Data direction programmable in nibble units : 8 (P0n) (When N-channel open drain output is selected, data can be input in bit units.) • Input ports : 2 (XT1, XT2) • LCD ports Segment output : 48 (S00 to S47) Common output : 4 (COM0 to COM3) Bias terminals for LCD driver 3 (V1 to V3) Other functions Input/output ports : 48 (PAn, PBn, PDn, PEn, PFn) Input ports : 7 (PLn) • Oscillator pins : 2 (CF1, CF2) • Reset pin : 1 (RES) • Power supply : 6 (VSS1 to 3, VDD1 to 3) ■LCD controller • Seven display modes are available (static, 1/2, 1/3, 1/4 duty × 1/2, 1/3 bias) • Segment output and common output can be switched to general purpose input/output ports. ■Small signal detection (MIC signals etc) • Counts pulses with the level which is greater than a preset value • 2-bit counter ■Timer • Timer 0 : 16-bit timer/counter with capture register Mode 0 : 2-channel 8-bit timer with programmable 8-bit prescaler and 8-bit capture register Mode 1 : 8-bit timer with 8-bit programmable prescaler and 8-bit capture register + 8-bit Counter with 8-bit capture register Mode 2 : 16-bit timer with 8-bit programmable prescaler and 16-bit capture register Mode 3 : 16-bit counter with 16-bit capture register • Timer 1 : PWM/16-bit timer/counter with toggle output function Mode 0 : 2-channel 8-bit timer/counter (with toggle output) Mode 1 : 2-channel 8-bit PWM Mode 2 : 16-bit timer/counter (with toggle output) Toggle output from lower 8-bits is also possible. Mode 3 : 16-bit timer (with toggle output) Lower order 8-bits can be used as PWM. • Timer 4 : 8-bit timer with 6-bit prescaler • Timer 5 : 8-bit timer with 6-bit prescaler • Timer 6 : 8-bit timer with 6-bit prescaler • Timer 7 : 8-bit timer with 6-bit prescaler • Base Timer 1. The clock signal can be selected from any of the following : Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0 2. Interrupts of five different time intervals are possible. ■High speed clock counter • Countable up to 20MHz clock (when using 10MHz main clock) • Real time output No.7825-2/21 LC87F74C8A ■Serial interface • SIO0 : 8-bit synchronous serial interface 1. LSB first/MSB first is selectable 2. Internal 8-bit baud-rate generator (fastest clock period 4/3 tCYC) 3. Consecutive automatic data communication (1 to 256-bits) • SIO1 : 8-bit asynchronous/synchronous serial interface Mode 0 : Synchronous 8-bit serial IO (2-wire or 3-wire, transmit clock 2 to 512 tCYC) Mode 1 : Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC) Mode 2 : Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC) Mode 3 : Bus mode 2 (start detection, 8 data bits, stop detection) ■AD converter • 8-bits × 15-channels ■Remote control receiver circuit (connected to P73/INT3/T0IN terminal) • Noise rejection function (noise rejection filter’s time constant can be selected from 1/32/128 tCYC) ■Watchdog timer • The watching time period is determined by an external RC. • Watchdog timer can produce interrupt or system reset ■Interrupts : 18 sources, 10 vectors 1. Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower priority interrupt request is postponed. 2. If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence. No. Vector Selectable Level 1 00003H X or L INT0 Interrupt Signal 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4 4 0001BH H or L INT3/Base timer/INT5 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0 8 0003BH H or L SIO1 9 00043H H or L ADC/MIC/T6/T7 10 0004BH H or L Port 0/T4/T5 • Priority Level : X>H>L • For equal priority levels, vector with lowest address takes precedence. ■Subroutine stack levels : 2048 levels max. Stack is located in RAM. ■Multiplication and division • 16-bit × 8-bit (executed in 5 cycles) • 24-bit × 16-bit (12 cycles) • 16-bit ÷ 8-bit (8 cycles) • 24-bit ÷ 16-bit (12 cycles) ■Oscillation circuits • On-chip RC oscillation for system clock use. • CF oscillation for system clock use. (Rf built in, Rd external) • Crystal oscillation low speed system clock use. (Rf built in, Rd external) • On-chip frequency variable RC oscillation circuit for system clock use. No.7825-3/21 LC87F74C8A ■System clock divider • Low power consumption operation is available • Minimum instruction cycle time (300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs can be switched by program (when using 10MHz main clock) ■Standby function • HALT mode HALT mode is used to reduce power consumption. During the HALT mode, program execution is stopped but peripheral circuits keep operating (some parts of serial transfer operation stop.) 1. Oscillation circuits are not stopped automatically. 2. Released by the system reset or interrupts. • HOLD mode HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are stopped. 1. CF, RC and crystal oscillation circuits stop automatically. 2. Released by any of the following conditions. 1. Low level input to the reset pin 2. Specified level input to one of INT0, INT1, INT2, INT4, INT5 3. Port 0 interrupt • X’tal HOLD mode X’tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits except the base timer are stopped. 1. CF and RC oscillation circuits stop automatically. 2. Crystal oscillator operation is kept in its state at HOLD mode inception. 3. Released by any of the following conditions 1. Low level input to the reset pin 2. Specified level input to one of INT0, INT1, INT2, INT4, INT5 3. Port 0 interrupt 4. Base-timer interrupt ■Package • QIP100E • TQFP100 ■Development tools • Evaluation chip • Emulator : LC876093 : EVA62S + ECB876600 (Evaluation chip board) + SUB877400 + POD100QFP or POD100SQFP (Type B) : ICE-B877300 + SUB877400 + POD100QFP or POD100SQFP (Type B) • Flash ROM write adapter : W87FQ100 or W87FSQ100 ■Same package and pin assignment as mask ROM version. 1. LC877400 series options can be set using flash ROM data. Thus the board used for mass production can be used for debugging and evaluation without modifications. 2. If the program for the mask ROM version is used, the usable ROM/RAM capacity is the same as the mask ROM version. No.7825-4/21 V2/PL5/AN13 V1/PL4/AN12 COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 P30/INT4/T1IN P31/INT4/T1IN VSS3 VDD3 P32/INT4/T1IN P33/INT4/T1IN P34/INT5/T1IN P35/INT5/T1IN P00 P01 P02 P03 P04 P05 P06 P07 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7/MICIN P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN P73/INT3/T0IN S0/PA0 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 V3/PL6/AN14 S47/PF7 S46/PF6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 VSS2 VDD2 S23/PC7 S22/PC6 S21/PC5 LC87F74C8A Package Dimensions Package Dimensions unit : mm 3151A unit : mm 3274 Pin Assignment LC87F74C8A 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15/PB7 S14/PB6 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1/PA1 Top view SANYO:QIP100E No.7825-5/21 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 S46/PF6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 VSS2 VDD2 LC87F74C8A LC87F74C8A 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 S23/PC7 S22/PC6 S21/PC5 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15/PB7 S14/PB6 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1/PA1 S0/PA0 P73/INT3/T0IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7/MICIN P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN S47/PF7 V3/PL6/AN14 V2/PL5/AN13 V1/PL4/AN12 COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 P30/INT4/T1IN P31/INT4/T1IN VSS3 VDD3 P32/INT4/T1IN P33/INT4/T1IN P34/INT5/T1IN P35/INT5/T1IN P00 P01 P02 P03 P04 P05 P06 P07 P10/SO0 Top view SANYO:TQFP100 No.7825-6/21 LC87F74C8A System Block Diagram Interrupt Control IR Stand-by Control PLA Flach ROM RC MRC Clock Generator CF PC X’tal Bus Interface ACC SIO0 Port 0 B Register SIO1 Port 1 C Register Timer 0 (High-speed clock counter) Port 3 ALU Timer 1 Port 7 Base Timer Port 8 PSW LCD Controller ADC RAR INT0 to 5 Noise Rejection Filter Weak Signal Detector RAM Timer 4 Timer 6 Stack Pointer Timer 5 Timer 7 Watch Dog Timer No.7825-7/21 LC87F74C8A Pin Description Pin name I/O Function Option VSS1, VSS2, VSS3 - Power supply (-) No VDD1, VDD2, VDD3 - Power supply (+) No • 8-bit input/output port Yes Port 0 I/O P00 to P07 • Data direction programmable in nibble units • Use of pull-up resistor can be specified in nibble units • Input for HOLD release • Input for port 0 interrupt Port 1 I/O P10 to P17 • 8-bit input/output port Yes • Data direction programmable for each bit • Use of pull-up resistor can be specified for each bit individually • Other pin functions P10 : SIO0 data output P11 : SIO0 data input or bus input/output P12 : SIO0 clock input/output P13 : SIO1 data output P14 : SIO1 data input or bus input/output P15 : SIO1 clock input/output P16 : Timer 1 PWML output P17 : Timer 1 PWMH output/Buzzer output Port 3 I/O P30 to P35 • 6-bit input/output port Yes • Data direction can be specified for each bit • Use of pull-up resistor can be specified for each bit individually • Other functions P30 to p33 : INT4 input/HOLD release input/timer 1 event input Timer 0L capture input/Timer 0H capture input P34 to P35 : INT5 input/HOLD release input/timer 1 event input Timer 0L capture input/Timer 0H capture input • Interrupt detection selection Port 7 I/O P70 to P73 Rising Falling INT4 Yes Yes INT5 Yes Yes Rising and H level L level Yes No No Yes No No falling • 4-bit input/output port No • Data direction can be specified for each bit • Use of pull-up resistor can be specified for each bit individually • Other functions P70 : INT0 input/HOLD release input/Timer 0L capture input/output for watchdog timer P71 : INT1 input/HOLD release input/Timer 0H capture input P72 : INT2 input/HOLD release input/timer 0 event input/Timer 0L capture input P73 : INT3 input (noise rejection filter attached) /timer 0 event input/Timer 0H capture input AD input port : AN8 (P70), AN9 (P71) • Interrupt detection selection Port 8 I/O P80 to P87 Rising Falling INT0 Yes Yes INT1 Yes Yes INT2 Yes INT3 Yes Rising and H level L level No Yes Yes No Yes Yes Yes Yes No No Yes Yes No No falling • 8-bit input/output port No • Input/output can be specified for each bit individually • Other functions : AD input port : AN0 to AN7 Small signal detector input port : MICIN (P87) S0/PA0 to S7/PA7 I/O • Segment output for LCD No • Can be used as general purpose input/output port (PA) S8/PB0 to S15/PB7 I/O • Segment output for LCD No • Can be used as general purpose input/output port (PB) S16/PC0 to S23/PC7 I/O • Segment output for LCD No • Can be used as general purpose input/output port (PC) Continued on next page. No.7825-8/21 LC87F74C8A Continued from preceding page. Pin name I/O S24/PD0 to S31/PD7 I/O S32/PE0 to S39/PE7 I/O Function Option • Segment output for LCD No • Can be used as general purpose input/output port (PD) • Segment output for LCD No • Can be used as general purpose input/output port (PE) S40/PF0 to S47/PF7 I/O • Segment output for LCD No • Can be used as general purpose input/output port (PF) COM0/PL0 to I/O • Common output for LCD COM3/PL3 V1/PL4 to V3/PL6 No • Can be used as general purpose input port (PL) I/O • LCD output bias power supply No • Can be used as general purpose input port (PL) • Other functions : AD input ports : AN12 to AN14 RES I Reset terminal No XT1 I • Input for 32.768kHz crystal oscillation No • Other functions : General purpose input port AD input port : AN10 • When not in use, connect to VDD1 XT2 I/O • Output for 32.768kHz crystal oscillation No • Other functions : General purpose input port AD input port : AN11 • When not in use, set to oscillation mode and leave open CF1 I Input terminal for ceramic oscillator No CF2 O Output terminal for ceramic oscillator No Port output Configuration Port form and pull-up resistor options are shown in the following table. Port status can be read even when port is set to output mode. Terminal P00 to P07 P10 to P17 P30 to P35 Option applies to : each bit each bit each bit Option Output format Pull-up resistor 1 CMOS Programmable 2 Nch-open drain None 1 CMOS Programmable 2 Nch-open drain Programmable 1 CMOS Programmable 2 Nch-open drain None Programmable P70 – None Nch-open drain P71 to P73 – None CMOS Programmable P80 to P87 – None Nch-open drain None S0/PA0 to S47/PF7 – None CMOS Programmable COM0/PL0 to – None Input only None V1/PL4 to V3/PL6 – None Input only None XT1 – None Input only None XT2 – None Output for 32.768kHz crystal oscillation None (Note 1) COM3/PL3 Note 1 : Attachment of Port 0 programmable pull-up resistors is controllable in nibble units (P00 to 03, P04 to 07). * Note 1 : Connect as follows to reduce noise on VDD. VSS1, VSS2 and VSS3 must be connected together and grounded. * Note 2 : The power supply for the internal memory is VDD1 but it uses the VDD2 as the power supply for ports. When the VDD2 is not backed up, the port level does not become "H" even if the port latch is in the "H" level. Therefore, when the VDD2 is not backed up and the port latch is "H" level, the port level is unstable in the HOLD mode, and the back up time becomes shorter because the through current runs from VDD to GND in the input buffer. If VDD2 is not backed up, output "L" by the program or pull the port to "L" by the external circuit in the HOLD mode so that the port level becomes "L" level and unnecessary current consumption is prevented. No.7825-9/21 LC87F74C8A Back-up Capacitors *2 LSI VDD1 Power Supply VDD2 VDD3 VSS1 VSS2 VSS3 Absolute Maximum Ratings / Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pins Conditions Supply voltage VDD max VDD1, VDD2, VDD3 VDD1 = VDD2 = VDD3 Supply voltage VLCD V1/PL4, V2/PL5, V3/PL6 VDD1 = VDD2 = VDD3 for LCD Input voltage VI Port L XT1, XT2, CF1, RES Input/Output VIO(1) voltage • Port 0, 1, 3, 7, 8 • Port A, B, C, D, E, F High Peak level output output current current IOPH(1) Port 0, 1, 3 • CMOS output selected • Current at each pin Limits VDD [V] min typ unit +6.5 -0.3 VDD -0.3 VDD+0.3 -0.3 VDD+0.3 IOPH(2) Port 71, 72, 73 Current at each pin -3 IOPH(3) Port A, B, C, D, E, F Current at each pin -5 ΣIOAH(1) Port 0, 1, 32 to 35 Total of all pins -40 output ΣIOAH(2) Port 30, 31 Total of all pins -10 ΣIOAH(3) Port 7 Total of all pins -5 ΣIOAH(4) Port A, B, C Total of all pins -25 -25 ΣIOAH(5) Port D, E, F Total of all pins Low Peak IOPL(1) Port 0, 1, 32 to 35 Current at each pin 20 level output IOPL(2) Port 30, 31 Current at each pin 30 output current IOPL(3) Port 7, 8 Current at each pin 5 IOPL(4) Port A, B, C, D, E, F Current at each pin 15 Total ΣIOAL(1) Port 0, 1, 32 to 35 Total of all pins 60 output ΣIOAL(2) Port 30, 31 Total of all pins 60 ΣIOAL(3) Port 7, 8 Total of all pins 20 ΣIOAL(4) Port A, B, C Total of all pins 40 ΣIOAL(5) Port D, E, F Total of all pins 40 QIP100E Ta = -20 to +70°C current current Maximum power Pd max consumption Operating Storage temperature range 559 TQFP100 Topr temperature range Tstg V -10 Total current max -0.3 404 -20 70 -55 125 mA mW °C No.7825-10/21 LC87F74C8A Recommended Operating Range / Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Operating supply VDD(1) voltage range VDD(2) Supply voltage VHD Pins VDD1 = VDD2 = VDD3 VDD1 range in Hold Limits Conditions VDD [V] min typ max unit 0.294µs≤ tCYC≤200µs 4.5 5.5 0.735µs≤ tCYC≤200µs 3.0 5.5 2.0 5.5 3.0 to 5.5 0.3VDD +0.7 VDD 3.0 to 5.5 0.3VDD +0.7 VDD 3.0 to 5.5 0.75VDD VDD 3.0 to 5.5 0.9VDD VDD 3.0 to 5.5 0.75VDD 3.0 to 5.5 VSS VDD 0.15VDD 3.0 to 5.5 VSS 3.0 to 5.5 VSS 3.0 to 5.5 VSS 3.0 to 5.5 VSS 0.25VDD 4.5 to 5.5 0.294 200 3.0 to 5.5 0.735 200 4.5 to 5.5 0.1 10 3.0 to 5.5 0.1 4 4.5 to 5.5 0.2 20 3.0 to 5.5 0.2 8 Keep RAM and register data in HOLD mode. mode Input high voltage VIH(1) • Port 0, 3, 8 Output disable • Port A, B, C, D, E, F, L VIH(2) • Port 1 Output disable • Port 71, 72, 73 • P70 port input/interrupt VIH(3) P87 small signal input Output disable VIH(4) Port 70 Output disable Watchdog timer Input low voltage VIH(5) XT1, XT2, CF1, RES VIL(1) • Port 0, 3, 8 Output disable • Port A, B, C, D, E, F, L VIL(2) • Port 1 +0.4 Output disable • Port 71, 72, 73 0.1VDD +0.4 • P70 port input/interrupt VIL(3) Port 87 small signal Output disable input VIL(4) Port 70 Output disable Watchdog timer VIL(5) Operation cycle XT1, XT2, CF1, RES tCYC time External system FEXCF(1) CF1 clock frequency V 0.25VDD 0.8VDD -1.0 µs • CF2 open • System clock divider : 1/1 • External clock DUTY = 50 ± 5% • CF2 open • System clock divider : 1/2 Oscillation FmCF(1) CF1, CF2 frequency range 10MHz ceramic resonator oscillation (Note 1) MHz 4.5 to 5.5 10 3.0 to 5.5 4 Refer to figure 1 FmCF(2) CF1, CF2 4MHz ceramic resonator oscillation Refer to figure 1 FmRC RC oscillation FmMRC Frequency variable RC oscillation source 3.0 to 5.5 0.3 1.0 3.0 to 5.5 50 3.0 to 5.5 32.768 2.0 oscillation FsX’tal XT1, XT2 32.768kHz crystal resonator oscillation kHz Refer to figure 2 Note 1 : The parts value of oscillation circuit is shown in table 1 and table 2. No.7825-11/21 LC87F74C8A Electrical Characteristics / Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter High level input Symbol IIH(1) current Pins Conditions • Port 0, 1, 3, 7, 8 • Output disabled • Port A, B, C, D, E, F, L • Pull-up resister OFF. • VIN = VDD Limits VDD [V] min typ max unit 3.0 to 5.5 1 3.0 to 5.5 1 3.0 to 5.5 1 15 (Including OFF state leak current of the output Tr.) IIH(2) RES VIN = VDD IIH(3) XT1, XT2 When configured as an input port VIN = VDD Low level input IIH(4) CF1 VIN = VDD 3.0 to 5.5 IIH(5) P87/AN7/MICIN VIN = VBIS+0.5V small signal input (VBIS : Bias voltage) 3.0 to 5.5 • Port 0, 1, 3, 7, 8 • Output disabled • Port A, B, C, D, E, F, L • Pull-up resister OFF. IIL(1) current • VIN = VSS 4.2 8.5 15 µA 3.0 to 5.5 -1 3.0 to 5.5 -1 3.0 to 5.5 -1 3.0 to 5.5 -15 3.0 to 5.5 -15 (Including OFF state leak current of the output Tr.) IIL(2) RES VIN = VSS IIL(3) XT1, XT2 When configured as an input port VIN = VSS IIL(4) CF1 VIN = VSS IIL(5) P87/AN7/MICIN VIN = VBIS-0.5V small signal input (VBIS : Bias voltage) High level output VOH(1) Port 0, 1, 3, CMOS IOH = -1.0mA 4.5 to 5.5 voltage VOH(2) VOH(3) output option IOH = -0.1mA 3.0 to 5.5 VDD-1 VDD-0.5 Port 7 IOH = -0.4mA 3.0 to 5.5 VDD-1 VOH(4) Port A, B, C, D, E, F IOH = -1.0mA 4.5 to 5.5 IOH = -0.1mA 3.0 to 5.5 VDD-1 VDD-0.5 Low level output voltage VOH(5) VOL(1) Port 0, 1, 3 VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) Port 30, 31 Port 7, 8 Port A, B, C, D, E, F VOL(7) LCD output VODLS S0 to S47 voltage regulation -8.5 -4.2 IOL = 10mA 4.5 to 5.5 1.5 IOL = 1.6mA 3.0 to 5.5 0.4 IOL = 30mA IOL = 1mA 4.5 to 5.5 1.5 4.5 to 5.5 0.4 IOL = 0.5mA 3.0 to 5.5 0.4 IOL = 8mA IOL = 1.4mA 4.5 to 5.5 1.5 3.0 to 5.5 0.4 V IO = 0mA VLCD, 2/3VLCD, 1/3VLCD 3.0 to 5.5 0 ± 0.2 3.0 to 5.5 0 ± 0.2 level output Refer to figure 8 VODLC COM0 to COM3 IO = 0mA VLCD, 2/3VLCD, 1/2VLCD 1/3VLCD level output Refer to figure 8 LCD bias resistor RLCD(1) Resistance per one bias Refer to figure 8 resistor RLCD(2) • Resistance per one 3.0 to 5.5 60 3.0 to 5.5 30 Refer to figure 8 bias resistor kΩ • 1/2R mode Resistance of Rpu pull-up MOS Tr. Hysterisis voltage • Port 0, 1, 3, 7 • Port A, B, C, D, E, F VHIS(1) • Port 1, 7 • RES VHIS(2) Port 87 small signal input VOH = 0.9VDD 4.5 to 5.5 15 40 70 3.0 to 5.5 25 70 150 3.0 to 5.5 0.1VDD 3.0 to 5.5 0.1VDD V Continued on next page. No.7825-12/21 LC87F74C8A Continued from preceding page. Parameter Pin capacitance Symbol Pins CP Conditions All pins Limits VDD [V] min typ max unit • All other terminals connected to VSS. • f = 1MHz 3.0 to 5.5 10 pF • Ta = 25°C Input sensitivity Vsen Port 87 small signal 3.0 to 5.5 input 0.12VDD Vp-p Serial Input/Output Characteristics / Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Input clock Cycle time Symbol tSCK(1) Low level pulse tSCKL(1) width tSCKLA(1) High level pulse tSCKH(1) width tSCKHA(1) Cycle time tSCK(2) Low level pulse tSCKL(2) Pins SCK0 (P12) Conditions Refer to figure 6 Serial clock Output clock tSCKL(3) width tSCKLA(2) High level pulse tSCKH(3) width tSCKHA(2) Cycle time tSCK(4) Low level pulse tSCKL(4) Refer to figure 6 2/3 1 SCK0 (P12) • CMOS output 4/3 • Refer to figure 6 1/2 3.0 to 5.5 3/4 2 SCK1 (P15) • CMOS output 2 1/2 tSCK tSCKH(4) Serial input Serial output Data hold time thDI Output delay time tdDO tCYC • Refer to figure 6 3.0 to 5.5 tsDI tSCK 1/2 1/2 width Data set-up time tCYC 2 1 width High level pulse unit 3 SCK1 (P15) tSCKH(2) tSCK(3) max 2/3 width Low level pulse typ 2/3 3.0 to 5.5 Cycle time min 4/3 3.0 to 5.5 width High level pulse Limits VDD [V] SI0 (P11), • Measured with respect to SI1 (P14), SI0CLK leading edge. SB0 (P11), • Refer to figure 6 SB1 (P14) SO0 (P10), • When Port is open drain : SO1 (P13), Time delay form SIOCLK SB0 (011), trailing edge to the SO SB1 (P14) data change • Refer to figure 6 4.5 to 5.5 0.03 3.0 to 5.5 0.1 4.5 to 5.5 0.03 3.0 to 5.5 0.1 4.5 to 5.5 3.0 to 5.5 1/3 tCYC µs +0.05 1/3 tCYC +0.25 No.7825-13/21 LC87F74C8A Pulse Input Conditions / Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pins High/low level tPIH(1) INT0 (P70), pulse width tPIL(1) INT1 (P71), Conditions Limits VDD [V] min typ max unit • Condition that interrupt is accepted INT2 (P72) • Condition that event input INT4 (P30 to P33) 3.0 to 5.5 1 3.0 to 5.5 2 3.0 to 5.5 64 3.0 to 5.5 256 3.0 to 5.5 1 3.0 to 5.5 200 to timer 0 is accepted INT5 (P34 to P35) tPIH(2) INT3 (P73) tPIL(2) (Noise rejection ratio is 1/1.) • Condition that interrupt is accepted • Condition that event input to timer 0 is accepted tPIH(3) INT3 (P73) tPIL(3) (Noise rejection ratio is 1/32.) • Condition that interrupt is accepted • Condition that event input tCYC to timer 0 is accepted tPIH(4) INT3 (P73) • Condition that interrupt is tPIL(4) (Noise rejection ratio is accepted 1/128.) • Condition that event input MICIN (P87) • Condition that signal is to timer 0 is accepted tPIL(5) tPIL(5) accepted to small signal detection counter. tPIL(6) RES • Condition that reset is accepted µs AD Converter Characteristics / Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pins Resolution N AN0 (P80) Absolute precision ET to AN7 (P87) Conversion time tCAD AN8 (P70) AN9 (P71) AN10 (XT1) Limits Conditions VDD [V] (Note 2) AD conversion time = 32 × tCYC (ADCR2 = 0) (Note 3) 4.0 to 5.5 3.0 to 5.5 AN13 (V2) AD conversion time = 64 × tCYC (ADCR2 = 1) (Note 3) 4.5 to 5.5 3.0 to 5.5 VAIN 3.0 to 5.5 voltage range Analog port input IAINH VAIN = VDD 3.0 to 5.5 current IAINL VAIN = VSS 3.0 to 5.5 max unit 8 3.0 to 5.5 AN12 (V1) Analog input typ 3.0 to 5.5 AN11 (XT2) AN14 (V3) min bit ±1.5 15.62 97.92 (tCYC = (tCYC = 0.488µs) 3.06µs) 23.52 97.92 (tCYC = (tCYC = 0.735µs) 3.06µs) 18.82 97.92 (tCYC = (tCYC = 0.294µs) 1.53µs) 47.04 97.92 (tCYC = (tCYC = 0.735µs) 1.53µs) VSS VDD 1 -1 LSB µs V µA Note 2 : Absolute precision does not include quantizing error (±1/2 LSB). Note 3 : Conversion time means time from executing AD conversion instruction to loading complete digital value to register. No.7825-14/21 LC87F74C8A Current Dissipation Characteristics / Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Current Symbol IDDOP(1) Pins Conditions consumption VDD1 = VDD2 = • FsX’tal = 32.768kHz crystal oscillation during normal VDD3 • System clock : CF 10MHz oscillation operation min typ max unit • FmCF = 10MHz Ceramic resonator oscillation • Frequency variable RC oscillation stopped (Note 4) Limits VDD [V] 4.5 to 5.5 16 35 4.5 to 5.5 17 36 4.5 to 5.5 7 21 • Internal RC oscillation stopped. • Divider : 1/1 IDDOP(2) • CF1 = 20MHz external clock • FsX’tal = 32.768kHz crystal oscillation • System clock : CF1 oscillation • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped • Divider : 1/2 • FmCF = 4MHz Ceramic resonator oscillation IDDOP(3) • FsX’tal = 32.768kHz crystal oscillation mA • System clock : CF 4MHz oscillation IDDOP(4) • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped 3.0 to 4.5 3 13 4.5 to 5.5 1.5 11 3.0 to 4.5 0.8 7 4.5 to 5.5 2.5 13 3.0 to 4.5 1.8 9 4.5 to 5.5 80 450 • Divider : 1/1 IDDOP(5) • FmCF = 0Hz (No oscillation) • FsX’tal = 32.768kHz crystal oscillation • Frequency variable RC oscillation stopped IDDOP(6) • System clock : RC oscillation • Divider : 1/2 IDDOP(7) • FmCF = 0Hz (No oscillation) • FsX’tal = 32.768kHz crystal oscillation • Internal RC oscillation stopped. • System clock : 1MHz with frequency variable IDDOP(8) RC oscillation • Divider : 1/2 • FmCF = 0Hz (No oscillation) IDDOP(9) • FsX’tal = 32.768kHz crystal oscillation • System clock : 32.768kHz µA • Internal RC oscillation stopped. IDDOP(10) • Frequency variable RC oscillation stopped 3.0 to 4.5 35 250 4.5 to 5.5 4.6 12 4.5 to 5.5 5.1 13 4.5 to 5.5 2.2 6 3.0 to 4.5 1.0 5 • Divider : 1/2 Current IDDHALT(1) HALT mode consumption VDD1 = VDD2 = • FmCF = 10MHz Ceramic resonator oscillation during HALT VDD3 • FsX’tal = 32.768kHz crystal oscillation mode • System clock : CF 10MHz oscillation (Note 4) • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped • Divider : 1/1 IDDHALT(2) HALT mode • CF1 = 20MHz external clock • FsX’tal = 32.768kHz crystal oscillation • System clock : CF1 oscillation mA • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped • Divider : 1/2 IDDHALT(3) HALT mode • FmCF = 4MHz ceramic resonator oscillation • FsX’tal = 32.768kHz crystal oscillation IDDHALT(4) • System clock : CF 4MHz oscillation • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped • Divider : 1/1 Continued on next page. No.7825-15/21 LC87F74C8A Continued from preceding page. Parameter Symbol Pins Limits Conditions VDD [V] HALT mode consumption VDD1 = VDD2 = during HALT VDD3 • FsX’tal = 32.768kHz crystal oscillation Current IDDHALT(5) • FmCF = 0Hz (Oscillation stop) IDDHALT(6) mode min typ max 4.5 to 5.5 600 1600 3.0 to 4.5 350 1300 4.5 to 5.5 1500 3600 3.0 to 4.5 1250 3300 4.5 to 5.5 25 100 3.0 to 4.5 12 60 4.5 to 5.5 0.1 25 3.0 to 4.5 0.03 20 4.5 to 5.5 20 90 3.0 to 4.5 8 50 unit • System clock : RC oscillation • Frequency variable RC oscillation stopped (Note 4) • Divider : 1/2 IDDHALT(7) HALT mode • FmCF = 0Hz (No oscillation) • FsX’tal = 32.768kHz crystal oscillation • Internal RC oscillation stopped. IDDHALT(8) µA • System clock : 1MHz with frequency variable RC oscillation • Divider : 1/2 HALT mode IDDHALT(9) • FmCF = 0Hz (Oscillation stop) • FsX’tal = 32.768kHz crystal oscillation • System clock : 32.768kHz IDDHALT(10) • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped • Divider : 1/2 Current IDDHOLD(1) VDD1 HOLD mode consumption • CF1 = VDD or open during HOLD (when using external clock) IDDHOLD(2) mode Current IDDHOLD(3) VDD1 µA Date/time clock HOLD mode consumption during Date/time clock • CF1 = VDD or open IDDHOLD(4) (when using external clock) HOLD mode • FmX’tal = 32.768kHz crystal oscillation Note 4 : The currents through the output transistors and the pull-up MOS transistors are ignored. F-ROM Write Characteristics / Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol On-board write IDDF(1) current Pins VDD1 Limits Conditions VDD [V] • 128-byte write • Including erase current Write cycle time tFW(1) min typ max unit 4.5 to 5.5 30 65 mA 4.5 to 5.5 6.3 9 mS • 128-byte write • Including erase current • Not including time to prepare 128-byte data Main System Clock Oscillation Circuit Characteristics The characteristics in the table bellow is based on the following conditions : 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer Table 1. Main system clock oscillation circuit characteristics using ceramic resonator Circuit parameters Frequency Manufacturer 10MHz Murata 4MHz Murata Oscillator C1 C2 Rd1 Operating Oscillation supply voltage stabilizing time range typ max Notes [pF] [pF] [Ω] [V] [mS] [mS] CSTCE10M0G52-R0 (10) (10) 220 4.5 to 5.5 0.05 0.15 Built-in C1, C2 CSTLS10M0G53-B0 (10) (10) 220 4.5 to 5.5 0.05 0.15 Built-in C1, C2 CSTCR4M00G53-R0 (15) (15) 1k 3.0 to 5.5 0.05 0.15 Built-in C1, C2 CSTLS4M00G53-B0 (15) (15) 470 3.0 to 5.5 0.05 0.15 Built-in C1, C2 The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (Refer to Figure 4) No.7825-16/21 LC87F74C8A Subsystem Clock Oscillation Circuit Characteristics The characteristics in the table bellow is based on the following conditions : 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer Table 2. Subsystem clock oscillation circuit characteristics using crystal oscillator Circuit parameters Frequency Manufacturer SEIKO 32.768kHz EPSON Oscillator MC-306 Oscillation Operating supply C3 C4 Rf Rd2 [pF] [pF] [Ω] [Ω] 18 18 OPEN 560k stabilizing time voltage range [V] 3.0 to 5.5 typ max [S] [S] 1.553 3.00 Notes The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the HOLD mode. (Refer to Figure 4) Notes : Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. CF1 XT1 CF2 Rd1 C1 CF C2 XT2 Rf C3 Rd2 C4 X’tal Figure 1 Ceramic oscillation circuit Figure 2 Crystal oscillation circuit 0.5VDD Figure 3 AC timing measurement point No.7825-17/21 LC87F74C8A VDD Power VDD limit 0V Reset time RES Internal RC Resonator tmsCF CF1, CF2 tmsXtal XT1, XT2 Operation mode Unfixed Reset Instruction execution mode Reset time and oscillation stable time HOLD release Without HOLD Release HOLD release signal VALID Internal RC Resonator tmsCF CF1, CF2 tmsXtal XT1, XT2 Operation mode HOLD HALT HOLD release signal and oscillation stable time Figure 4 Oscillation stabilizing time No.7825-18/21 LC87F74C8A VDD RRES (Note) Select CRES and RRES value to assure that at least 200µs reset time is generated after the VDD becomes higher than the minimum operating voltage. RES CRES Figure 5 Reset circuit SIOCLK DATAIN DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 Data RAM transmission period (only SIO0) tSCK tSCKL tSCKH SIOCLK tsDI thDI DATAIN tdDO DATAOUT Data RAM transmission period (only SIO0) tSCKLA tSCKHA SIOCLK tsDI thDI DATAIN tdDO DATAOUT Figure 6 Serial input/output wave form No.7825-19/21 LC87F74C8A tPIL tPIH Figure 7 Pulse input timing VDD SW : ON/OFF (programmable) RLCD RLCD SW : ON (VLCD = VDD) RLCD RLCD VLCD RLCD RLCD 2/3VLCD RLCD 1/2VLCD RLCD 1/3VLCD RLCD RLCD GND Figure 8 LCD bias resistor No.7825-20/21 LC87F74C8A PS No.7825-21/21