L6258EP PWM CONTROLLED - HIGH CURRENT DMOS UNIVERSAL MOTOR DRIVER DATASHEET 1 ■ ■ ■ ■ ■ ■ ■ ■ ■ 2 FEATURES Figure 1. Package ABLE TO DRIVE BOTH WINDINGS OF A BIPOLAR STEPPER MOTOR OR TWO DC MOTORS OUTPUT CURRENT UP TO 1.3A EACH WINDING WIDE VOLTAGE RANGE: 12V TO 40V FOUR QUADRANT CURRENT CONTROL, IDEAL FOR MICROSTEPPING AND DC MOTOR CONTROL PRECISION PWM CONTROL NO NEED FOR RECIRCULATION DIODES TTL/CMOS COMPATIBLE INPUTS CROSS CONDUCTION PROTECTION THERMAL SHUTDOW PowerSSO36 Table 1. Order Codes Part Number Package E-L6258EP PowerSSO36 complete control and drive circuit. It has high efficiency phase shift chopping that allows a very low current ripple at the lowest current control levels, and makes this device ideal for steppers as well as for DC motors.The power stage is a dual DMOS full bridge capable of sustaining up to 40V, and includes the diodes for current recirculation.The output current capability is 1.3A per winding in continuous mode, with peak start-up current up to 2A. A thermal protection circuitry disables the outputs if the chip temperature exceeds the safe limits. DESCRIPTION L6258EP is a dual full bridge for motor control applications realized in BCD technology, with the capability of driving both windings of a bipolar stepper motor or bidirectionally control two DC motors. L6258EP and a few external components form a Figure 2. Block Diagram R1 1M CP VCP1 VCP2 EA_IN1 CHARGE PUMP + VREF1 INPUT & SENSE AMP I3_1 I1_1 DAC VS EA_OUT1 TRI_0 VR I2_1 CBOOT CC1 RC1 TRI_180 - + - ERROR AMP + - VBOOT OUT1A C POWER BRIDGE 1 C OUT1B SENSE1B Rs I0_1 PH_1 VDD(5V) SENSE1A VR GEN VR (VDD/2) DISABLE THERMAL PROT. VS VREF1 VR I3_2 I2_2 I1_2 INPUT & SENSE AMP DAC I0_2 + ERROR AMP + TRI_180 TRIANGLE GENERATOR + - - PH_2 TRI_CAP TRI_0 - OUT2A C C POWER BRIDGE 2 OUT2B SENSE2B Rs TRI_0 TRI_180 CFREF SENSE2A GND EA_IN2 EA_OUT2 D96IN430D RC2 CC2 R2 1M July 2005 Rev. 3 1/22 L6258EP Table 2. Absolute Maximum Ratings Symbol Vs VDD Vref1/Vref2 Parameter Value Unit Supply Voltage 45 V Logic Supply Voltage 7 V 2.5 V 2 A 1.3 A -0.3 to 7 V Bootstrap Supply 60 V Maximum Vgate applicable 15 V Junction Temperature 150 °C -55 to 150 °C Reference Voltage IO Output Current (peak) (1) IO Output Current (continuous) Vin Logic Input Voltage Range Vboot Vboot - Vs Tj Tstg Storage Temperature Range (1) This current is intended as not repetitive current for max. 1 second. Figure 3. Pin Connection (Top view) PWR_GND 1 36 PWR_GND PH_1 2 35 SENSE1 I1_1 3 34 OUT1B I0_1 4 33 I3_1 OUT1A 5 32 I2_1 DISABLE 6 31 VS TRI_CAP 7 30 EA_OUT1 VCC 8 29 EA_IN1 GND 9 28 VREF1 VCP1 10 27 SIG_GND VCP2 11 26 VREF2 VBOOT 12 25 EA_IN2 VS 13 24 EA_OUT2 OUT2A 14 23 I2_2 I0_2 15 22 I3_2 I1_2 16 21 OUT2B PH_2 17 20 SENSE2 PWR_GND 18 19 PWR_GND D96IN432E 2/22 L6258EP Table 3. Pins Function Pin # Name Description 1, 36 PWR_GND Ground connection (1). They also conduct heat from die to printed circuit copper. 2, 17 PH_1, PH_2 These TTL compatible logic inputs set the direction of current flow through the load. A high level causes current to flow from OUTPUT A to OUTPUT B. 3 I1_1 Logic input of the internal DAC (1). The output voltage of the DAC is a percentage of the Vref voltage applied according to the thruth table of page 7 4 I0_1 See pin 3 5 OUT1A 6 DISABLE Bridge output connection (1) Disables the bridges for additional safety during switching. When not connected the bridges are enabled 7 TRI_cap Triangular wave generation circuit capacitor. The value of this capacitor defines the output switching frequency 8 VDD (5V) Supply Voltage Input for logic circuitry 9 GND Power Ground connection of the internal charge pump circuit 10 VCP1 Charge pump oscillator output 11 VCP2 Input for external charge pump capacitor 12 VBOOT Overvoltage input for driving of the upper DMOS Supply voltage input for output stage. They are shorted internally 13, 31 VS 14 OUT2A 15 I0_2 Logic input of the internal DAC (2). The output voltage of the DAC is a percentage of the VRef voltage applied according to the truth table of page 7 See pin 15 Bridge output connection (2) 16 I1_2 18, 19 PWR_GND 20, 35 SENSE2, SENSE1 21 OUT2B 22 I3_2 See pin 15 23 I2_2 See pin 15 24 EA_OUT_2 25 EA_IN_2 26, 28 VREF2, VREF1 27 SIG_GND Ground connection. They also conduct heat from die to printed circuit copper Negative input of the transconductance input amplifier (2, 1) Bridge output connection and positive input of the tranconductance (2) Error amplifier output (2) Negative input of error amplifier (2) Reference voltages for the internal DACs, determining the output current value. Output current also depends on the logic inputs of the DAC and on the sensing resistor value Signal ground connection 29 EA_IN_1 30 EA_OUT_1 Negative input of error amplifier (1) 32 I2_1 See pin 3 33 I3_1 See pin 3 34 OUT1B Error amplifier output (1) Bridge output connection and positive input of the tranconductance (1) Note: The number in parenthesis shows the relevant Power Bridge of the circuit. Pins 18, 19, 1 and 36 are connected together. 3/22 L6258EP Table 4. Electrical Characteristics (VS = 40V; VDD = 5V; Tj = 25°; unless otherwise specified.) Symbol VS VDD Parameter Test Condition Supply Voltage Min. Typ. Max. Unit 12 40 V 4.75 5.25 V VS = 12 to 40V VS+6 VS+12 V Logic Supply Voltage VBOOT Storage Voltage VSense Max Drop Across Sense Resistor 1.25 V VS(off) Power off Reset Off Threshold 6 7.2 V VDD(off) 3.3 Power off Reset Off Threshold 4.1 V IS(on) VS Quiescent Current Both bridges ON, No Load 15 mA IS(off) VS Quiescent Current Both bridges OFF 7 mA IDD VDD Operative Current 15 mA ∆TSD-H Shut Down Hysteresis 25 TSD Thermal shutdown fosc Triangular Oscillator Frequency (*) CFREF = 1nF °C 150 12.5 °C 15 18.5 KHz 500 µA 0.6 0.75 Ω 1 1.4 V TRANSISTORS IDSS Rds(on) Vf Leakage Current OFF State On Resistance ON State Flywheel diode Voltage If =1.0A CONTROL LOGIC Vin(H) lnput Voltage All Inputs 2 VDD V Vin(L) Input Voltage All Inputs 0 0.8 V Iin Input Current (Note 1) 0 < Vin < 5V -150 +10 µA Idis Disable Pin Input Current Vref1/ref2 Iref -10 +150 µA Reference Voltage operating 0 2.5 V Vref Terminal Input Current Vref = 1.25 -2 5 µA PWM Loop Transfer Ratio FI = Vref/Vsense VFS Voffset 2 DAC Full Scale Precision Vref = 2.5V I0/I1/I2/I3 = L 1.23 1.34 V Current Loop Offset Vref = 2.5V I0/I1/I2/I3 = H -40 +40 mV DAC Factor Ratio Normalized @ Full scale Value -2 +2 % -0.7 VS+0.7 V -200 0 µA SENSE AMPLIFIER Vcm lnput Common Mode Voltage Range Iinp Input Bias sense1/sense2 ERROR AMPLIFIER GV Open Loop Voltage Gain SR Output Slew Rate GBW Open Loop Gain Bandwidth Product Note 1: This is true for all the logic inputs except the disable input. (*) Chopping frequency is twice fosc value. 4/22 70 dB 0.2 V/µs 400 kHz L6258EP 3 FUNCTIONAL DESCRIPTION The circuit is intended to drive both windings of a bipolar stepper motor or two DC motors. The current control is generated through a switch mode regulation. With this system the direction and the amplitude of the load current are depending on the relation of phase and duty cycle between the two outputs of the current control loop. The L6258EP power stage is composed by power DMOS in bridge configuration as it is shown in figure 4, where the bridge outputs OUT_A and OUT_B are driven to Vs with an high level at the inputs IN_A and IN_B while are driven to ground with a low level at the same inputs . The zero current condition is obtained by driving the two half bridge using signals IN_A and IN_B with the same phase and 50% of duty cycle. In this case the outputs of the two half bridges are continuously switched between power supply (Vs) and ground, but keeping the differential voltage across the load equal to zero. In figure 4A is shown the timing diagram of the two outputs and the load current for this working condition. Following we consider positive the current flowing into the load with a direction from OUT_A to OUT_B, while we consider negative the current flowing into load with a direction from OUT_B to OUT_A. Now just increasing the duty cycle of the IN_A signal and decreasing the duty cycle of IN_B signal we drive positive current into the load. In this way the two outputs are not in phase, and the current can flow into the load trough the diagonal bridge formed by T1 and T4 when the output OUT_A is driven to Vs and the output OUT_B is driven to ground, while there will be a current recirculation into the higher side of the bridge, through T1 and T2, when both the outputs are at Vs and a current recirculation into the lower side of the bridge, through T3 and T4, when both the outputs are connected to ground. Since the voltage applied to the load for recirculation is low, the resulting current discharge time constant is higher than the current charging time constant during the period in which the current flows into the load through the diagonal bridge formed by T1 and T4. In this way the load current will be positive with an average amplitude depending on the difference in duty cycle of the two driving signals. In figure 4B is shown the timing diagram in the case of positive load current On the contrary, if we want to drive negative current into the load is necessary to decrease the duty cycle of the IN_A signal and increase the duty cycle of the IN_B signal. In this way we obtain a phase shift between the two outputs such to have current flowing into the diagonal bridge formed by T2 and T3 when the output OUT_A is driven to ground and output OUT_B is driven to Vs, while we will have the same current recirculation conditions of the previous case when both the outputs are driven to Vs or to ground. So, in this case the load current will be negative with an average amplitude always depending by the difference in duty cycle of the two driving signals. In figure 4C is shown the timing diagram in the case of negative load current . Figure 5 shows the device block diagram of the complete current control loop. 3.1 Reference Voltage The voltage applied to VREF pin is the reference for the internal DAC and, together with the sense resistor value, defines the maximum current into the motor winding according to the following relation: 0.5 ⋅ V REF 1 V REF I MAX = -------------------------- = ----- ⋅ -------------FI R S RS where Rs = sense resistor value 5/22 L6258EP Figure 4. Power Bridge Configuration VS IN_A IN_B T1 OUT_A T3 T2 LOAD OUT_B T4 OUTA OUTB Fig. 4A Iload 0 OUTA OUTB Fig. 4B Iload 0 OUTA OUTB Fig. 4C 0 Iload D97IN624 6/22 L6258EP Figure 5. Current Control Loop Block Diagram POWER AMPL. VS OUTA Tri_0 INPUT TRANSCONDUCTANCE ERROR AMPL. AMPL. RL + LL VR VS + - ia VREF RS - I0 ic + I1 DAC Tri_180 VDAC - I2 Rc + OUTB Cc I3 PH LOAD - ib Gin=1/Ra VSENSE + D97IN625 Gs=1/Rb SENSE TRANSCONDUCTANCE AMPL. 3.2 Input Logic (I0 - I1 - I2 - I3) The current level in the motor winding is selected according to this table: Table 5. I3 I2 I1 I0 Current level % of IMAX H H H H No Current H H H L 9.5 H H L H 19.1 H H L L 28.6 H L H H 38.1 H L H L 47.6 H L L H 55.6 H L L L 63.5 L H H H 71.4 L H H L 77.8 L H L H 82.5 L H L L 88.9 L L H H 92.1 L L H L 95.2 L L L H 98.4 L L L L 100 7/22 L6258EP 3.3 Phase Input ( PH ) The logic level applied to this input determines the direction of the current flowing in the winding of the motor. High level on the phase input causes the motor current flowing from OUT_A to OUT_B through the load. 3.4 Triangular Generator This circuit generates the two triangular waves TRI_0 and TRI_180 internally used to generate the duty cycle variation of the signals driving the output stage in bridge configuration. The frequency of the triangular wave defines the switching frequency of the output, and can be adjusted by changing the capacitor connected at TR1_CAP pin : K F ref = ---C where : K = 1.5 x 10-5 3.5 Charge Pump Circuit To ensure the correct driving of the high side drivers a voltage higher than Vs is supplied on the Vboot pin. This boostrap voltage is not needed for the low side power DMOS transistors because their sources terminals are grounded. To produce this voltage a charge pump method is used. It is made by using two external capacitors; one connected to the internal oscillator (CP) and the other (Cboot) to storage the overvoltage needed for the driving the gates of the high side DMOS. The value suggested for the capacitors are: Table 6. Cboot Storage Capacitor 100 nF CP PumpCapacitor 10 nF 3.6 Current Control LOOP The current control loop is a transconductance amplifier working in PWM mode. The motor current is a function of the programmed DAC voltage. To keep under control the output current, the current control modulates the duty cycle of the two outputs OUT_A and OUT_B, and a sensing resistor Rs is connected in series with the motor winding in order to produce a voltage feedback compared with the programmed voltage of the DAC . The duty cycle modulation of the two outputs is generated comparing the voltage at the outputs of the error amplifier, with the two triangular wave references . In order to drive the output bridge with the duty cycle modulation explained before, the signals driving each output ( OUTA & OUTB ) are generated by the use of the two comparators having as reference two triangular wave signals Tri_0 and Tri_180 of the same amplitude, the same average value (in our case Vr), but with a 180° of phase shift each other. The two triangular wave references are respectively applied to the inverting input of the first comparator and to the non inverting input of the second comparator. The other two inputs of the comparators are connected together to the error amplifier output voltage resulting by the difference between the programmed DAC. The reset of the comparison between the mentioned signals is shown in fig. 6. 8/22 L6258EP Figure 6. Output comparator waveforms Tri_0 Error Ampl. Output Tri_180 First Comp. Output Second Comp. Output In the case of VDAC equal to zero, the transconductance loop is balanced at the value of Vr, so the outputs of the two comparators are signals having the same phase and 50% of duty cycle . As we have already mentioned, in this situation, the two outputs OUT_A and OUT_B are simultaneously driven from Vs to ground ; and the differential voltage across the load in this case is zero and no current flows in the motor winding. With a positive differential voltage on VDAC (see Fig. 5), the transconductance loop will be positively unbalanced respected Vr. In this case being the error amplifier output voltage greater than Vr, the output of the first comparator is a square wave with a duty cycle higher than 50%, while the output of the second comparator is a square wave with a duty cycle lower than 50%. The variation in duty cycle obtained at the outputs of the two comparators is the same, but one is positive and the other is negative with respect to the 50% level. The two driving signals, generated in this case, drive the two outputs in such a way to have switched current flowing from OUT_A through the motor winding to OUT_B. With a negative differential voltage VDAC, the transconductance loop will be negatively unbalanced respected Vr. In this case the output of the first comparator is a square wave with a duty cycle lower than 50%, while the output of the second comparator is a square wave with a duty cycle higher than 50%. The variation in the duty cycle obtained at the outputs of the two comparators is always of the same. The two driving signals, generated in this case, drive the the two outputs in order to have the switched current flowing from OUT_B through the motor winding to OUT_A. 3.7 Current Control Loop Compensation In order to have a flexible system able to drive motors with different electrical characteristics, the non inverting input and the output of the error amplifier ( EA_OUT ) are available. Connecting at these pins an external RC compensation network it is possible to adjust the gain and the bandwidth of the current control loop. 9/22 L6258EP 4 PWM CURRENT CONTROL LOOP 4.1 Open Loop Transfer Function Analysis Block diagram : refer to Fig. 5. Table 7. Application data: VS = 24V Gs transconductance gain = 1/Rb LL = 12mH Gin transconductance gain = 1/Ra RL = 12Ω Ampl. of the Tria_0_180 ref. = 1.6V (peak to peak) RS = 0.33Ω Ra = 40KΩ RC = to be calculated Rb = 20KΩ CC = to be calculated Vr = Internal reference equal to VDD/2 (Typ. 2.5V) these data refer to a typical application, and will be used as an example during the analysis of the stability of the current control loop. The block diagram shows the schematics of the L6258EP internal current control loop working in PWM mode; the current into the load is a function of the input control voltage VDAC , and the relation between the two variables is given by the following formula: Iload · RS · GS = VDAC · Gin 1 1 I LOAD ⋅ R S ⋅ ------- = V DAC ⋅ ------Rb Ra Rb V DAC I LOAD = V DAC ⋅ ------------------ = 0.5 ⋅ --------------- ( A ) Ra ⋅ Rs RS where: VDAC is the control voltage defining the load current value Gin is the gain of the input transconductance amplifier ( 1/Ra ) Gs is the gain of the sense transconductance amplifier ( 1/Rb ) Rs is the resistor connected in series to the output to sense the load current In this configuration the input voltage is compared with the feedback voltage coming from the sense resistor, then the difference between this two signals is amplified by the error amplifier in order to have an error signal controlling the duty cycle of the output stage keeping the load current under control. It is clear that to have a good performance of the current control loop, the error amplifier must have an high DC gain and a large bandwidth . Gain and bandwidth must be chosen depending on many parameters of the application, like the characteristics of the load, power supply etc..., and most important is the stability of the system that must always be guaranteed. To have a very flexible system and to have the possibility to adapt the system to any application, the error amplifier must be compensated using an RC network connected between the output and the negative input of the same. For the evaluation of the stability of the system, we have to consider the open loop gain of the current control loop: 10/22 L6258EP Aloop = ACerr · ACpw · ACload · ACsense where AC... is the gain of the blocks that refers to the error, power and sense amplifier plus the attenuation of the load block. The same formula in dB can be written in this way: AloopdB = ACerrdB + ACpwdB + ACloaddB + ACsensedB So now we can start to analyse the dynamic characteristics of each single block, with particular attention to the error amplifier. 4.2 Power Amplifier The power amplifier is not a linear amplifier, but is a circuit driving in PWM mode the output stage in full bridge configuration. The output duty cycle variation is given by the comparison between the voltage of the error amplifier and two triangular wave references Tri_0 and Tri_180. Because all the current control loop is referred to the Vr reference, the result is that when the output voltage of the error amplifier is equal to the Vr voltage the two output Out_A and Out_B have the same phase and duty cycle at 50%; increasing the output voltage of the error amplifier above the Vr voltage, the duty cycle of the Out_A increases and the duty cycle of the Out_B decreases of the same percentage; on the contrary decreasing the voltage of the error amplifier below the Vr voltage, the duty cycle of the Out_A decreases and the duty cycle of the Out_B increases of the same percentage. The gain of this block is defined by the amplitude of the two triangular wave references; more precisely the gain of the power amplifier block is a reversed proportion of the amplitude of the two references. In fact a variation of the error amplifier output voltage produces a larger variation in duty cycle of the two outputs Out_A and Out_B in case of low amplitude of the two triangular wave references. The duty cycle has the max value of 100% when the input voltage is equal to the amplitude of the two triangular references. The transfer function of this block consist in the relation between the output duty cycle and the amplitude of the triangular references. Vout = 2 · VS · (0.5 - DutyCycle) ∆V out 2 ⋅ VS - = -----------------------------------------------------ACpw dB = 20 ⋅ log -------------∆V in Triangular Amplitude 2 ⋅ 24 ACpw dB = 10 ⋅ log -------------- = 29.5dB 1.6 Moreover, having the two references Tri_0 and Tri_180 a triangular shape it is clear that the transfer function of this block is a linear constant gain without poles and zeros. 4.3 Load Attenuation The load block is composed by the equivalent circuit of the motor winding (resistance and inductance) plus the sense resistor. We will considered the effect of the Bemf voltage of the motor in the next chapter. The input of this block is the PWM voltage of the power amplifier and as output we have the voltage across the sense resistor produced by the current flowing into the motor winding. The relation between the two variable is : V out V sense = --------------------- ⋅ R S RL + RS 11/22 L6258EP so the gain of this block is: V sense RS ACload = ----------------- = -------------------v out RL + RS RS ACload dB = 20 ⋅ log -------------------RL + RS 0.33 Aload dB = 20 ⋅ log ------------------------ = – 31.4dB 12 + 0.33 where: RL = equivalent resistance of the motor winding RS = sense resistor Because of the inductance of the motor LL, the load has a pole at the frequency : 1 Fpole = -------------------------------LL 2π ⋅ --------------------RL + RS 1 - = 163Hz Fpole = ---------------------------------------–3 12 ⋅ 10 6.28 ⋅ -----------------------12 + 0.33 Before analysing the error amplifier block and the sense transconductance block, we have to do this consideration : AloopdB = AxdB + BxdB Ax|dB = ACpw|dB + ACload|dB and Bx|dB = ACerr|dB + ACsense|dB this means that Ax|dB is the sum of the power amplifier and load blocks; Ax|dB = (29,5) + (-31.4) = -1.9dB The BODE analysis of the transfer function of Ax is: Figure 7. 12/22 L6258EP The Bode plot of the Ax|dB function shows a DC gain of -1.9dB and a pole at 163Hz. It is clear now that (because of the negative gain of the Ax function), Bx function must have an high DC gain in order to increment the total open loop gain increasing the bandwidth too. 4.4 Error Amplifier and Sense Amplifier As explained before the gain of these two blocks is : BxdB = ACerrdB + ACsensedB Being the voltage across the sense resistor the input of the Bx block and the error amplifier voltage the output of the same, the voltage gain is given by : 1 ib = Vsense ⋅ Gs = Vsense ⋅ -------Rb 1 Verr_out = -(ic · Zc) so ic = -(Verr_out · ------- ) Zc because ib = icwe have: 1 1 Vsense · -------- = -(Verr_out · ------- ) Rb Zc Zc Verr_out Bx = – ------------------------ = – -------Vsense Rb In the case of no external RC network is used to compensate the error amplifier, the typical open loop transfer function of the error plus the sense amplifier is something with a gain around 80dB and a unity gain bandwidth at 400kHz. In this case the situation of the total transfer function Aloop, given by the sum of the AxdB and BxdB is : Figure 8. The BODE diagram shows together the error amplifier open loop transfer function, the Ax function and the resultant total Aloop given by the following equation : AloopdB = AxdB + BxdB The total Aloop has an high DC gain of 78.1dB with a bandwidth of 15KHz, but the problem in this case is the stability of the system; in fact the total Aloop cross the zero dB axis with a slope of -40dB/decade. Now it is necessary to compensate the error amplifier in order to obtain a total Aloop with an high DC gain and a large bandwidth. Aloop must have enough phase margin to guarantee the stability of the system. A method to reach the stability of the system, using the RC network showed in the block diagram, is to cancel the load pole with the zero given by the compensation of the error amplifier. 13/22 L6258EP The transfer function of the Bx block with the compensation on the error amplifier is : 1 Rc – j ------------------------Zc 2π ⋅ f ⋅ CcBx = – -------- = – ---------------------------------------Rb Rb In this case the Bx block has a DC gain equal to the open loop and equal to zero at a frequency given by the following formula: 1 Fzero = -----------------------------2π ⋅ Rc ⋅ Cc In order to cancel the pole of the load, the zero of the Bx block must be located at the same frequency of 163Hz; so now we have to find a compromise between the resistor and the capacitor of the compensation network. Considering that the resistor value defines the gain of the Bx block at the zero frequency, it is clear that this parameter will influence the total bandwidth of the system because, annulling the load pole with the error amplifier zero, the slope of the total transfer function is -20dB/decade. So the resistor value must be chosen in order to have an error amplifier gain enough to guarantee a desired total bandwidth . In our example we fix at 35dB the gain of the Bx block at zero frequency, so from the formula: Rc Bx_gain @ zero freq. = 20 ⋅ log -------Rb where: Rb = 20kΩ we have: Rc = 1.1MΩ Therefore we have the zero with a 163Hz the capacitor value : 1 1 Cc = ---------------------------------------- = ------------------------------------------------------ = 880pF –6 2π ⋅ Fzero ⋅ Rc 6.28 ⋅ 163 ⋅ 1.1 ⋅ 10 Now we have to analyse how the new Aloop transfer function with a compensation network on the error amplifier is. The following bode diagram shows : – the Ax function showing the position of the load pole – the open loop transfer function of the Bx block – the transfer function of the Bx with the RC compensation network on the error amplifier – the total Aloop transfer function that is the sum of the Ax function plus the transfer function of the compensated Bx block. Figure 9. 14/22 L6258EP We can see that the effect of the load pole is cancelled by the zero of the Bx block ; the total Aloop cross a the 0dB axis with a slope of -20dB/decade, having in this way a stable system with an high gain at low frequency and a bandwidth of around 8KHz. To increase the bandwidth of the system, we should increase the gain of the Bx block, keeping the zero in the same position. In this way the result is a shift of the total Aloop transfer function up to a greater value. 4.5 Effect of the Bemf of the stepper motor on the current control loop stability In order to evaluate what is the effect of the Bemf voltage of the stepper motor we have to look at the load block: Figure 10. OUT+ Bemf R L L L R S to Sense Amplifier OUT- The schematic now shows the equivalent circuit of the stepper motor including a sine wave voltage generator of the Bemf. The Bemf voltage of the motor is not constant, its value changes depending on the speed of the motor. Increasing the motor speed the Bemf voltage increases : Bemf = Kt · ω where: Kt is the motor constant ω is the motor speed in radiant per second The formula defining the gain of the load considering the Bemf of the stepper motor becomes: RS ( V S – Bemf ) ⋅ --------------------RL + RS Vsense ACload = ---------------------- = ----------------------------------------------------------Vout VS RS V S – Bemf Acload = ---------------------------- ⋅ --------------------VS RL + RS RS ⎞ ⎛ V S – Bemf ACload dB = 20 ⋅ log ⎜ ---------------------------- ⋅ ---------------------⎟ VS R L + R S⎠ ⎝ we can see that the Bemf influences only the gain of the load block and does not introduce any other additional pole or zero, so from the stability point of view the effect of the Bemf of the motor is not critical because the phase margin remains the same. Practically the only effect of the Bemf is to limit the gain of the total Aloop with a consequent variation of the bandwidth of the system. 15/22 L6258EP 5 APPLICATION INFORMATION A typical application circuit is shown in Fig. 11. Note: For avoid current spikes on falling edge of DISABLE a "DC feedback" would be added to the ERROR Amplifier. (R1-R2 on Fig. 11). 5.1 Interference Due to the fact that the circuit operates with switch mode current regulation, to reduce the effect of the wiring inductance a good capacitor (100nF) can be placed on the board near the package, between the power supply line (pin 13,31) and the power ground (pin 1,36,18,19) to absorb the small amount of inductive energy. It should be noted that this capacitor is usually required in addition to an electrolytic capacitor, that has poor performance at the high frequencies, always located near the package, between power supply voltage (pin 13,31) and power ground (pin 1,36,18,19), just to have a current recirculation path during the fast current decay or during the phase change. The range value of this capacitor is between few µF and 100µF, and it must be chosen depending on application parameters like the motor inductance and load current amplitude. A decoupling capacitor of 100nF is suggested also between the logic supply and ground. The EA_IN1 and EA_IN2 pins carry out high impedance lines and care must be taken to avoid coupled noise on this signals. The suggestion is to put the components connected to this pins close to the L6258EP, to surround them with ground tracks and to keep as far as possible fast switching outputs of the device. Remember also an 1 Mohm resistor between EA_INx and EA_OUTx to avoid output current spike during supply startup/shutdown. A non inductive resistor is the best way to implement the sensing. Whether this is not possible, some metal film resistor of the same value can be paralleled. The two inputs for the sensing of the winding motor current (SENSE_A & SENSE_B) should be connected directly on the sensing resistor Rs terminals, and the path lead between the Rs and the two sensing inputs should be as short as possible. Figure 11. Typical Application Circuit. VCP1 10nF VCP2 VBOOT 100nF VS VS TRI_CAP 0.33 21 10 20 11 I0_1 I1_1 I2_1 I3_1 PH2 I0_2 I1_2 I2_2 I3_2 DISABLE 14 13,31 35 34 L6258EP 5 PWSSO36 PACKAGE 9 2 4 3 1,36 18,19 32 33 17 8 15 27 16 23 28 22 EA_IN1 26 29 30 EA_OUT1 1M 820pF 25 EA_IN2 24 12mH 10Ω SENSE1 OUT1B OUT1A GND PWR_GND VDD VDD(5V) SIG_GND VREF VREF1 VREF2 EA_OUT2 1M 820pF D97IN626EP R1 1M 16/22 R2 1M STEPPER MOTOR OUT2A 0.33 7 6 SENSE2 M 12 1nF PH1 OUT2B L6258EP 5.2 Motor Selection Some stepper motor have such high core losses that they are not suitable for switch mode current regulation. Furthermore, some stepper motors are not designed for continuous operating at maximum current. Since the circuit can drive a constant current through the motor, its temperature might exceed, both at low and high speed operation. 5.3 Unused Inputs Unused inputs should be connected to the proper voltage levels in order to get the highest noise immunity. 5.4 Notes on PCB Design We recommend to observe the following layout rules to avoid application problems with ground and anomalous recirculation current. The by-pass capacitors for the power and logic supply must be kept as near as possible to the IC. It's important to separate on the PCB board the logic and power grounds and the internal charge pump circuit ground avoiding that ground traces of the logic signals cross the ground traces of the power signals. Because the IC uses the board as a heat sink, the dissipating copper area must be sized in accordance with the required value of Rthj-amb. 6 OPERATION MODE TIME DIAGRAMS Figure 12. Full step operation mode timing diagram (Phase - DAC input and Motor Current) Position 0 1 2 3 0 1 2 3 FULL Step Vector 0 5V Phase 1 Ph1 0 5V Phase 2 1 0 0 5V I0_1 0 Ph2 Ph2 5V I1_1 0 DAC 1 Inputs 2 5V 3 I2_1 0 Ph1 5V I3_1 0 I2 I1 I0 0 0 0 0 0 100 5V 0 0 0 1 98.4 0 0 1 0 95.2 0 0 1 1 92.1 0 1 0 0 88.9 0 1 0 1 82.5 0 1 1 0 77.8 0 1 1 1 71.4 1 0 0 0 63.5 1 0 0 1 55.6 1 0 1 0 47.6 1 0 1 1 38.1 1 1 0 0 28.6 1 1 0 1 19.1 1 1 1 0 9.5 1 1 1 1 No Current I0_2 DAC 2 Inputs I1_2 0 5V I2_2 0 I3_2 0 95.2% Motor drive Current 1 19.1% 0 95.2% Motor drive Current 2 Current level % of IMAX I3 5V 19.1% 0 D97IN629A 17/22 L6258EP Figure 13. Half step operation mode timing diagram (Phase - DAC input and Motor Current) 0 1 2 3 4 5 6 7 5V 0 5V 0 Phase 1 Phase 2 Half Step Vector Ph1 I0_1 DAC 1 Inputs I1_1 I2_1 I3_1 I0_2 DAC 2 Inputs I1_2 I2_2 I3_2 5V 0 5V 0 5V 0 5V 0 2 3 1 Ph2 4 5V 0 5V 0 5V 0 5V 0 0 5 7 6 Ph1 100% I3 I2 I1 I0 Current level% of IMAX 0 0 0 0 100 0 0 0 1 98.4 0 0 1 0 95.2 0 0 1 1 92.1 0 1 0 0 88.9 0 1 0 1 82.5 0 1 1 0 77.8 0 1 1 1 71.4 100% 1 0 0 0 63.5 71.4% 1 0 0 1 55.6 1 0 1 0 47.6 1 0 1 1 38.1 1 1 0 0 28.6 1 1 0 1 19.1 1 1 1 0 9.5 1 1 1 1 No Current 71.4% 0 Motor drive Current 1 -71.4% -100% Motor drive Current 2 0 -71.4% -100% 18/22 D97IN627C Ph2 L6258EP Figure 14. 4 bit microstep operation mode timing diagram (Phase - DAC input and Motor Current) Position 0 4 Micro Step Vector 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 5V Ph1 16 0 Phase 1 5V 24 8 0 Phase 5V 2 I0_1 0 Ph2 32 0 Ph2 5V I1_1 0 DAC 1 Inputs 40 5V 56 I2_1 48 0 Ph1 5V I3_1 0 5V I0_2 0 DAC 2 Inputs 5V I1_2 5V I2_2 0 I3_2 0 Motor drive Current 1 0 Motor drive 0 Current 2 100% 95.2% 82.5% 63.5% 47.6% 38.1% 19.1% 0% Current level% of IMAX I3 I2 I1 I0 0 0 0 0 100 0 0 0 1 98.4 0 0 1 0 95.2 0 0 1 1 92.1 0 1 0 0 88.9 0 1 0 1 82.5 0 1 1 0 77.8 0 1 1 1 71.4 1 0 0 0 63.5 1 0 0 1 55.6 1 0 1 0 47.6 1 0 1 1 38.1 1 1 0 0 28.6 1 1 0 1 19.1 1 1 1 0 9.5 1 1 1 1 No Current 0 D97IN628A 19/22 L6258EP Figure 15. PowerSSO36 Mechanical Data & Package Dimensions DIM. MIN. 2.15 2.15 0 0.18 0.23 10.10 A A2 a1 b c D (1) mm TYP. 7.4 E (1) e e3 F G G1 H h k L M N O Q S T U X Y MAX. 2.47 2.40 0.075 0.36 0.32 10.50 MIN. 0.084 0.084 0 0.007 0.009 0.398 7.6 0.291 0.5 8.5 2.3 inch TYP. MAX. 0.097 0.094 0.003 0.014 0.012 0.413 OUTLINE AND MECHANICAL DATA 0.299 0.019 0.335 0.090 0.10 0.06 10.50 0.40 10.10 0.004 0.002 0.413 0.016 0.398 5˚ 5˚ 0.55 0.90 0.022 4.3 0.035 0.169 10˚ 10˚ 1.2 0.8 2.9 3.65 1.0 0.047 0.031 0.114 0.144 0.039 4.1 6.5 4.7 7.3 0.161 0.256 PowerSSO-36 (slug-down) 0.185 0.287 A A2 (1) "D” and “E" do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0.15 mm per side(0.006”) hx45û Gauge plane 0.25 c G LEAD COPLANARITY A D M a1 stand-off Y k e T L H E X O F S Q U BOTTOM VIEW B 0.1 M A B b e3 7587131 A 20/22 L6258EP Table 8. Revision History Date Revision Description of Changes February 2005 1 First Issue in the EDOCS DMS. March 2005 2 Modified the note “(1)” of the Table 2. July 2005 3 Changed the maturity from Preliminary data to datasheet. Modified in Table 4 the Voffset parameter values. 21/22 L6258EP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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