STD110NH02L N-CHANNEL 24V - 0.0044 Ω - 80A DPAK STripFET™ III POWER MOSFET TYPE STD110NH02L ■ ■ ■ ■ ■ ■ ■ VDSS RDS(on) ID 24 V < 0.005 Ω 80 A(2) TYPICAL RDS(on) = 0.0044 Ω @ 10 V TYPICAL RDS(on) = 0.0056 Ω @ 5 V RDS(ON) * Qg INDUSTRY’s BENCHMARK CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED LOW THRESHOLD DEVICE SURFACE-MOUNTING DPAK (TO-252) POWER PACKAGE IN TAPE & REEL (SUFFIX “T4") 3 1 DPAK TO-252 (Suffix “T4”) DESCRIPTION The STD110NH02L utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology. This is suitable fot the most demanding DC-DC converter application where high efficiency is to be achieved. INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY DC/DC CONVERTES ABSOLUTE MAXIMUM RATINGS Symbol Vspike(1) VDS VDGR Value Unit Drain-source Voltage Rating Parameter 30 V Drain-source Voltage (VGS = 0) 24 V Drain-gate Voltage (RGS = 20 kΩ) 24 V ± 20 V Drain Current (continuous) at TC = 25°C 80 A Drain Current (continuous) at TC = 100°C 80 A Drain Current (pulsed) 320 A VGS Gate- source Voltage ID(2) ID(2) IDM(3) Ptot EAS (1) Tstg Tj Total Dissipation at TC = 25°C 125 W Derating Factor 0.83 W/°C Single Pulse Avalanche Energy 900 mJ -55 to 175 °C Storage Temperature Max. Operating Junction Temperature September 2003 1/11 STD110NH02L THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max 1.20 100 275 °C/W °C/W °C ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol Parameter Test Conditions Drain-source Breakdown Voltage ID = 25 mA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = 20 V VDS = 20V TC = 125°C IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20V V(BR)DSS Min. Typ. Max. 24 Unit V 1 10 µA µA ±100 nA Max. Unit ON (5) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS ID = 250 µA RDS(on) Static Drain-source On Resistance VGS = 10 V VGS = 5 V ID = 40 A ID = 20 A Min. Typ. 1 V 0.0044 0.0050 0.0050 0.0095 Ω Ω Typ. Max. Unit DYNAMIC Symbol Test Conditions gfs (5) Forward Transconductance VDS = 10 V Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 15V f = 1 MHz VGS = 0 Gate Input Resistance f = 1 MHz Gate DC Bias = 0 Test Signal Level = 20 mV Open Drain RG 2/11 Parameter ID = 40 A Min. 52 S 4450 1126 141 pF pF pF 1.6 Ω STD110NH02L ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time ID = 40 A VDD = 10 V RG = 4.7 Ω VGS = 10 V (Resistive Load, Figure 3) 14 224 Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD= 10 V ID= 80 A VGS= 10 V 69 13 9 Qoss (6) Output Charge VDS= 16 V VGS= 0 V 27 nC Qgls (7) Third-quadrant Gate Charge VDS< 0 V VGS= 10 V 64 nC ns ns 93 nC nC nC SWITCHING OFF Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions Min. ID = 40 A VDD = 10 V RG = 4.7Ω, VGS = 10 V (Resistive Load, Figure 3) Typ. Max. Unit 69 40 54 ns ns Typ. Max. Unit 80 320 A A 1.3 V SOURCE DRAIN DIODE Symbol Parameter ISD ISDM Source-drain Current Source-drain Current (pulsed) VSD (*) trr Qrr IRRM Test Conditions Forward On Voltage ISD = 40 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current di/dt = 100A/µs ISD = 80 A VDD = 15 V Tj = 150°C (see test circuit, Figure 5) Min. VGS = 0 47 58 2.5 (1) Garanted when external Rg=4.7 Ω and tf < tfmax. (2) Value limited by wire bonding (3) Pulse width limited by safe operating area. (4) Starting Tj = 25 oC, ID = 40A, VDD = 10V . (5) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (6) Q oss = Coss*∆ Vin , Coss = Cgd + Cds . See Appendix A (7) Gate charge for synchronous operation Safe Operating Area Thermal Impedance ns nC A 3/11 STD110NH02L Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/11 STD110NH02L Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized Breakdown Voltage vs Temperature . . 5/11 STD110NH02L Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/11 STD110NH02L TO-252 (DPAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.64 0.9 0.025 0.035 B2 5.2 5.4 0.204 0.212 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260 G 4.4 4.6 0.173 0.181 H 9.35 10.1 0.368 0.397 L2 0.8 L4 0.031 0.6 1 0.023 0.039 A1 C2 A H A2 C DETAIL "A" L2 D = 1 = G 2 = = = E = B2 3 B DETAIL "A" L4 0068772-B 7/11 STD110NH02L 8/11 STD110NH02L APPENDIX A Buck Converter: Power Losses Estimation SW1 SW2 The power losses associated with the FETs in a Synchronous Buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is er moved to allow for a safer working junction temperature. The low side (SW2) device requires: • • • • • Very low RDS(on) to reduce conduction losses Small Qgls to reduce the gate charge losses Small Coss to reduce losses due to output capacitance Small Qrr to reduce losses on SW1 during its turn-on The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source voltage to avoid the cross conduction phenomenon; The high side (SW1) device requires: • Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate • Small Qg to have a faster commutation and to reduce gate charge losses • Low RDS(on) to reduce the conduction losses. 9/11 STD110NH02L Pconduction Pswitching R DS(on)SW1 * I 2L * d R DS(on)SW2 * I 2L * (1 − d ) Vin * (Q gsth(SW1) + Q gd(SW1) ) * f * IL Ig Zero Voltage Switching Not Applicable Conduction Not Applicable Vf(SW2) * I L * t deadtime * f Pgate(Q G ) Q g(SW1) * Vgg * f Q gls(SW2) * Vgg * f PQoss Vin * Q oss(SW1) * f Vin * Q oss(SW2) * f 2 2 Parameter d Qgsth Qgls Pconduction Pswitching Pdiode Pgate PQoss 10/11 Low Side Switch (SW2) Recovery Pdiode 1 High Side Switch (SW1) 1 Meaning Duty-cycle Post threshold gate charge Third quadrant gate charge On state losses On-off transition losses Conduction and reverse recovery diode losses Gate drive losses Output capacitance losses Dissipated by SW1 during turn-on Vin * Q rr(SW2) * f STD110NH02L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 2003 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. 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