STD2NC50 STD2NC50-1 N-CHANNEL 500V - 3Ω - 2.2A DPAK/IPAK PowerMesh™II MOSFET TYPE STD2NC50 STD2NC50-1 ■ ■ ■ ■ ■ VDSS RDS(on) ID 500 V 500 V <4Ω <4Ω 2.2 A 2.2 A TYPICAL RDS(on) = 3 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED NEW HIGH VOLTAGE BENCHMARK GATE CHARGE MINIMIZED DESCRIPTION The PowerMESH™II is the evolution of the first generation of MESH OVERLAY™. The layout refinements introduced greatly improve the Ron*area figure of merit while keeping the device at the leading edge for what concerns swithing speed, gate charge and ruggedness. 3 3 1 2 1 IPAK DPAK INTERNAL SCHEMATIC DIAGRAM APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING ■ SWITH MODE POWER SUPPLIES (SMPS) ■ DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVER ■ ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Drain-source Voltage (VGS = 0) 500 V Drain-gate Voltage (RGS = 20 kΩ) 500 V Gate- source Voltage ±30 V ID Drain Current (continuos) at TC = 25°C 2.2 A ID Drain Current (continuos) at TC = 100°C 1.4 A Drain Current (pulsed) 8.8 A Total Dissipation at TC = 25°C 45 W 0.36 W/°C 3 V/ns –60 to 150 °C 150 °C VDS VDGR VGS IDM (1) PTOT Parameter Derating Factor dv/dt Peak Diode Recovery voltage slope Tstg Storage Temperature Tj Max. Operating Junction Temperature (•)Pulse width limited by safe operating area May 2001 (1)ISD ≤ 2.2A, di/dt ≤100A/µs, VDD ≤ V(BR)DSS, T j ≤ TJMAX 1/10 STD2NC50 / STD2NC50-1 THERMAL DATA Rthj-case Thermal Resistance Junction-case Max 2.78 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W Maximum Lead Temperature For Soldering Purpose 300 °C Tl AVALANCHE CHARACTERISTICS Symbol Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Parameter 2.2 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 140 mJ ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating IGSS Gate-body Leakage Current (VDS = 0) VGS = ±30V V(BR)DSS Min. Typ. Max. 500 Unit V VDS = Max Rating, TC = 125 °C 1 µA 50 µA ±100 nA ON (1) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 1.4 A Min. Typ. Max. Unit 2 3 4 V 3 4 Ω Typ. Max. Unit DYNAMIC Symbol gfs (1) 2/10 Parameter Forward Transconductance Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Test Conditions VDS > ID(on) x RDS(on)max, ID = 1.4A VDS = 25V, f = 1 MHz, VGS = 0 Min. 2 S 260 pF 45 pF 5 pF STD2NC50 / STD2NC50-1 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time VDD = 250V, ID = 1.4 A RG = 4.7Ω VGS = 10V (see test circuit, Figure 3) 10 10 Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 400V, ID = 2.8 A, VGS = 10V 10 2.5 4.5 13.5 nC nC nC Typ. Max. Unit ns ns SWITCHING OFF Symbol tr(Voff) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Conditions Min. VDD = 400V, ID = 2.8 A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 5) 10 8 20 ns ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (1) Parameter Test Conditions Min. Typ. Source-drain Current Source-drain Current (pulsed) Forward On Voltage ISD = 2.2 A, VGS = 0 trr Reverse Recovery Time Qrr Reverse Recovery Charge ISD = 2.8A, di/dt = 100A/µs, VDD = 100V, Tj = 150°C (see test circuit, Figure 5) IRRM Reverse Recovery Current Max. Unit 2.2 A 8.8 A 1.6 V 380 ns 2200 nC 11.5 A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area Thermal Impedence 3/10 STD2NC50 / STD2NC50-1 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/10 STD2NC50 / STD2NC50-1 Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/10 STD2NC50 / STD2NC50-1 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/10 STD2NC50 / STD2NC50-1 TO-252 (DPAK) MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 2.20 2.40 0.087 0.094 A1 0.90 1.10 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.64 0.90 0.025 0.035 B2 5.20 5.40 0.204 0.213 C 0.45 0.60 0.018 0.024 C2 0.48 0.60 0.019 0.024 D 6.00 6.20 0.236 0.244 E 6.40 6.60 0.252 0.260 G 4.40 4.60 0.173 0.181 H 9.35 10.10 0.368 0.398 L2 0.8 0.031 L4 0.60 1.00 0.024 0.039 V2 0o 8o 0o 0o P032P_B 7/10 STD2NC50 / STD2NC50-1 TO-251 (IPAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. 2.4 0.086 MAX. 0.094 0.043 A 2.2 A1 0.9 1.1 0.035 A3 0.7 1.3 0.027 0.051 B 0.64 0.9 0.025 0.031 B2 5.2 5.4 0.204 0.212 B3 0.85 B5 0.033 0.3 0.012 B6 0.95 0.037 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260 G 4.4 4.6 0.173 0.181 H 15.9 16.3 0.626 0.641 L 9 9.4 0.354 0.370 L1 0.8 1.2 0.031 L2 0.8 0.047 1 0.031 0.039 A1 C2 A3 A C H B B3 = 1 = 2 G = = = E B2 = 3 B5 L D B6 L2 L1 0068771-E 8/10 STD2NC50 / STD2NC50-1 DPAK FOOTPRINT TUBE SHIPMENT (no suffix)* All dimensions are in millimeters All dimensions are in millimeters TAPE AND REEL SHIPMENT (suffix ”T4”)* REEL MECHANICAL DATA DIM. mm MIN. A DIM. mm inch MIN. MAX. A0 6.8 7 0.267 0.275 B0 10.4 10.6 0.409 0.417 12.1 0.476 B1 MAX. D 1.5 D1 1.5 E 1.65 1.85 0.065 0.073 F 7.4 7.6 0.291 0.299 0.059 0.063 0.059 K0 2.55 2.75 0.100 0.108 P0 3.9 4.1 0.153 0.161 P1 7.9 8.1 0.311 0.319 P2 1.9 2.1 0.075 0.082 16.3 1.574 0.618 R 40 W 15.7 * on sales type 9/10 1.6 MIN. 0.641 inch MIN. 330 B 1.5 C 12.8 D 20.2 G 16.4 N 50 T TAPE MECHANICAL DATA MAX. MAX. 12.992 0.059 13.2 0.504 0.520 0.795 18.4 0.645 0.724 1.968 22.4 0.881 BASE QTY BULK QTY 2500 2500 STD2NC50 / STD2NC50-1 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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