STS3DPF60L DUAL P-CHANNEL 60V - 0.10 Ω - 3A SO-8 STripFET™ MOSFET Table 1: General Features TYPE VDSS RDS(on) ID 60 V < 0.12 Ω 3A STS3DPF60L ■ ■ ■ Figure 1: Package TYPICAL RDS(on) = 0.10 Ω @ 10V STANDARD OUTLINE FOR EASY AUTOMATED SURFACE MOUNT ASSEMBLYY LOW THRESHOLD DRIVE DESCRIPTION This MOSFET is the latest development of STMicroelectronis unique "Single Feature Size™" stripbased process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. SO-8 Figure 2: Internal Schematic Diagram APPLICATIONS ■ DC-DC CONVERTERS Table 2: Order Codes PART NUMBER MARKING PACKAGE PACKAGING STS3DPF60L S3DPF60L SO-8 TAPE & REEL Rev. 1 September 2004 1/9 STS3DPF60L Table 3: Absolute Maximum ratings Symbol VDS VDGR VGS ID IDM(•) Parameter Value Unit Drain-source Voltage (VGS = 0) 60 V Drain-gate Voltage (RGS = 20 kΩ) 60 V Gate- source Voltage ± 16 V Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C 3 1.9 A A Drain Current (pulsed) 12 A Ptot Total Dissipation at TC = 25°C 2 W Tstg Storage Temperature -55 to 150 °C 62.5 °C/W Tj Operating Junction Temperature (•) Pulse width limited by safe operating area. Table 4: Thermal Data Rthj-amb (*) (*)Thermal Resistance Junction-ambient When Mounted on 1 inch2 FR-4 board, 2 oz of Cu t ≤ 10 s ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 5: On/Off Symbol Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating ,TC= 125°C IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 16 V VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA RDS(on) Static Drain-source On Resistance VGS = 10 V, ID = 1.5 A VGS = 4.5 V, ID = 1.5 A V(BR)DSS 2/9 Parameter Min. Typ. Max. 60 Unit V 1 10 µA µA ±100 nA 0.12 0.160 Ω Ω 1.5 V 0.10 0.130 STS3DPF60L ELECTRICAL CHARACTERISTICS (CONTINUED) Table 6: Dynamic Symbol Parameter Test Conditions Min. Typ. Max. Unit Forward Transconductance VDS = 10 V, ID = 3 A 7.2 S Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25V f = 1 MHz VGS = 0 630 121 49 pF pF pF td(on) tr td(off) tf Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time VDD = 30 V , ID = 1.5 A RG = 4.7 Ω, VGS = 4.5 V (see Figure 16) 124 54 39 14.5 ns ns ns ns Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD= 48V, ID= 3A VGS=4.5V (see Figure 19) 11.6 4.5 4.7 15.7 nC nC nC Typ. Max. Unit 3 12 A A 1.2 V gfs (*) Table 7: Source Drain Diode Symbol Parameter ISD ISDM (•) Source-drain Current Source-drain Current (pulsed) VSD (*) Forward On Voltage ISD = 3 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 3 A, di/dt = 100A/µs VDD = 30 V, Tj = 150°C (see Figure 17) trr Qrr IRRM Test Conditions Min. 44 68.2 3.1 ns nC A (*) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (•)Pulse width limited by safe operating area. 3/9 STS3DPF60L Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics Figure 5: Transconductance Figure 8: Static Drain-source On Resistance 4/9 STS3DPF60L Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized On Resistance vs Temperature Figure 11: Dource-Drain Diode Forward Characteristics Figure 14: Normalized Breakdown Voltage vs Temperature 5/9 STS3DPF60L Figure 15: Unclamped Inductive Load Test Circuit Figure 18: Unclamped Inductive Wafeform Figure 16: Switching Times Test Circuit For Resistive Load Figure 19: Gate Charge Test Circuit Figure 17: Test Circuit For Inductive Load Switching and Diode Recovery Times 6/9 STS3DPF60L SO-8 MECHANICAL DATA DIM. mm. MIN. TYP A a1 MAX. MIN. TYP. 1.75 0.1 MAX. 0.068 0.25 a2 a3 inch 0.003 0.009 1.65 0.064 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 c1 45 (typ.) D 4.8 5.0 0.188 0.196 E 5.8 6.2 0.228 0.244 1.27 e e3 0.050 3.81 0.150 F 3.8 4.0 0.14 L 0.4 1.27 0.015 M S 0.6 0.157 0.050 0.023 8 (max.) 7/9 STS3DPF60L Table 8: Revision History 8/9 Date Revision 16-Sep-2004 1 Description of Changes New release. STS3DPF60L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 9/9