STMICROELECTRONICS STV5342

STV5342
TELETEXT DECODER WITH 4 INTEGRATED PAGES
COMPLETE TELETEXT DECODER INCLUDING ON-CHIP 4 PAGES MEMORY, REDUCING EMC RADIATIONS
UPWARD SOFTWARE AND HARDWARE
COMPATIBLE WITH PREVIOUS SGS-THOMSON’s DECODER SDA5243
AUTOMATIC SELECTION OF UP TO SIX NATIONAL LANGUAGES
4 SIMULTANEOUS PAGE REQUESTS
DISPLAY OF THE 25TH STATUS ROW
MICROPROCESSOR CONTROL VIA AN I2C
BUS (SLAVE ADDRESS 0010001 R/W)
DATA ACQUISITION AVAILABLE FROM
LINES 2 TO 22 OR FROM A COMPLETE
FIELD
HIGH QUALITY DISPLAY USING A CHARACTER MATRIX OF 12 x 10 DOTS
SINGLE + 5V SUPPLY VOLTAGE
ON-CHIP MASK PROGRAMMABLE ROM
CHARACTER GENERATORS
HCMOS PROCESS
DIP40
(Plastic Package)
ORDER CODE : STV5342
PIN CONNECTIONS
VDD
1
40
2
39
3
38
4
37
5
36
TTD
6
35
TTC
7
34
ODD/EVEN
8
33
F6
9
32
VCS
10
31
SAND
11
30
TCS/SCS
12
29
R
13
28
G
14
27
RESERVED
DESCRIPTION
The STV5342 is a HCMOS integrated circuit which
performs all the processing of logical data within a
625 lines system teletext decoder. It is designed to
operate in conjunction with one-chip : the SAA5231
integrated chip which extracts Teletext information
embedded in a composite video signal. Up to 4
pages of display data can be stored in internal
memory. A complete system also comprises a microprocessor controlling the STV5342 via a 2-wires
serial bus. An on-chip ROM memory contains the
character sets. The STV5342 performs automatic
selection of one of up to six natural languages. Data
bytes may be decoded in either 7-Bit plus parity or
in full 8-Bit formats. The chip set also supports
facilities for reception and display of higher-level
protocol data.
April 1994
B
15
26
COR
16
25
BL AN
17
24
Y
18
23
SCL
19
22
SDA
20
21
RESERVED
5342-01.EPS
.
.
.
..
.
.
.
..
.
V SS
1/20
STV5342
PIN DESCRIPTION
Pin
Symbol
Function
+5V
Description
Positive supply voltage
1
VDD
2 to 5
22 to 40
RESERVED
6
TTD
Teletext data input
An A.C. coupled teletext data input supplied by the
SAA5231 chip is latched to VSS between 4 and 8µs
after each TV line.
7
TTC
Teletext clock input
A 6.9375MHz clock signal, supplied by the SAA5231
chip, is internally A.C. coupled, clamped and
buffered.
8
ODD/EVEN
Interlaced mode state output
High for even numbered and low for odd numbered
frames. The value is valid 2µs before the end of
lines 311 and 624.
9
F6
Character display clock signal
The 6MHz clock signal, supplied by the SAA5231
chip is internally A.C. coupled, clamped and buffered.
10
VCS
Video composite
synchronization input signal
11
SAND
Sandcastle
Three level output pulse to the SAA5231 device.
Phase lock, blanking signal, and color burst
components are contained in this signal.
12
TCS/SCS
Input / output composite
synchronization signal
Scan composite input signal (SCS) for the display
synchronization or Text composite sync. (TCS)
output signal to the SAA5231. Both signals are
active low.
13,14,15
RGB
Red, green, blue
16
COR
Contrast reduction
17
BLAN
Blanking signal output
18
Y
Foreground output
2/20
Not used
SCL
Serial clock
20
SDA
Serial data input / output
21
VSS
0 Volt
Character and background colors active-high
open-drain outputs.
Open-drain active-low output supporting optimal
display of characters in ”mixed mode” operation.
Open-drain active high output for TV-image blanking
in normal and mixed-mode operation.
Open-drain active-high output with foreground
information. Can be used for printer command.
Microprocessor clock input via serial bus.
Open-drain microprocessor serial data input/output
via serial bus.
Ground
5342-01.TBL
19
Active high VCS input.
STV5342
BLOCK DIAGRAM
TCS/
VCS
SAND
SCS
10
11
12
Pins 22 to 40 and
Pins 2 to 5 not used
DATA
6
DATA
4 PAGES
INTERNAL
MEMORY
SCL 19
13 RED
DISPLAY &
CONTROL
INTERFACE
I 2 C BUS
INTERFACE
SDA 20
1
21
VD D
V SS
18
Y
17
BLAN
16
14 GREEN
15 BLUE
8
5342-02.EPS
TTD
DATA ACQUISITION
&
DATA PROCESSING
CTRL
7
CTRL
TTC
ADDRESS
TIME BASE
DATA
9
ADDRESS
EXTERNAL
MEMORY
INTERFACE
CLOC K
F6
COR ODD/
EVEN
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
Parameter
Power Supply Range
Value
Unit
-0.3, +6.0
V
INPUT VOLTAGE RANGE :
VI
VCS,SDA,SCL,D0-D7
-0.3, VDD + 0.5
V
VI
TTD,F6,TCS/SCS,TT C
-0.3, +10
V
V
VO
SAND,SDA,ODD/EVEN,R,G,B
-0.3 , VDD
VO
BLAN,COR, Y, TCS/SCS
-0.3 , VDD
V
-20, +125
o
-20, +70
o
Tstg
TA
Storage Temperature Range
Operating Ambient Temperature Range
C
C
5342-02.TBL
OUTPUT VOLTAGE RANGE :
Symbol
Parameter
VDD
Supply Voltage (Pin 1)
IDD
Supply Current (operating mode)
Min
4.5
Typ
Max
Unit
5
5.5
V
15
40
mA
3/20
5342-03.TBL
ELECTRICAL CHARACTERISTICS
VDD = 5V, VSS = 0V, TA = - 20 to + 70oC
STV5342
ELECTRICAL CHARACTERISTICS (continued)
VDD = 5V, VSS = 0V, TA = - 20 to + 70oC
Symbol
Parameter
Min
Typ
Max
Unit
INPUTS
TTD (Pin 6)
CEXT
Ext. Coupling Capacitor
50
nF
VI(p-p)
Input Voltage p-p
2
7
V
tr , tf
Input Rise / Fall Times
10
80
ns
tDS
Input Set-up Time
40
ns
tDH
Input Hold Time
40
ns
II(L)
Input Leakage Current (VI = 0 to VDD)
-10
CI
Input capacitance
+10
µA
7
pF
TTC, F6 (Pins 7,9)
DC Input Voltage
- 0.3
+10
V
VI(p-p)
AC Input Voltage F6
AC Input Voltage TTC
1
1.5
7
7
V
V
± VP
Input Peak Rel. 50 % Duty
0.2
3.5
V
fTTC
TTC Clock Frequency
fF6
F6 Clock Frequency
tr , tf
Clock Rise / Fall Times
10
80
II(L)
Input Leakage Current (VI = 0 to 10V)
-10
+10
µA
CI
Input Capacitance
10
pF
VI
6.9375
MHz
6
MHz
ns
VCS (Pin 10)
VIL
Low Level Input Voltage
0
0.8
V
VIH
High Level Input Voltage
2
VDD
V
tr , tf
Input Rise / Fall Times
500
ns
II(L)
Input Leakage Current (VI = 0 to VDD)
-10
+10
µA
CI
Input Capacitance
7
pF
V
SCL (Pin 19)
VIL
Low Level Input Voltage
0
1.5
3
VIH
High Level Input Voltage
VDD
V
fSCL
SCL Clock Frequency
100
kHz
tr , tf
Input Rise / Fall Times
2
µs
II(L)
Input Leakage Current (VI = 0 to VDD)
CI
Input Capacitance
-10
+10
µA
7
pF
V
INPUT/OUTPUTS
Low Level Input Voltage
0
1.5
VIH
High Level Input Voltage
3
8
V
tr , tf
Input Rise / Fall Times
500
ns
II(L)
Input Leakage Current
(VI = 0 to VDD and output in high impedance state)
-10
+10
µA
CI
Input Capacitance
7
pF
0
0.4
V
2.4
VOL
Low Level Output Voltage (IOL = 0.4mA)
VOH
High Level Output Voltage (-IOH = 0.2mA)
VDD
V
tr , tf
Output Rise / Fall Times between 0.6V and 2.2V
100
ns
Load Capacitance
50
pF
CL
4/20
5342-04.TBL
TCS(output), SCS(input) (Pin12)
VIL
STV5342
ELECTRICAL CHARACTERISTICS (continued)
VDD = 5V, VSS = 0V, TA = - 20 to + 70oC
Symbol
Parameter
Min
Typ
Max
Unit
V
INPUT/OUTPUTS (continued)
SDA (Pin 20)
VIL
Low Level Input Voltage
0
1.5
3
VDD
V
2
µs
+10
µA
7
pF
VIH
High Level Input Voltage
tr , tf
Input Rise / Fall Times
II(L)
Input Leakage Current (VI = 0 to VDD and output in high impedance state)
CI
Input Capacitance
VOL
tf
CL
Low Level Output Voltage (IOL = 3mA)
-10
0.5
V
Output Fall Time between 3.0V and 1.0V
0
200
ns
Load Capacitance
400
pF
D0-D7 (Pins 22-29)
VIL
Low Level Input Voltage
0
0.8
V
VIH
High Level Input Voltage
2
VDD
V
II(L)
Input Leakage Current (VI = 0 to VDD and output in high impedance state)
-10
+10
µA
CI
Input Capacitance
7
pF
0
0.4
V
2.4
VDD
V
VOL
Low Level Output Voltage (IOL = 1.6mA)
VOH
High Level Output Voltage (-I OH = 0.2mA)
tr , tf
Output Rise / Fall Times between 0.6V and 2.2V
50
ns
CL
Load Capacitance
120
pF
0
0.4
V
2.4
VDD
V
OUTPUTS
ODD/EVEN ••(Pin 8)
VOL
Low Level Output Voltage (IOL = 0.4mA)
VOH
High Level Output Voltage (-I OH = 0.2mA)
tr , tf
Output Rise / Fall Times between 0.6V and 2.2V
100
ns
Load Capacitance
50
pF
CL
SAND (Pin 11)
VOL
Low Level Output Voltage (IOL = 0.2mA)
VOI
Middle Level Output Voltage (IOL = ± 10 µA)
VOH
High Level Output Voltage (-IOH = 0 to 10µA)
0
-
0.25
V
1.1
-
2.9
V
4
VDD
V
tr1
tr2
Output Rise Time :
VOL to VOI from 0.4 to 1.1V
VOI to VOH from 2.9 to 4.0V
-
-
400
200
tf
Output Fall Time V OH to VOl from 4.0 to 0.4V
-
-
50
ns
Load Capacitance
-
-
30
pF
Low Level Output Voltage :
IOL = 2mA
IOL = 5mA
0
0
-
0.4
1
Pull-up Voltage (with R = 1kΩ to VDD)
-
-
VDD
V
Output Fall Time from 4.5 to 1.5V (with R = 1kΩ to VDD)
-
-
20
ns
tSK
Skew Delay on Falling Edges (at 3V with R = 1kΩ connected to VDD)
-
-
20
ns
CL
Load Capacitance
-
-
25
pF
ILO
Output Leakage Current (VPU = 0 to VDD output off)
-
-
20
µA
CL
ns
R, G, B, COR, BLAN, Y (Pins 13-18)
VPU
tf
V
5/20
5342-05.TBL
VOL
STV5342
ELECTRICAL CHARACTERISTICS (continued)
VDD = 5V, VSS = 0V, TA = - 20 to + 70oC
Symbol
Parameter
Min
Typ
Max
Unit
TIMING
Low Period Clock
4
-
-
µs
tHIGH
High Period Clock
4
-
-
µs
tSU , DAT
Data Set-up Time
250
-
-
ns
170
-
-
ns
4
-
-
µs
tHD , DAT
Data Hold Time
tSU , sTO
Stop Set-up Time from Clock High
tBUF
Start Set-up Time Following a Stop
4
-
-
µs
tHD , STA
Start Hold Time
4
-
-
µs
tSU , STA
Start Set-up Time Following Clock Low to High Transition
4
-
-
µs
5342-06.TBL
SERIAL BUS (referred to VIH = 3V, VIL = 1.5V) (see Fig. 6)
tLOW
Figure 1 : F6, TTC, TTD Input Internal Connections
F6
character display clock input
to timing chain
9
50%
duty cycle
level
V
TTC
teletext clock input
to data acquistion circuit
7
VP
VI(p-p)
VP
teletext data input
to data acquisition circuit
C EXT
0
clamping pulses from timing circuit
from time 4µs to 8µs of each television
line to maintain correct D.C. level
following external A.C. coupling
t
shaded regions equal in area
F6, TTC, TTD INPUT CIRCUITRY
INPUT WAVEFORM PARAMETERS
5342-03.EPS
6
TTD
Figure 2 : Teletext Data Input Timing
t CY
90%
TTC
10%
10%
tr
tf
40ns min. 40ns min.
80ns max.
80ns max.
Data Stable
Data Stable
t DS
TTD
data may change
Data Stable : 1 if ≥ 2V , 0 if ≤ 0.8V
6/20
90%
t DH
data may change
data may change
5342-04.EPS
144ns typ.
STV5342
Figure 3 : Synchronization Timing
F1
continuous internal 1MHz clock
0
64
TCS
Phase lock
4.67
SAND
1.5
8.5
5342-05.EPS
Phase lock off
33.5
All timings in µs
Figure 4 : Composite Sync. Waveforms
LSP
0
4.66
64
EP
0 2.33
32 34.33
64
BP
0
27.33 32
59.33 64
All timings in µs
TCS
(interlaced)
621
(308)
622
(309)
623
(310)
624
(311)
625
(312)
1
309
310
311
312
313
314
(1)
308
309
311
312
1
2
3
4
5
6
316
(3)
317
(4)
318
(5)
319
(6)
3
4
5
6
TCS
(interlaced)
315
(2)
TCS
(non-interlaced)
310
2
5342-06.EPS
The number positions indicate the end of lines.
The Teletext composite synchronization signal (TCS), whether interlacing is present or not, comprise
three components.
a) the line-synchronization pulses (LSP).
b) the equalization pulses (EP)
c) the frame-synchronization pulses (BP).
The timing reference is specified by the descending edge of the signal LSP, with a tolerance spread of ± 100ns.
7/20
STV5342
Figure 5 : Display Output Timing
A) LINE RATE
LSP (TCS)
0
4.66
64
40µs
R.G.B.Y (1)
display period
0
16.67
B) FIELD RATE
56.67
All timings in µs
lines 42 to 291 inclusive
(and 355 to 604 inclusive interlaced)
display period
0
41
291 312
Line numbers
(1) Also BLAN in charac ter and box bla nking
Horizontal directio n(line ) - Vertical direc tion (frame)
5342-07.EPS
R.G.B.Y (1)
Figure 6 : Serial Bus Timing
SDA
t BUF
t LOW
tf
SCL
t HD,STA
tr
t HD,DAT
t HIGH
t SU,DAT
t SU,STA
VIH = 3V , VIL = 1.5V
8/20
t SU,STO
5342-08.EPS
SDA
5342-09.EPS
VS or
Pin 28
Voltage
Sensor
70µA
Phase
Detector
6MHz
Oscillator
28
25
22
17
SAA5231
DATA SLICER
Sync. Output
1.2kΩ
1
Sync.
Separator
Switch in this position
TCS ON
Teletext
Data
and
Clock
Separator
27
CVBS
F6
9
VCS
12
10
TCS/SCS
Scan
Composite
Sync.
Sync.
Video
Composite
15.625kHz
11
SAND
6MHz
TCS
ENABLE
TCS
Outputs
Buffer
Vertical
Sync.
Integrator
Signal
Quality
Detector
6
I 2 C-Register 1
TCS ON Mode
(D2 = 1) (D1/D0)
Composite
Sync.
Generator
64
VIDEOTEXT CONTROLLER
STV5342
DISPLAY
FIELD SYNC.
ENABLE
ACQUISITION
SYSTEM
CLOCK
ACQUISITION
FIELD SYNC.
LINE
SYNC
STV5342
Figure 7 : Master Synchronization Mode
9/20
10/20
5342-10.EPS
Videotext
Data
and
Clock
Separator
27
CVBS
18
Phase
Detector
6MHz
Oscillator
20
28
25
22
17
SAA5231
DATA SLICER
Not connected for
External synchronization
1
Determines F6 and line sync.
Sync.
Separator
C
L
F6
9
SCS
TCS
Composite
Sync.
Generator
64
I 2 C-Register 1
DISABLE TCS OFF EXT-SYNC
(D2=0)
(D1=D0=1)
TCS
Outputs
Buffer
Sync.
Integrator
Signal
Quality
Detector
6
SCS
Field
Sync.
I2 C - Register 1, Bit D2=0 to disable TCS output buffer
and D1=D0=1 to enable external sync.
Acquisition only works when external sync. signal is
phase synchronous with CBVS input.
12
TCS/SCS
Scan
Composite
Sync.
Video
Composite
Sync.
10
VCS
15.625kHz
11
SAND
6MHz
VIDEOTEXT CONTROLLER
STV5342
DISPLAY
FIELD SYNC.
ENABLE
ACQUISITION
INTERNAL
CLOCK
FIELD
SYNC.
LINE
SYNC.
STV5342
Figure 8 : Slave Synchronization Mode
5342-11.EPS
SDA
SCL
TS
+12V
22µH
+5V
22µ H
10kΩ
16
15µH
0.1µ F
470Ω
21
1
20
19
10kΩ
+12V 10nF
23nF
470Ω
BC558B
4.7µ F
23
6 12 11 9
7 10
2
21
18
19
3
4
SAA5231
7
5
13.875MHz
7 - 36
11
15pF
390Ω
6
10
8
470Ω
820Ω
9
1
+12V
24
10µ F
10Ω
STV5342
8 16 18
7
5
26 13
15
14
13
17
27
TEA2014A
8
47µF
47nF 47nF 15pF 1nF 470pF 22nF 270pF 100pF 220pF 68nF
6MHz
560pF
1kΩ
20
10pF
68kΩ
15 28 22 17 14 25
12
27pF
10kΩ
1
2
3
1kΩ
10µ F
1kΩ
1N4148
3.7kΩ
2.2µF
6
1kΩ
1k Ω
22µ F
BC548B
BC548B
BC548B
GND
3
1.2kΩ
6.8kΩ
L7805
2 V0
100Ω
150pF
BC548B
2.7kΩ
+5V
1kΩ
4.7kΩ
82Ω
82Ω
82Ω
82Ω
V1 1
+12V
GND
B
G
R
BLK
GND
+12V
VIDEO
SYNC
STV5342
APPLICATION DIAGRAM
11/20
STV5342
APPLICATION NOTES
ORGANIZATION OF A PAGE-MEMORY
The organization of a page-memory is shown in
Figure 9. The STV5342 chip provides a display
format of 25 rows of 40 characters per row.
Row number twenty-four is used by the microprocessor for the display of information.
Row zero contains the page header.
The organization is as follows :
The first seven characters (0 - 6) are used for
messages regarding the operational status.
The eighth character is an alphanumeric control
character either ”white” or ”green” defining the
”search” status of the page. When it is ”white” the
operational state is normal and the header appears
white ; when it is ”green” the operational state
corresponds to ”search mode” and the header
appears green. The following twenty-four characters give the header of the requested page when
the system is in search mode. The last eight characters display the time of day.
Row twenty-five comprises ten bytes of control
data concerning the received page (see Table 1)
and fourteen free bytes which can be used by the
microprocessor.
PAGE MEMORY ORGANIZATION
Figure 9
7 Status
Characters
Fixed characters
Alphanumerics white
for normal,
green on searc h
7
24 characters from page header
rolling on page search
1
8 scrolling
time characters
ROW
8
0
24
1
2
3
4
5
6
7
8
9
10
11
MAIN PAGE DISPLAY AREA
12
13
14
15
16
17
18
19
20
21
22
23
12/20
10
14
10 bytes for received
page information
14 bytes free
for use by µC
24
25
5342-12.EPS
this row always free for status
STV5342
8/30 READING
8/30 packet is read at row 23 equivalent address.
R8 register must be programmed with D3, D2,
D0 = 0 and D2 = 1 (8/30 selection).
R9 register must be programmed with 23 (17h).
R10 register value corresponds to the position of
the byte to be read (from 0 to 39).
R11A contents the value of the needed byte.
D0
PU0
PT0
MU0
MT0
HU0
HT0
C7
C11
MAG0
0
D1
PU1
PT1
MU1
MT1
HU1
HT1
C8
C12
MAG1
0
D2
PU2
PT2
MU2
MT2
HU2
C5
C9
C13
MAG2
0
D3
PU3
PT3
MU3
C4
HU3
C6
C10
C14
0
0
D4
HAM
HAM
HAM
HAM
HAM
HAM
HAM
HAM
FOUND
0
D5
0
0
0
0
0
0
0
0
0
PBLF
D6
0
0
0
0
0
0
0
0
0
0
D7
0
0
0
0
0
0
0
0
0
0
COLUMN
0
1
2
3
4
5
6
7
8
9
Page number : - MAG = magazine, PU = page units, PT = page tens.
Page sub-code : - MU = minutes units, MT = minutes tens, HU = hours units, HT = hours tens.
PBLF = page being looked for, FOUND = low for page found, HAM = hamming error in byte, C4-14 = control bits.
5342-08.TBL
Table 1 : Row 25 received page control data format
REGISTER MAP (see Table 2)
follows : all bits in registers R0 to R11A are cleared
to zero with the exception of bits D0 and D1 in
registers R5 and R6 which are set to logical one.
After power-up all the memory bytes are preset to
hexadecimalvalue 20 H (space) with the exception
of the byte corresponding to row 0 of column 7 of
chapter 0 which is set to the value corresponding
to ”alpha white” hexadecimal value 07 H.
D7
D6
D5
D4
D3
D2
D1
D0
*
*
*
*
*
EVEN
OFF
TC
SEL11B
TA
7 + P/
8 BIT
ACQ.
ON/OFF
8/30
ENABLE
DEW/
FULL
FIELD
TCS
ON
T1
T0
*
ACQ
CCT
A1
ACQ.
CCT
A0
TB
START
COLUMN
SC2
START
START
COLUMN COLUMN
SC0
SC1
*
↵
↵
↵
R0
Mode 0
R1
Mode 1
R2
Page request adress
R3
Page request data
R4
Display chapter
R5
Display control (normal)
R6
Display control
(newsflash / subtitle)
R7
Display mode
R8
Active chapter
R9
Active row
R10
Active column
*
*
*
PRD4
PRD3
PRD2
PRD1
PRD0
*
*
*
*
*
*
A1
A0
BKGND
OUT
BKGND
IN
COR
OUT
COR
IN
TEXT
OUT
TEXT
IN
PON
OUT
PON
IN
BKGND
OUT
BKGND
IN
COR
OUT
COR
IN
TEXT
OUT
TEXT
IN
PON
OUT
PON
IN
STATUS
ROW
BTM/TOP
CURSOR
ON
CONCEAL/
REVEAL
TOP/
BOTTOM
SINGLE/
DOUBLE
HEIGHT
BOX ON
24
BOX ON
1-23
BOX ON
0
*
*
*
*
CLEAR
MEM.
8/30
SELECT
A1
A0
*
*
*
R4
R3
R2
R1
R0
*
*
C5
C4
C3
C2
C1
C0
D7
(R/W)
D6
(R/W)
D5
(R/W)
D4
(R/W)
D3
(R/W)
D2
(R/W)
D1
(R/W)
D0
(R/W)
R11A
Active data
60Hz
0
0
0
0
0
0
VCS
signal
quality
R11B
Status
↵
↵
↵
↵
↵
5342-09.TBL
Registers R0 to R10 are write only whilst R11A is a
read/write and R11B is a read only register respect
to the microprocessor.
The automatic succession on a byte basis is indicated by the arrows in Table 2.
In the normal operating mode TA, TB and TC
should be set to logic level 0.
After power-up the contents of the registers are as
Table 2 : Register specification
* Reserved register bits : must be set to 0
13/20
STV5342
REGISTER FUNCTIONS
Register
Function
R0
Address
00H
R11 adressing
and pin functions
control
Bit(s)
Description
SEL 11B (D0)
TC (D1)
EVEN OFF (D2)
T1
0
0
1
1
T0
0
1
0
1
TCS ON (D2)
R1
Address
01H
Operating mode
controls
Selection of register 11B (D0 = 1) or 11A (D0 = 0)
Test bit, must be cleared in the normal working mode
Control of ODD/EVEN pin : EVEN signal output (D2 = 0)
or grounded (D2 = 1)
312/313 line MIX - mode with interlace
312/313 line TEXT - mode without interlace
312/312 line Terminal mode without interlace
External synchronization TCS/SCS is an input
D2 = 1, TCS output on Pin TCS/SCS
D2 = 0, SCS input on Pin TCS/SCS
DEW / FULLFIELD
(D3)
Selection of field flyback mode or full channel mode
(D3 = 1)
8/30 ENABLE (D4)
Selection of 8/30 packet acquisition (D4 = 1)
ACQUISITION
ON / OFF (D5)
Control of acquisition operation (D5 = 0 enables
acquisition)
7 bits + parity or 8
Selection of received data format either 7 bits with parity
bits without parity (D6) (D6 = 0) or 8 bits without parity (D6 = 1).
R2
Address
02H
Addressing
information for
a page request
R3
Address
03H
Data relative to
the requested
page (see Table 3)
PRD0 - PRD4
(D0 - D4)
R4
Address
04H
Selection of one
of 4 pages to
display
A0 - D0
A1 - D1
R5
Address
05H
Display control for
normal operation
R6
Address
06H
Display control for
news-flash
subtitle generation
TB (D3)
Test bit, must be cleared in the normal working mode.
A0 - D4
A1 - D5
Selection of acquisition circuit (1 of 4)
R8
Address
08H
14/20
Active Chapter
Address
Selection of page to be displayed
PON (D0, D1)
Picture on (IN: D0, OUT: D1)
Text on (IN: D2, OUT: D3)
COR (D4, D5)
Contrast reduction on (IN: D4, OUT: D5)
BKGND (D6, D7)
Background colour on (IN: D6, OUT: D7)
See R5
BOX ON 0, 1-23,24
(D0, D1, D2)
Display mode
Written data in the page request RAM, starting with the
columns addressed by SC0,SC1,SC2.
TEXT (D2, D3)
IN / OUT
R7
Address
07H
Test bit, must be cleared in the normal working mode
Address the first column of the on chip page request RAM
to be written.
TOP/BOTTOM
Single/Double Height
(D4/D3)
Enable inside/outside the box
See R5
The ”boxing” function is enabled on row 0,1-23 and 24 by
D0, D1 and D2 set to one.
X0 = Normal
01 = double height Rows 0 to 11
11 = double height Rows 12 to 23
Conceal/Reveal (D5)
Conceal Reveal Function
Cursor ON/OFF (D6)
Cursor position given by row/column value of R9/R10
STATUS ROW
BTM / TOP (D7)
The 25th row is displayed before the ”Main text Area”
(lines 0-23) or after (D7 = 0).
A0 (D0)
A1 (D1)
8/30 SELECT(D2)
Selection of chapter to be READ/WRITE
To read 8/30 packet R8, D0 and D1 must be ”0” and
D2 = 1
5342-10.TBL
TA (D7)
SC0, SC1, SC2
(D0, D1, D2)
STV5342
REGISTER FUNCTIONS
R9 to R11A
Address
09H to 0BH*
R11B
Address
0BH*
Function
Bit(s)
Description
Active row address (R9), active column address (R10).
2
Data contained in R11A read (written) from (to) memory by microprocessor via I C.
Status
VCS Signal
Quality (D0)
60Hz (D7)
Good VCS quality signal detected (D0 = 1) or disturbed (D0 = 0)
5342-11.TBL
Register
VCS received with 60Hz frequency (D7 = 1) or 50Hz (D7 = 0).
Only valid when VCS is good (D0 = 1)
* Reading of R11A or R11B is determined by register 0, bit D0. Nevertheless, write operation is always performed on R11A register.
START
COLUMN
PRD4
PRD3
PRD2
PRD1
PRD0
0
Do care magazine
HOLD
MAG2
MAG1
MAG0
1
Do care page tens
PT3
PT2
PT1
PT0
2
Do care page units
PU3
PU2
PU1
PU0
3
Do care hours tens
X
X
HT1
HT0
4
Do care hours units
HU3
HU2
HU1
HU0
5
Do care minutes tens
X
MT2
MT1
MT0
6
Do care minutes units
MU3
MU2
MU1
MU0
5342-12.TBL
Table 3 : Register R3
The abbreviations have the same significance as in Table 1 with the exception of the ”DO CARE” entries. It is only
when this bit is ”1” that the corresponding digit is taken into consideration on page request. For example, a page
defined as ”normal” or one defined as ”timed” may be selected.
If ”HOLD” is low the page is held. The addressing of successive bytes via the I2C bus is automatic.
CHARACTER SETS
The complete character set with 8-bit decoding is
given in Table 4.
Characters in columns 0 and 1 are normally displayed as blanks. Black dots represent the character shape whereas white dots represent the
background.
Each character can be identified by a pair of corre-
sponding row and column integers : for example
the character ”3” may be indicated by 3/3.
A rectangle may be represented as follows :
The characters 8/6, 8/7, 9/5, 9/7 are used as special characters, always in conjunction with 8/5.
The 13 national characters are placed in columns
with bit 8 = 0.
15/20
*
**
16/20
Case using C12 C13 C14 = 001 (German Set)
These control characters are reserved for compatibility with other data codes.
These control characters are presumed before each row begins
5342-13.EPS
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
B
I
T
S
b4 b 3 b 2 b 1
b6
b5
b8
b7
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
cyan
cyan
SI
*
*
graphics
release
graphics
hold
height
SO
new
background
double
black
ESC
graphics
separated
graphics
continuous
display
background
**
**
**
conceal
white
1
normal
height
start box
end box
steady
flash
white
alphanumerics
graphics
graphics
alphanumerics
**
graphics
magenta
blue
blue
magenta
graphics
alphanumerics
alphanumerics
yellow
yellow
alphanumerics
green
red
graphics
red
graphics
graphics
alphanumerics
green
black
alphanumerics
graphics
0
black
0
0
alphanumerics
0
0
1
0
2
column
10
r
o
w
0
**
**
**
*
**
2
1
0 or 1
0
0
0
1
2a
0
0
3
1
0 or 1
0
0
0
1
3a
0
0
0
1
4
0
0
0
1
5
0
1
6
0
1
1
6a
0
7
0
1
1
7a
1
1
0
8
0
0
1
0
9
0
1
1
0
12
1
0
1
0
13
1
1
1
1
14
1
0
1
1
15
1
1
STV5342
Table 4 : Complete character set (with 8 bit codes) - West European Languages
STV5342
NATIONAL OPTION CHARACTER SETS
The basic set of the 96 characters is shown in
Table 5.The location of the 13 national characters
are shown in Table 5 whilst full national character
sets are depicted in Table 6.
Table 5 : Basic character set.
4/0
National
5/0
6/0
Character
National
Character
7/0
2/1
3/1
4/1
5/1
6/1
7/1
2/2
3/2
4/2
5/2
6/2
7/2
3/3
4/3
5/3
6/3
7/3
3/4
4/4
5/4
6/4
7/4
2/5
3/5
4/5
5/5
6/5
7/5
2/6
3/6
4/6
5/6
6/6
7/6
2/7
3/7
4/7
5/7
6/7
7/7
2/8
3/8
4/8
5/8
6/8
7/8
2/9
3/9
4/9
5/9
6/9
7/9
2/10
3/10
4/10
5/10
6/10
7/10
2/11
3/11
4/11
5/11
6/11
7/11
2/12
3/12
4/12
5/12
6/12
7/12
2/13
3/13
4/13
5/13
6/13
7/13
2/14
3/14
4/14
5/14
6/14
7/14
2/15
3/15
4/15
5/15
6/15
7/15
2/3
2/4
National
Character
National
Character
National
Character
National
Character
National
Character
National
Character
National
Character
National
Character
National
Character
National
Character
National
Character
5342-14.EPS
3/0
2/0
17/20
STV5342
18/20
Where PHCB are the Page Header Control bits. Other Combinations de fault to English. Only the above ch aracters change with the PHCB. All others
characters in the basic set are shown in Table 5.
5342-15.EPS
0
1
SPANISH
1
0
1
FRENCH
0
1
0
ITALIAN
1
1
0
SWEDISH
0
0
0
GERMAN
1
0
0
ENGLISH
0
C13
PHCB (1)
LANGUAGE
Note 1 :
C12
C14
2/3
2/4
4/0
5/11
5/12
5/13
5/14
5/15
CHARACTER POSITION (COLUMN/ROW)
6/0
7/11
7/12
7/13
7/14
Table 6 : Character Set for STV5342 West European Languages
STV5342
Figure 10 : Character Format
Contiguous
graphics character
7/6
Alphanumerics
character
2/13
Separated
graphics character
7/6
Alphanumerics or
blast-thro ugh
alphanumerics
character 4/8
Separated
graphics character
7/15
=
Background
Color
Alphanumerics
character
7/15
Contiguous
graphics character
7/15
=
5342-16.EPS
Alphanumerics and
Graphics ’space’
character
2/0
Display
Color
19/20
STV5342
I
L
a1
PACKAGE MECHANICAL DATA
40 PINS - PLASTIC DIP
b1
b
e
b2
E
e3
D
21
1
20
a1
b
b1
b2
D
E
e
e3
F
i
L
Min.
Millimeters
Typ.
0.63
0.45
0.23
Max.
Min.
0.31
0.009
1.27
Max.
0.012
0.050
52.58
16.68
15.2
Inches
Typ.
0.025
0.018
2.070
0.657
0.598
2.54
48.26
0.100
1.900
14.1
4.445
3.3
0.555
0.175
0.130
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility
for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result
from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.
Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life
support devices or systems without express written approval of SGS-THOMSON Microelectronics.
 1994 SGS-THOMSON Microelectronics - All Rights Reserved
Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips
I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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20/20
DIP40.TBL
Dimensions
PM-DIP40.EPS
F
40