TDA7438 THREE BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR INPUT MULTIPLEXER - 3 STEREO INPUTS - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES ONE STEREO OUTPUT TREBLE, MIDDLE AND BASS CONTROL IN 2.0dB STEPS VOLUME CONTROL IN 1.0dB STEPS TWO SPEAKER ATTENUATORS: - TWO INDEPENDENT SPEAKER CONTROL IN 1.0dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS DESCRIPTION The TDA7438 is a volume tone (bass, middle and treble) balance (Left/Right) processor for quality audio applications in car-radio and Hi-Fi systems. Selectable input gain is provided. Control of all the functions is accomplished by serial bus. SO28 DIP28 ORDERING NUMBER: TDA7438D (SO28) TDA7438 (DIP28) The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained. BLOCK DIAGRAM MUXOUTL L-IN1 3 6 INL TREBLE(L) 7 18 17 100K L-IN2 BOUT(L) MIN(L) MOUT(L) BIN(L) 16 14 RM 15 RB 4 100K L-IN3 5 G VOLUME TREBLE MIDDLE SPKR ATT LEFT BASS 27 LOUT 100K R-IN1 21 0/30dB 2dB STEP 2 I2CBUS DECODER + LATCHES 22 20 100K R-IN2 SDA DIG_GND 1 100K R-IN3 SCL G VOLUME TREBLE MIDDLE SPKR ATT RIGHT BASS 26 ROUT 28 V REF 100K 24 SUPPLY INPUT MULTIPLEXER + GAIN RM 8 MUXOUTR April 1999 9 INR 19 TREBLE(R) 10 RB 11 12 MIN(R) MOUT(R) BIN(R) 13 25 VS AGND 23 BOUT(R) CREF D96AU488A 1/17 TDA7438 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value 10.5 V Tamb Operating Ambient Temperature -10 to 85 °C Tstg Storage Temperature Range -55 to 150 °C VS Operating Supply Voltage Unit PIN CONNECTION R_IN2 1 28 R_IN3 R_IN1 2 27 LOUT L_IN1 3 26 ROUT L_IN2 4 25 AGND L_IN3 5 24 VS MUXOUTL 6 23 CREF INL 7 22 SDA MUXOUTR 8 21 SCL INR 9 20 DIG-GND MIN(R) 10 19 TREBLE(R) MOUT(R) 11 18 TREBLE(L) BIN(R) 12 17 MIN(L) BOUT(R) 13 16 MOUT(L) BIN(L) 14 15 BOUT(L) D96AU489A THERMAL DATA Symbol R th j-pin Parameter Thermal Resistance Junction-pins Value Unit 85 °C/W QUICK REFERENCE DATA Symbol Parameter Min. Typ. Max. 9 10.2 VS Supply Voltage 6 VCL Max. input signal handling 2 Total Harmonic Distortion V = 1Vrms f = 1KHz 0.01 S/N Signal to Noise Ratio V out = 1Vrms (mode = OFF) 106 SC Channel Separation f = 1KHz Volume Control Treble Control (1dB step) (2dB step) 0.1 % dB 90 dB 0 30 dB -47 0 dB -14 +14 dB -14 +14 dB Bass Control (2dB step) -14 +14 dB Balance Control -79 0 dB Middle Control (2dB step) 1dB step Mute Attenuation (*) 80 100 (*) Even applied to Speaker Attenuator Left, Speaker Attenuator Right, Volume Control stand alone or to the combination, if any. 2/17 V Vrms THD Input Gain in (2dB step) Unit dB TDA7438 ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL= 10KΩ, RG = 600Ω, all controls flat (G = 0dB), unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit 10.2 V SUPPLY VS Supply Voltage 6 9 IS SVR Supply Current Ripple Rejection 60 7 90 mA dB THD = 0.3% 2 100 2.5 KΩ Vrms The selected input is grounded through a 2.2µ capacitor 80 100 dB -1 0 INPUT STAGE RIN VCL Input Resistance Clipping Level SIN Input Separation Ginmin Minimum Input Gain Ginman Gstep Maximum Input Gain Step Resolution 1 30 2 dB dB dB VOLUME CONTROL Ri CRANGE AVMAX ASTEP EA ET Input Resistance Control Range Max. Attenuation Step Resolution Attenuation Set Error Tracking Error VDC DC Step Amute Mute Attenuation AV = 0 to -24dB AV = -24 to -47dB 20 45 45 33 47 47 50 49 49 KΩ dB dB 0.5 -1.0 -1.5 1 0 0 1.5 1.0 1.5 dB dB dB 1 2 3 80 0 0 0 0.5 100 dB dB mV mV dB AV = 0 to -24dB AV = -24 to -47dB adjacent attenuation steps from 0dB to AV max BASS CONTROL (The center frequency and the response quality can be chosen by the ext. circuitry) Gb BSTEP RB Control Range Max. Boost/cut Step Resolution Internal Feedback Resistance +12.0 +14.0 +16.0 dB 1 33 2 44 3 55 dB KΩ TREBLE CONTROL (The center frequency and the response quality can be chosen by the ext. circuitry) Gt TSTEP Control Range Max. Boost/cut Step Resolution +13.0 +14.0 +15.0 dB 1 2 3 dB MIDDLE CONTROL (The center frequency and the response quality can be chosen by the ext. circuitry) Gm MSTEP RM Control Range Step Resolution Internal Feedback Resistance Max. Boost/cut +12.0 1 18.75 +14.0 2 25 +16.0 3 31.25 dB dB KΩ SPEAKER ATTENUATORS CRANGE SSTEP EA ET Control Range Step Resolution Attenuation Set Error Tracking Error VDC DC Step Amute Mute Attenuation 76 AV = 0 to -20dB AV = -20 to -56dB 0.5 -1.5 -2 AV = 0 to -24dB AV = -24 to -47dB adjacent attenuation steps 80 dB 1 0 0 1.5 1.5 2 dB dB dB 0 0 0 1 2 3 dB dB mV 100 dB 3/17 TDA7438 ELECTRICAL CHARACTERISTICS (continued.) Symbol Parameter Test Condition Min. Typ. 2.1 2 10 2.6 Max. Unit AUDIO OUTPUTS VCLIP RL RO Clipping Level Output Load Resistance Output Impedance VDC DC Voltage Level d = 0.3% VRMS KΩ 40 70 Ω V 3.8 GENERAL (Gain, Bass, Treble, Middle Controls Flat) ENO Et Output Noise All gains = 0dB; BW = 20Hz to 20KHz flat 5 15 µV Total Tracking Error AV = 0 to -24dB AV = -24 to -47dB AV = -47 to -79dB 0 0 0 1 2 3 dB dB dB 0.08 dB dB % (Volume + Speaker Attenuator) S/N SC d All gains 0dB; VO = 1VRMS ; Signal to Noise Ratio Channel Separation Left/Right Distortion 90 80 106 100 0.01 AV = 0; V I = 1VRMS ; BUS INPUT V IL VIH IIN Input Low Voltage Input High Voltage Input Current 3 -5 VIN = 0.4V 1 V V 5 µA TEST CIRCUIT 2.7K 5.6nF 5.6K 18nF 22nF 100nF 100nF MUXOUTL L-IN1 3 0.47µF L-IN2 5 0.47µF 16 BIN(L) BOUT(L) 14 15 RM RB G VOLUME TREBLE MIDDLE SPKR ATT LEFT BASS 27 21 0/30dB 2dB STEP 2 2 I CBUS DECODER + LATCHES 22 20 100K SCL SDA DIGGND 1 100K G VOLUME TREBLE MIDDLE SPKR ATT RIGHT BASS 26 ROUT 28 VREF 100K 24 INPUT MULTIPLEXER + GAIN RM 9 INR 19 TREBLE(R) 2.2µF 5.6nF 10 MIN(R) MUXOUTR SUPPLY RB 25 VS AGND 8 4/17 LOUT 100K 0.47µF R-IN3 MOUT(L) 17 100K 0.47µF R-IN2 18 100K 0.47µF R-IN1 TREBLE(L) 7 4 0.47µF L-IN3 INL 6 MIN(L) 2.2µF 11 MOUT(R) 18nF 2.7K 12 13 BIN(R) BOUT(R) 22nF 100nF 5.6K 100nF 23 CREF 10µF D96AU490A TDA7438 APPLICATION SUGGESTIONS The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for the first one, 0 to -79dB (mute) for the last one. Both of them have 1dB step resolution. The very high resolution allows the implementation of systems free from any noisy acoustical effect. The TDA7438 audioprocessor provides 3 bands tones control. Bass, Middle Stages The Bass and the middle cells have the same structure. The Bass cell has an internal resistor Ri = 44KΩ typical. The Middle cell has an internal resistor Ri = 25KΩ typical. Several filter types can be implemented, connecting external components to the Bass/Middle IN and OUT pins. The fig.1 refers to basic T Type Bandpass Filter starting from the filter component values (R1 internal and R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed as follows: FC = AV = OUT C1 C2 R2 C2 + R2 C1 + Ri C1 R2 C1 + R2 C2 √ Ri R2 + C1 C2 R2 C1 + R2 C2 Viceversa, once Fc, Av, and Ri internal value are fixed, the external components values will be: C1 = AV − 1 2 ⋅ π ⋅ Ri ⋅ Q R2 = IN 2 ⋅ π ⋅√ Ri, R2, C1, C2 Q= Figure 1. Ri internal 1 C2 = Q2 ⋅ C1 AV − 1 Q2 AV − 1 − Q2 2 ⋅ π ⋅ C1 ⋅ FC ⋅ (AV − 1) ⋅Q Treble Stage The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25KΩ typical) and an external capacitor connected between treble pins and ground Typical responses are reported in Figg. 10 to 13. R2 D95AU313 Figure 2: THD vs. frequency CREF The suggested 10µF reference capacitor (CREF) value can be reduced to 4.7µF if the application requires faster power ON. Figure 3: THD vs. RLOAD 5/17 TDA7438 Figure 4: Channel separation vs. frequency Figure 5: Bass response Ri = 44kΩ C9 = C10 = 100nF (Bout, Bin) R3 = 5.6kΩ Figure 6: Middle response Ri = 25kΩ C9 = 15nF (MIN) C6 - 22nF (MOUT) R1 = 2.7kΩ Figure 8: Typical tone response 6/17 Figure 7: Treble response TDA7438 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7438 and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an ac- knowledge bit. The MSB is transferred first. Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor, the µP can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 3: Data Validity on the I2CBUS Figure 4: Timing Diagram of I2CBUS Figure 5: Acknowledge on the I2CBUS 7/17 TDA7438 address A subaddress bytes A sequence of data (N byte + acknowledge) A stop condition (P) SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7438 CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 1 0 0 0 MSB ACK X DATA 1 to DATA n LSB X X B DATA MSB ACK LSB DATA ACK P D96AU420 ACK = Acknowledge S = Start P = Stop A = Address B = Auto Increment EXAMPLES No Incremental Bus The TDA7438 receives a start condition, the cor- CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 1 0 rect chip address, a subaddress with the B = 0 (no incremental bus), N-data (all these data concern the subaddress selected), a stop condition. 0 0 MSB ACK X DATA LSB X X MSB 0 D3 D2 D1 D0 ACK LSB DATA ACK P D96AU421 Incremental Bus The TDA7438 receive a start conditions, the correct chip address, a subaddress with the B = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 D96AU422 8/17 1 0 SUBADDRESS from ”XXX1000” to ”XXX1111” of DATA are ignored. The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. 0 0 MSB ACK X DATA 1 to DATA n LSB X X 1 D3 D2 D1 D0 ACK MSB LSB DATA ACK P TDA7438 POWER ON RESET CONDITION INPUT SELECTION IN2 INPUT GAIN 28dB VOLUME MUTE BASS 0dB MIDDLE 2dB TREBLE 2dB SPEAKER MUTE DATA BYTES Address = 88 HEX (ADDR:OPEN). FUNCTION SELECTION: First byte (subaddress) MSB LSB SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 X X X B 0 0 0 0 INPUT SELECT X X X B 0 0 0 1 INPUT GAIN X X X B 0 0 1 0 VOLUME X X X B 0 0 1 1 BASS X X X B 0 1 0 0 MIDDLE X X X B 0 1 0 1 TREBLE X X X B 0 1 1 0 SPEAKER ATTENUATE ”R” X X X B 0 1 1 1 SPEAKER ATTENUATE ”L” B = 1: INCREMENTAL BUS ACTIVE B = 0: NO INCREMENTAL BUS X = DON’T CARE INPUT SELECTION MSB LSB INPUT MULTIPLEXER D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 0 IN3 X X X X X X 0 1 NOT ALLOWED X X X X X X 1 0 IN2 X X X X X X 1 1 IN1 9/17 TDA7438 DATA BYTES (continued) INPUT GAIN SELECTION MSB D7 D6 D5 D4 LSB INPUT GAIN D3 D2 D1 D0 2dB STEPS 0 0 0 0 0dB 0 0 0 1 2dB 0 0 1 0 4dB 0 0 1 1 6dB 0 1 0 0 8dB 0 1 0 1 10dB 0 1 1 0 12dB 0 1 1 1 14dB 1 0 0 0 16dB 1 0 0 1 18dB 1 0 1 0 20dB 1 0 1 1 22dB 1 1 0 0 24dB 1 1 0 1 26dB 1 1 1 0 28dB 1 1 1 1 30dB LSB VOLUME 1dB STEPS GAIN = 0 to 30dB VOLUME SELECTION MSB D7 D6 D4 D3 D2 D1 D0 0 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 -7dB 0 0 0 0 0dB 0 0 0 1 -8dB 0 0 1 0 -16dB 0 0 1 1 -24dB 0 1 0 0 -32dB 0 1 0 1 X 1 1 1 VOLUME = 0 to 47dB/MUTE 10/17 D5 -40dB X X X MUTE TDA7438 DATA BYTES (continued) BASS SELECTION MSB D7 D6 D5 D4 LSB BASS D3 D2 D1 D0 2dB STEPS 0 0 0 0 -14dB 0 0 0 1 -12dB 0 0 1 0 -10dB 0 0 1 1 -8dB 0 1 0 0 -6dB 0 1 0 1 -4dB 0 1 1 0 -2dB 0 1 1 1 0dB 1 1 1 1 0dB 1 1 1 0 2dB 1 1 0 1 4dB 1 1 0 0 6dB 1 0 1 1 8dB 1 0 1 0 10dB 1 0 0 1 12dB 1 0 0 0 14dB LSB MIDDLE MIDDLE SELECTION MSB D7 D6 D5 D4 D3 D2 D1 D0 2dB STEPS 0 0 0 0 -14dB 0 0 0 1 -12dB 0 0 1 0 -10dB 0 0 1 1 -8dB 0 1 0 0 -6dB 0 1 0 1 -4dB 0 1 1 0 -2dB 0 1 1 1 0dB 1 1 1 1 0dB 1 1 1 0 2dB 1 1 0 1 4dB 1 1 0 0 6dB 1 0 1 1 8dB 1 0 1 0 10dB 1 0 0 1 12dB 1 0 0 0 14dB 11/17 TDA7438 DATA BYTES (continued) TREBLE SELECTION MSB D7 D6 D5 D4 LSB TREBLE D3 D2 D1 D0 2dB STEPS 0 0 0 0 -14dB 0 0 0 1 -12dB 0 0 1 0 -10dB 0 0 1 1 -8dB 0 1 0 0 -6dB 0 1 0 1 -4dB 0 1 1 0 -2dB 0 1 1 1 0dB 1 1 1 1 0dB 1 1 1 0 2dB 1 1 0 1 4dB 1 1 0 0 6dB 1 0 1 1 8dB 1 0 1 0 10dB 1 0 0 1 12dB 1 0 0 0 14dB LSB SPEAKER ATTENUATION D3 D2 D1 D0 1dB 0 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 -7dB SPEAKER ATTENUATE SELECTION MSB D7 D6 D5 D4 0 0 0 0 0dB 0 0 0 1 -8dB 0 0 1 0 -16dB 0 0 1 1 -24dB 0 1 0 0 -32dB 0 1 0 1 -40dB 0 1 1 0 -48dB 0 1 1 1 -56dB 1 0 0 0 -64dB 1 0 0 1 1 1 1 1 SPEAKER ATTENUATION = 0 to -79dB/MUTE 12/17 -72dB X X X MUTE TDA7438 PINS: 23 PINS: 26,27 VS VS VS 20K 24 ROUT LOUT CREF 20µA 20K D96AU430 D96AU434 PINS: 1, 2, 3, 4, 5, 28 PINS: 6, 8 VS VS VS 20µA 20µA MUXOUT IN 100K GND VREF D96AU425 PINS: 7, 9 D96AU491 PINS: 10, 11 VS VS 20µA 20µA INL INR 33K 25K D96AU427 V REF MOUT(L) MOUT(R) D96AU431 13/17 TDA7438 PINS: 10, 17 PINS: 12,14 VS VS 20µA 20µA 25K 44K MIN(L) BIN(L) MIN(R) D96AU431 PINS: 13,15 BIN(R) D96AU428 PINS: 18, 19 VS VS 20µA 20µA TREBLE(L) TREBLE(R) 50K 44K BOUT(L) BOUT(R) D96AU433 D96AU429 PINS: 20 PINS: 21 20µA SCL 20µA SDA D96AU423 D96AU424 14/17 TDA7438 mm DIM. MIN. TYP. inch MAX. MIN. TYP. a1 0.63 0.025 b 0.45 0.018 b1 0.23 b2 0.31 D E 0.012 0.009 1.27 0.050 37.34 15.2 16.68 1.470 0.598 0.657 e 2.54 0.100 e3 33.02 1.300 F MAX. OUTLINE AND MECHANICAL DATA 14.1 0.555 I 4.445 0.175 L 3.3 0.130 DIP28 15/17 TDA7438 mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 2.65 MAX. 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 c1 0.020 45° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S 16/17 OUTLINE AND MECHANICAL DATA 8 ° (max.) SO28 TDA7438 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com 17/17