www.fairchildsemi.com AN-9750 High-Power Factor Flyback Converter for LED Driver with FL7732 PSR Controller Introduction This highly integrated PWM controller, FL7732, provides several features to enhance the performance of low-power flyback converters. The proprietary topology enables simplified circuit design for LED lighting applications. By using single-stage topology with primary-side regulation, a LED lighting board can be implemented with few external components and minimized cost, without requiring an input bulk capacitor and feedback circuitry. To implement high power factor and low THD, constant on-time control utilizes an external capacitor connected at the COMI pins. Precise constant-current control regulates accurate output current across changes in input voltage and output voltage. The operating frequency is proportionally changed by the output voltage to guarantee DCM operation with higher efficiency and simple design. FL7732 provides protection functions such as open-LED, short-LED and overtemperature protection. The current-limit level is automatically reduced to minimize the output current and protect external components in short-LED condition. This application note presents practical design consideration for an LED driver employing Fairchild Semiconductor PWM PSR controller FL7732. It includes designing the transformer, selecting the components, and implementing constant current regulation. The step-by-step design procedure helps engineers design a power supply. The design procedure is verified through an experimental prototype converter. Figure 1 shows the typical application circuit of primary-side controlled flyback converter using FL7732 created in the design example. Figure 1. Typical Application Circuit © 2011 Fairchild Semiconductor Corporation Rev. 1.0.3 • 5/15/12 www.fairchildsemi.com AN-9750 APPLICATION NOTE Basic Operation VIN.peak n:1 ID D - VD + Generally, Discontinuous Conduction Mode (DCM) operation is preferred for primary-side regulation because it allows better output regulation. The operation principles of DCM flyback converter are as follows: + Lm CO IM VOUT - IDS Q Mode I + VDS During the MOSFET turn-on time (tON), input voltage (VIN.pk) is applied across the primary-side inductor (Lm). Then, drain current (IDS) of the MOSFET increases linearly from zero to the peak value (Ipk), as shown in Figure 2. During this time, the energy is drawn from the input and stored in the inductor. - Figure 3. Mode I: Q[ON], D[OFF] Mode II When the MOSFET (Q) is turned off, the energy stored in the inductor forces the rectifier diode (D) to be turned on. VGate MODE II MODE I MODE III VDS nVOUT Figure 4. Mode II: Q[OFF], D[ON] VIN IM ID IDS IDS ID IO Figure 5. Mode III: Q[OFF], D[OFF] VA While the diode is conducting, output voltage (VOUT), together with diode forward-voltage drop (VF), is applied across the secondary-side inductor and diode current (ID) decreases linearly from the peak value (Ipk NP/NS) to zero. At the end of inductor current discharge time (tDIS), all energy stored in the inductor has been delivered to the output. NA VO NS tDIS tS Mode III Figure 2. Basic Function of DCM Mode Flyback When the diode current reaches zero, the transformer auxiliary winding voltage begins to oscillate by the resonance between the primary-side inductor (Lm) and the effective capacitor loaded across MOSFET (Q). © 2011 Fairchild Semiconductor Corporation Rev. 1.0.3 • 5/15/12 www.fairchildsemi.com 2 AN-9750 APPLICATION NOTE Constant Current Regulation OSC The output current (IO) can be estimated by using the peak drain current (Ipk) of MOSFET and discharging time (tDIS) of inductor current because output current (IO) is same as the average of the diode current (ID) in steady state. The output current estimator identifies the peak value of the drain current with a peak-detection circuit and calculates the output current using the inductor discharging time and switching period (tS). This output information is compared with an internal precise reference to generate error voltage (VCOMI), which determines the duty cycle of the MOSFET in Constant Current Mode. With Fairchild’s innovative TRUECURRENT® technique, the constant output current can be precisely controlled. Io N 1 t DIS 1 VCS P N S RSENSE 2 tS VOUT Linear Frequency Controller Freq. 6 VS VS Figure 8. Linear Frequency Control When output voltage decreases, secondary diode conduction time is increased and the linear frequency control lengthens the switching period, which retains DCM operation in the wide output voltage range, as shown in Figure 8. The frequency control also lowers primary rms current with better power efficiency in full-load condition. (1) TRUECURRENT® calculation makes a precise output current prediction. nVo Lm T t DIS 3 VO 4 Lm n 4 t 3 4 T 3 DIS 3 n VO 5 Lm 5 t 3 Figure 6. Detection for TRUECURRENT® Calculation DIS 5 T 3 Figure 9. Primary and Secondary Current BCM Control The end of secondary diode conduction time is possibly over a switching period set by linear frequency control. In this case, FL7732 doesn’t allow CCM and the operation mode changes from DCM to BCM. Therefore, FL7732 originally eliminates sub-harmonic distortion in CCM. Figure 7. TRUECURRENT® Calculation Principle Linear Frequency Control As mentioned above, DCM should be guaranteed for high power factor in flyback topology. To maintain DCM in the wide range of output voltage, frequency is linearly changed by the output voltage in linear frequency control. Output voltage is detected by the auxiliary winding and resistive divider connected to the VS pin, as shown in Figure 7. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.3 • 5/15/12 www.fairchildsemi.com 3 AN-9750 APPLICATION NOTE Protections The FL7732 have several self-protection functions, such as over-voltage protection, over-temperature protection, and pulse-by-pulse current limit. All the protections are implemented as Auto-Restart Mode. Open-LED Protection FL7732 protects external components, such as diode and capacitor at secondary side, in open-LED condition. During switch-off, the VDD capacitor is charged up to the auxiliary winding voltage, which is applied as the reflected output voltage. Because the VDD voltage has output voltage information, the internal voltage comparator at the VDD pin can trigger output over-voltage protection (OVP), as shown in Figure 9. When at least one LED is open-circuited, output load impedance becomes very high and output capacitor is quickly charged up to VOVP x NS / NA. Then switching is shut down and the VDD block goes into “Hiccup Mode” until the open-LED condition is removed, as shown in Figure 10. Figure 11. Waveforms at Open-LED Condition Internal Bias Short-LED Protection (OCP) In case of short-LED condition, the switching MOSFET and secondary diode are usually stressed by the high powering current. However, FL7732 changes the OCP level in the short LED condition. When VS voltage is lower than 0.4V, OCP level changes to 0.2V from 0.7V, as shown in Figure 12 so that powering is limited and external components current stress is relieved. VDD good + - VDD 4 VOVP S VDD good Q Shutdown Gate Driver R Figure 10. Internal OVP Block Under Voltage Lockout (UVLO) The turn-on and turn-off thresholds are fixed internally at 16V and 7.5V, respectively. During startup, the VDD capacitor must be charged to 16V. The VDD capacitor continues to supply VDD until power can be delivered from the auxiliary winding of the main transformer. VDD is not allowed to drop below 7.5V during this startup process. This UVLO hysteresis window ensures that VDD capacitor properly supplies VDD during startup. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.3 • 5/15/12 Figure 12. Internal OCP Block Figure 13 shows operational waveforms at short-LED condition. Output voltage is quickly lowered to 0V right after the LED-short event. Then, the reflected auxiliary voltage is also 0V making VS voltage less than 0.4V. 0.2V OCP level limits primary-side current and VDD hiccups up and down in between UVLO hysteresis. www.fairchildsemi.com 4 AN-9750 APPLICATION NOTE Over-Voltage Protection (OVP) The OVP prevents damage in over-voltage conditions. If the VDD voltage exceeds 23V at open-loop feedback condition, the OVP is triggered and the PWM switching is disabled. At open-LED condition, VDD reaches VDD_OVP. Then, autorestart sequence causes a delay, limiting output voltage. Over-Temperature Protection (OTP) The built-in temperature-sensing circuit shuts down PWM output if the junction temperature exceeds 150°C. There is hysteresis of 10°C. Figure 13. Waveforms at Short-LED Condition At short-LED condition, VS is low due to low output voltage. Then, OCP level is changed to 0.2V to reduce output current. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.3 • 5/15/12 www.fairchildsemi.com 5 AN-9750 APPLICATION NOTE Design Procedure V IN . min . pk 2 V IN .rms where the IIN.rms and VIN.rms are rms line input current and voltage, respectively. In this section, a design procedure a of single-stage flyback using FL7732 is presented using the schematic of Figure 1 as a reference. An offline LED driver with 16.8W (24V/0.7A) output has been selected as a design example. The design specifications are as follows: (5) tON is required to calculate reasonable Lm value. With Equation (2) ~ (5), the turn-on time, tON, is obtained as: tON 2 Input voltage range: 90 ~ 264VAC and 50 ~ 60Hz Nominal output voltage and current: 24V/0.7A Minimum efficiency: 87% Maximum switching frequency: 65kHz 2 Lm I IN .rms VI N .rms f s (6) The input power is given as: PIN I IN .rms Step 1. Inductor Selection (Lm) FL7732 operates with constant turn-on and turn-off time, as shown Figure 14. When MOSFET turn-on time (tON) and switching period (tS) are constant, IIN is proportional to VIN and can implement high power factor. PO (7) With Equation (6) and (7), the Lm value is obtained as: Lm (VIN .rms ) 2 f s t ON 2 (8) 2 PO (Design Example) Since the minimum input voltage is 90VAC, the maximum tON occurs at full-load condition. Assuming the maximum tON is 7.4µs at 65kHz of the maximum frequency, the magnetizing inductance is obtained as: 0.87 90 2 65 10 3 (7.4 10 6 ) 2 743µH 2 16.8 The maximum peak current of MOSFET at nominal output power is calculated as: Lm Figure 14. Theoretical Waveform The single-stage flyback using FL7732 is assumed to operate in DCM due to constant tON and tS. Input voltage is applied across the magnetizing inductance (Lm) during tON, charging the magnetic energy in Lm. Therefore, the maximum peak switch current (ISW.pk) of MOSFET occurs at peak point of line voltage, as shown Figure 14. The peak input current (IIN.pk) is also shown at the peak input voltage of one line cycle. Once the maximum tON is decided, ISW.pk of MOSFET is obtained at the minimum line input voltage and full-load condition as: I SW . pk tON VIN .min pk Lm I SW . pk Step 2. Sensing Resistor and nPS Selection Since FL7732 adopts TRUECURRENT® Calculation method to regulate constant output current (IO), as defined in equation 1. The output current is proportional to turn ratio nps between the primary and secondary windings of the transformer and inversely proportional to sensing resistor (RS). The FL7732 also implements cycle-by-cycle current limitation by detecting VCS to protect system from output short or overload. Therefore, VCS level to handle rated system power without the current limitation should be considered. It is typical to set the cycle-by-cycle limit level (typical: 0.67V) at 20~30% higher than CS peak voltage (VCS.pk) at full-load condition. MOSFET peak current (ISW.pk) is converted into VCS,pk as: (2) where VIN.min.pk and tON are the peak input voltage and the maximum turn-on time at the minimum line input voltage, respectively. Using equation 2, the peak input current is obtained by: I IN . pk V 1 IN . min . pk (t )( t ) fs ON ON 2 Lm 7.4 10 6 2 90 1.26 A 743 10 6 (3) VCS . pk I SW . pk RS (9) then IIN.pk and VIN.min.pk can be expressed as: I IN . pk 2 I IN .rms © 2011 Fairchild Semiconductor Corporation Rev. 1.0.3 • 5/15/12 (4) www.fairchildsemi.com 6 AN-9750 APPLICATION NOTE RVS 1 rVS RVS 2 According to Equation (1), the transformer turn ratio is determined by the sensing resistor and nominal output current as: n ps 10.5 I O RS where VVS.max is the VS value to set the maximum switching frequency for constant output current in rated power and VF is secondary diode forward voltage. (10) where: RVS 2 1 t DIS 1 VCS 2 tS 10.5 (11) VCS . pk I SW . PK RVS Step 3. nAS Selection 1 (0.545 RVS 2 100 10 6 24.86k (12) 23 0.77 30 Step 4. Resistor Selection (RVS1 and RVS2) Step 5. Design the Transformer The first consideration for RVS1 and RVS2 selection is that VS is 2.35V at the end of diode current conduction time to operate at maximum switching frequency at rated power. The second consideration is VS blanking, as explained below. The output voltage is detected by auxiliary winding and a resistive divider connected to the VS pin, as shown in Figure 7. However, in a single-stage flyback without DC link capacitor, auxiliary winding voltage cannot be clamped to reflected output voltage due to the small Lm current, which induces VS voltage sensing error. Then, frequency decreases rapidly at the zero-crossing point of line voltage, which can cause flicker. To maintain constant frequency over the whole sinusoidal line voltage, FL7732 has VS blanking to disable sampling of VS voltage at less than a particular line voltage by sensing the auxiliary winding. The number of primary turns is determined by Faraday’s law. Np,min is fixed by the peak value of the minimum line input voltage across the primary winding and the maximum on time. The minimum number of turns for the transformer primary side to avoid the core saturation is given by: N p ,min © 2011 Fairchild Semiconductor Corporation Rev. 1.0.3 • 5/15/12 V IN . min . pk t ON B sat Ae (16) where Ae is the cross-sectional area of the core in m2 and Bsat is the saturation flux density in Tesla. Since the saturation flux density decreases as the temperature rises, the high-temperature characteristics should be considered when it is used in an enclosed case. Considering the maximum switching frequency at rated power and VS blanking level, RVS1 and RVS2 are obtained as: (VO VF )n AS VVS .max VVS .max 7.06 0.77 2.91 ) It is recommended to place a bypass capacitor of 10 ~ 30pF closely between the VS pin and the GND pin to bypass the switching noise and keep the accuracy of the VS sensing for CC regulation. The value of the capacitor affects constantcurrent regulation. If a high value of VS capacitor is selected, the discharge time tDIS becomes longer and the output current is lower, compared to small VS capacitor. (Design Example) Once output over-voltage level is set as 30V, nAS is obtained as: RVS 0.545 50 Then RVS1 is determined to be 175.5kΩ. where (nAS=NA/NS) is the turns ratio the of secondary to auxiliary of transformer. Therefore, VO.OVP can be set by changing the nAS value. nAS (24 0.7) 0.77 2.35 7.06 2.35 Once VIN.bnk level is set to 50V, RVS2 is obtained as. When VDD voltage is 23V, FL7732 stops switching operation due to over-voltage protection (OVP). So nAS can be determined as follows: VDD.OVP 23 VO.OVP VO.OVP (15) (Design Example) The voltage divider network is determined as: 0.5 0.396 1.26 n ps 10.5 0.7 0.396 2.91 n AS 0.545 VIN bnk n AP 1 ) (0.545 6 RVS 100 10 where VIN.bnk and nAP are the blanking level of input voltage and the turn ratio of auxiliary to primary, respectively. The nAP can be calculated as the ratio of nAS to nPS. (Design Example) Once VCS,pk is set as 0.5V, the sensing resistor value is obtained as: RS (14) (13) www.fairchildsemi.com 7 AN-9750 APPLICATION NOTE (Design Example) An RM8 core is selected for the transformer and the minimum number of turns for the transformer primary side to avoid the core saturation is given by: N p ,min 2 90 7.4 10 6 54.5T 0.27 64 10 6 Considering the tolerance of the transformer and high ambient temperature, NP should be selected with a margin about 5% ~ 10% to avoid core saturation: N p 54.5 1.1 59.95T Once the turn number of the primary side (NP) is determined as 60T, the turn number of the secondary side (NS) is obtained by: Figure 15. Drain Voltage of MOSFET N S 60 2.91 20.5T (Design Example) Assuming that drain voltage overshoot is the same as the reflected output voltage, the maximum drain voltage across the MOSFET is calculated as: Once the turn number of the secondary side (NS) is determined as 20T, the auxiliary winding turns (NA) is obtained by: VDS (max) 374 N A 20 0.77 15.4T The rms current though the MOSFET is NA is determined to be 15T. I SW .rms 1.26 Step 6. Calculate the Voltage and Current of the Switching Devices NP (Vo VF ) VOS NS 7.4 0.065 0.357 A 6 Secondary-Side Diode: The maximum reverse voltage and rms current of the rectifier diode are obtained as: Primary-Side MOSFET: The voltage stress of the MOSFET was discussed when determining the transformer turns ratio. Assuming the drain voltage overshoot is the same as the reflected output voltage, the maximum drain voltage is given as: VDS (max) VIN . max . pk 60 (24 0.7) 2 522V 20 VD VO NS Vin. max . pk NP I D.rms I SW .rms (17) (19) Vin. min . pk N P 2 VRO N S (20) where Vin.max.pk is the maximum line peak voltage. (Design Example) The diode voltage and current are obtained as: The rms current (ISW.rms) though the MOSFET is given as: t f I SW .rms I pk ON S 6 VD 24 (18) 20 374 148.7V 60 I D.rms 0.357 © 2011 Fairchild Semiconductor Corporation Rev. 1.0.3 • 5/15/12 127 60 0.991A 2 74.1 20 www.fairchildsemi.com 8 AN-9750 APPLICATION NOTE Snubber capacitor voltage at full-load condition is given as: Step 7. Design RCD Snubber in Primary Side VSN VRO VOS When the power MOSFET is turned off, there is a highvoltage spike on the drain due to the transformer leakage inductance. This excessive voltage on the MOSFET may lead to an avalanche breakdown and eventually failure of the device. Therefore, it is necessary to use an additional network to clamp the voltage. The RCD snubber circuit and its waveform are shown in Figure 16 and Figure 17, respectively. The RCD snubber network absorbs the current in the leakage inductance by turning on the snubber diode (DSN) once the MOSFET drain voltage exceeds the cathode voltage of snubber diode. In the analysis of snubber network, it is assumed that the snubber capacitor is large enough that its voltage does not change significantly during one switching cycle. The snubber capacitor should be ceramic or a material that offers low ESR. Electrolytic or tantalum capacitors are unacceptable for these reasons. (21) The power dissipated in the snubber network is obtained as: 2 PSN VSN VSN 1 2 Llk I PK fS RSN 2 VSN VRO (22) where Llk is leakage inductance, VSN is the snubber capacitor voltage at full load, and RSN is the snubber resistor. The leakage inductance is measured at the switching frequency on the primary winding with all other windings shorted. Then, the snubber resistor with proper rated wattage should be chosen based on the power loss. The maximum ripple of the snubber capacitor voltage is obtained as: VSN C SN VSN RSN f S (23) In general, 5 ~ 20% ripple of the selected capacitor voltage is reasonable. In this snubber design, neither the lossy discharge of the inductor nor stray capacitance is considered. (Design Example) Since the voltage overshoot of drain voltage has been determined to be the same as the reflected output voltage, the snubber voltage is: VSN VRO VOS 150V The leakage inductance is measured as 10µH. Then the loss in snubber networking is given as: 150 1 PSN 10 10 6 1.26 2 65 10 3 2 150 75 1.03W Figure 16. Snubber Circuit RSN 150 2 21.84k 1.03 To allow 7% ripple on the snubber voltage (150V): C SN 150 10.06nF 0.07 150 21.84 103 65 103 Figure 17. Snubber Waveforms © 2011 Fairchild Semiconductor Corporation Rev. 1.0.3 • 5/15/12 www.fairchildsemi.com 9 AN-9750 APPLICATION NOTE Lab Notes 1. Before modifying or soldering/desoldering the power supply, discharge the primary capacitors through the external bleeding resistor. Otherwise, the PWM IC may be destroyed by external high-voltage during the process. This device is sensitive to electrostatic discharge (ESD). To improve the yield, the production line should be ESD protected as required by ANSI ESD S1.1, ESD S1.4, ESD S7.1, ESD STM 12.1, and EOS/ESD S6.1 standards. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.3 • 5/15/12 2. In case of LED-short condition, VDD voltage charged at VDD capacitor should touch VDD off level rapidly to stop switching. Therefore, VDD capacitor value is recommended under 22µF. www.fairchildsemi.com 10 AN-9750 APPLICATION NOTE Schematic of Design example Figure 18 shows the schematic of the 16.8W LED driver design example. RM8 core is used for the transformer. Figure 19 shows the transformer information. Figure 18. Schematic of the FL7732 17W Design Example Figure 19. Transformer Winding Structure No. Winding Pin (S → F) Wire Turns Winding Method 1 NP1 12 1 0.25φ 30 Ts Solenoid Winding 2 Insulation: Polyester Tape t = 0.025mm, 3-Layer 3 NS 7- 8 4 0.5φ (TIW) 20 Ts Solenoid Winding Insulation: Polyester Tape t = 0.025mm, 3-Layer 5 NP2 12 6 0.25φ 30 Ts Solenoid Winding Insulation: Polyester Tape t = 0.025mm, 3-Layer 7 8 NA 65 0.25φ 15 Ts Insulation: Polyester Tape t = 0.025mm, 3-Layer Solenoid Winding Pin Specification Remark Inductance 12– 2 750µH ± 10% 60kHz, 1V Leakage 1– 2 6µH 60kHz, 1V Short All Output Pins © 2011 Fairchild Semiconductor Corporation Rev. 1.0.3 • 5/15/12 www.fairchildsemi.com 11 AN-9750 APPLICATION NOTE Bill of Materials Item No. Part Reference Part Number Qty Description Manufacturer 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 BD1 CF1 CF2 CS1 CY1 CO1,CO2 C1 C2 C3 C4 C5 DS1 Do1 D1 F1 LF1 MOV1 Q1 RG1, R6 RS1,RS2 RCS1,RCS2 RCS3 RO1 R4 R1,R2,R3 R5 T1 U1 DF06S MPX AC275V 104K MPX AC275V 473K C1206C103KDRACTU SCFz2E472M10BW KMG 470µF/35V MPE 630V104K 14S KMG 22µF/50V C0805C104K5RACTU C0805C200J5GACTU C0805C225Z3VACTU RS1M ES3D 1N4003 SS-5-1A R10402KT00 SVC 471 D-07A FDD5N60NZ RC1206JR-0710L RC1206JR-07100KL RC1206JR-071RL RC1206JR-072R4L RC1206JR-0720KL RC1206JR-07150KL RC1206JR-0768KL RC1206JR-0724KL RM8 Core FL7732M_F116 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1 1 3 1 1 1 1.5A/600V Bridge Diode 104/AC275V X-Capacitor 473/AC275V X-Capacitor 103/1kV SMD Capacitor 3216 472/250V Y-Capacitor 470uF/35V Electrolytic Capacitor 104/630V MPE Film Capacitor 22uF/35V Electrolytic Capacitor 104/50V SMD Capacitor 2012 200/50V SMD Capacitor 2012 225/25V SMD Capacitor 2012 1000V/1A Ultra Fast Recovery Diode 200V/3A, Fast Rectifier 200V/1A, General Purpose Rectifier 250V/1A Fuse 4mH Inductor, 10Ø Metal Oxide Varistor 600V/4A, N-Channel MOSFET 10Ω SMD Resistor 3216 100kΩ SMD Resistor 3216 1Ω SMD Resistor 3216 2.4Ω SMD Resistor 3216 20KΩ SMD Resistor 3216 150KΩ SMD Resistor 3216 68KΩ SMD Resistor 3216 24KΩ SMD Resistor 3216 12pin, Transformer Main PSR Controller Fairchild Carli Carli Kemet Samwha Samyoung Sungho Samyoung Kemet Kemet Kemet Fairchild Fairchild Fairchild Bussmann Bosung Samwha Fairchild Yageo Yageo Yageo Yageo Yageo Yageo Yageo Yageo TDK Fairchild © 2011 Fairchild Semiconductor Corporation Rev. 1.0.3 • 5/15/12 www.fairchildsemi.com 12 AN-9750 APPLICATION NOTE Related Datasheets FL7732 — Single-Stage PFC Primary-Side-Regulation Offline LED Driver Reference Designs — http://www.fairchildsemi.com/referencedesign/ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.3 • 5/15/12 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 13