www.fairchildsemi.com AN-9741 Design Guideline for LED Lamp Control Using PrimarySide Regulated Flyback Converter, FL103M Introduction Many LED lamp systems use the flyback converter topology. In applications where precise output current regulation is required, current sensing in the secondary side is always necessary, which results in additional sensing loss. For power supply designers struggling to meet increasing regulatory pressures, the output current sensing is a daunting design challenge. Primary-Side Regulation (PSR) for power supplies can be an optimal solution for compliance and cost in LED lamp systems. Primary-side regulation controls the output voltage and current precisely with information in the primary side of the LED lamp controller only. This removes the output current sensing loss and eliminates secondary-feedback circuitry. This facilitates a higher efficiency power supply design without incurring tremendous costs. Fairchild’s PWM PSR controller FL103M simplifies meeting tighter efficiency requirements with few external components. This application note presents design considerations for LED lamp systems employing Fairchild Semiconductor components. It includes designing the transformer and output filter, selecting the components, and implementing constant-current control. The step-by-step procedure completes a power supply design. The design is verified through an experimental prototype converter using FL103. Figure 1 shows the typical application circuit for an LED lamp using FL103M. Figure 1. Typical Application Circuit © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/27/11 www.fairchildsemi.com AN-9741 APPLICATION NOTE decreases linearly from the peak value to zero. At the end of tDIS, all the energy stored in the inductor has been delivered to the output. Principle of Primary-Side Regulation Figure 2 shows typical waveforms of a flyback converter. Generally, Discontinuous Conduction Mode (DCM) operation is preferred for primary-side regulation since it allows better output regulation. The key of primary-side regulation is how to obtain output voltage and current information without directly sensing them. Once these values are obtained, the control can be accomplished by the conventional feedback compensation method. Stage I Stage III Stage II Stage III When the diode current reaches zero, the transformer auxiliary winding voltage (VA) begins to oscillate by the resonance between the primary-side inductor (Lm) and the output capacitor of MOSFET. Design Procedure In this section, a design procedure is presented using the schematic in Figure 3 as a reference. Stage I IPK VO VON Constant Voltage Operation A IDS I PK × N N Constant Current Operation fS = 50kHz P 0.5*VON S B fS = 33kHz IO = IF_AVG UVLO C Protection IF O VF × NA NS Figure 3. CV and CC Operation Area VO × NA NS [STEP-1] Estimate the Efficiencies Figure 3 shows the Constant Voltage (CV) and Constant Current (CC) operation area. To optimize the power stage design, the efficiencies and input powers should be specified for operating point A (nominal output voltage and current), B (50% of nominal output voltage), and C (minimum output voltage). VA tON IO ION tDIS tS 1. Estimated overall efficiency (η) for operating points A, B, and C: The overall power conversion efficiency should be estimated to calculate the input power. If no reference data is available, set η = 0.7 ~ 0.75 for low-voltage output applications and η = 0.8 ~ 0.85 for high-voltage output applications. 2. Estimated primary-side efficiency (ηP) and secondary-side efficiency (ηS) for operating points A, B, and C. Figure 4 shows the definition of primaryside and secondary-side efficiencies, where the primary-side efficiency is for the power transfer from AC line input to the transformer primary side, while the secondary-side efficiency is for the power transfer from the transformer primary side to the power supply output. Figure 2. Key Waveforms of PSR Flyback Converter The operation principles of DCM flyback converter are: Stage I During the MOSFET on time (tON), input voltage (VDL) is applied across the primary-side inductor (Lm). Then MOSFET current (IDS) increases linearly from zero to the peak value (IPK). During this time, the energy is drawn from the input and stored in the inductor. Stage II When the MOSFET is turned off, the energy stored in the inductor forces the rectifier diode (DF) to turn on. During the diode conduction time (tDIS), the output voltage (VO), together with diode forward-voltage drop (VF), are applied across the secondary-side inductor and the diode current (IF) © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/27/11 www.fairchildsemi.com 2 AN-9741 APPLICATION NOTE The typical values for the primary-side and secondary-side efficiencies are given as: The secondary-side efficiency at 50% of nominal output voltage (operating point B) can be approximated as: 0.5 × VO V +V ≅ ηS × × O N F N 0.5 × VO + VF VO N 1 3 2 3 (1) 2 3 1 3 (2) η P ≅ η ,η S ≅ η ;VO < 10V η P ≅ η ,η S ≅ η ;VO > 10V ηS @ B N (6) Then, the power supply input power and transformer input power at 50% nominal output voltage (operating point B) are given as: 0.5 × VO × I O N PIN @ B = N (7) η@ B 0.5 × VO × I O N PIN _ T @ B = N (8) ηS @ B The overall efficiency at the minimum output voltage (operating point C) can be approximated as: η@ C ≅ η × Figure 4. Primary- and Secondary-Side Efficiency VO × I O N (3) η@ C where VO and IO are the nominal output voltage and current, respectively. VO × I O PIN @ C = N (4) ηS When the output voltage drops below 50% of its nominal value, the frequency is reduced to 33kHz to prevent CCM operation. Thus, the transformer should be designed for DCM both at 50% of nominal output voltage and minimum output voltage. N N (10) min × IO N (11) η@ C VO min × IO N (12) ηS @C It is typical to select the DC link capacitor as 2-3µF per watt of input power for universal input range (90 ~ 265VRMS) and 1µF per watt of input power for European input range (195 ~ 265VRMS). With the DC link capacitor chosen, the minimum DC link voltage is obtained as: N VDL (5) min = 2 × (VLINE min 2 ) − PIN (1 − Dch ) C DL × f L (13) where VLINEmin is the minimum line voltage, CDL is the DC link capacitor, fL is the line frequency, and Dch is the DC link capacitor charging duty ratio defined as shown in Figure 5 (typically about 0.2). where VF is diode forward-voltage drop. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/27/11 min [STEP-2] Determine the DC Link Capacitor (CDL) and the DC Link Voltage Range The overall efficiency at 50% of nominal output voltage (operating point B) can be approximated as: 0.5 × VO V +V × O N F N 0.5 × VO + VF VO VO PIN _ T @ B = As output voltage reduces in CC Mode, the efficiency also drops. To optimize the transformer design, it is necessary to estimate the efficiencies properly at 50% of nominal output voltage and minimum output voltage conditions. η@ B ≅ η × V +V ≅ η S × min × O N F VO + VF VO VO Then, the power supply input power and transformer input power at the minimum output voltage (operating point C) are given as: The input power of the transformer at nominal output is given as: PIN _ T = (9) The secondary-side efficiency at minimum output voltage (operating point C) can be approximated as: N N min N N η N VO V +V × O N F + VF VO min where, Vomin is the minimum output voltage. With the estimated overall efficiency, the input power at nominal output is given as: PIN = VO www.fairchildsemi.com 3 AN-9741 APPLICATION NOTE voltage should be also considered. The maximum voltage stress of MOSFET is given as: VDS T = 1 T2 D ch max = VDL max + VRO + VOS (20) For reasonable snubber design, voltage overshoot (VOS) is typically 1~1.5 times the reflected output voltage. It is also typical to have a margin of 15~20% of breakdown voltage for maximum MOSFET voltage stress. Figure 5. DC Link Voltage Waveforms The maximum DC link voltage is given as: VDL = 2 × VLINE max max (14) where VLINEmax is the maximum line voltage. (VO + VF ) × The minimum input DC link voltage at 50% nominal output voltage is given as: VDL @ B min = 2 × (VLINE ) − min 2 PIN @ B (1 − Dch ) C DL × f L (15) The minimum input DC link voltage at minimum output voltage are given as: VDL @ C min = 2 × (VLINE ) − min 2 PIN @ C (1 − Dch ) C DL × f L Figure 6. Voltage Stress of MOSFET The transformer turns ratio between the auxiliary winding and secondary winding (NA/NS) should be determined by considering the permissible IC supply voltage (VDD) range and minimum output voltage in constant current. When the LED operates in constant current, VDD is changed, together with the output voltage, as seen Figure 7. The overshoot of auxiliary winding voltage caused by the leakage inductance also affects the VDD. At light-load condition, where the overshoot of auxiliary winding voltage is negligible, VDD voltage is given as: (16) [STEP-3] Determine Transformer Turns Ratio Figure 6 shows the MOSFET drain-to-source voltage waveforms. When the MOSFET is turned off, the sum of the input voltage (VDL) and the output voltage reflected to the primary is imposed across the MOSFET as: VDS nom = VDL max + VRO VDD (17) NS × (VO + VF ) NP (18) where VF is the diode forward voltage drop and NP and NS are number of turns for the primary side and secondary side, respectively. When the MOSFET is turned on; the output voltage, together with input voltage reflected to the secondary, are imposed across the diode as: N max VF = VO + S × VDL NP (19) = NA × (VO + VF ) − VFA NS (21) VDD max VDD min 2 ≅ NA NS N × VO + VF + S × VOS − VFA NP (22) ≅ NA NS min N × VO + VF + S × VOS − VFA NP (23) where VFA is the diode forward-voltage drop of auxiliary winding diode. As observed in Equations (5) and (6), increasing the transformer turns ratio (NP/NS) results in increased voltage of MOSFET, while it leads to reduced voltage stress of rectifier diode. Therefore, the transformer turns ratio (NP/NS) should be determined by the compromise between MOSFET and diode voltage stresses. When determining the transformer turns ratio, the voltage overshoot (VOS) on drain © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/27/11 min 1 The actual VDD voltage at heavy load is higher than Equation (21) due to the overshoot by the leakage inductance, which is proportional to the voltage overshoot of MOSFET drain-to-source voltage shown in Figure 7. Considering the effect of voltage overshoot, the VDD voltages for nominal output voltage and minimum output voltage are given as: where VRO is reflected output voltage defined as: VRO = NP NS www.fairchildsemi.com 4 AN-9741 APPLICATION NOTE Transformer primary-side inductance can be calculated as: Lm = (VDL @ B min × tON @ B ) 2 × f S 2 × PIN _ T @ B (26) The maximum peak-drain current can be obtained at the nominal output condition as: I DS PK 2 × PIN _ T = Lm × f S (27) The MOSFET conduction time at the nominal output condition is obtained as: tON = I DS PK × Lm VDL min (28) The minimum number of turns for the transformer primary side to avoid the core saturation is given by: Figure 7. VDD and Winding Voltage Lm × I DS Bsat × Ae PK NP [STEP-4] Design the Transformer Figure 8 shows the definition of MOSFET conduction time (tON), diode conduction time (tDIS), and non-conduction time (tOFF). The sum of MOSFET conduction time and diode conduction time at 50% of nominal output voltage is obtained as: min V DL @ B N t ON @ B + t DIS @ B = t ON @ B 1 + S × N P 0.5 × VO + VF IDS tON (29) Figure 9 shows the typical characteristics of ferrite core from TDK (PC40). Since the saturation flux density (Bsat) decreases as the temperature rises, the high-temperature characteristics should be considered for a charger in an enclosed case. If there is no reference data, use Bsat =0.25~0.3T. (24) Once the turns ratio is obtained, determine the proper integer for NS so that the resulting NP is larger than NPmin obtained from Equation (29). Once the tOFF is determined, by considering the frequency variation caused by frequency hopping and its own tolerance, the MOSFET conduction time is obtained as: tON @ B = where Ae is the cross-sectional area of the core in m2 and Bsat is the saturation flux density in Tesla. The first step in transformer design is to determine how much non-conduction time (tOFF) is allowed in DCM operation. 1 − tOFF @ B fS = min VDL @ B NS 1+ × N P 0.5 × VO + VF min (25) IF tDIS tOFF t tS Figure 8. Definition of tON, tDIS, and tOFF Figure 9. Typical B-H Curves of Ferrite Core (TDK/PC40) © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/27/11 www.fairchildsemi.com 5 AN-9741 APPLICATION NOTE [STEP-6] Output Voltage and Current Setting DCM operation at minimum output voltage should be also checked. The MOSFET conduction time at minimum output voltage is given as: tON @ C = 1 VDL @ C min × 2 × PIN _ T @ C × Lm The nominal output current is determined by the sensing resistor value and transformer turns ratio as: RSense = (30) f SR where fSR is the reduced switching frequency to prevent CCM operation. N R1 VO N = × A −1 R2 Vref N S min t OFF @ C (31) It is recommended to place a bypass capacitor of 22~68pF closely between the VS pin and the GND pin to bypass the switching noise and keep the accuracy of the sampled voltage for CV regulation. The value of the capacitor affects the load regulation and constant-current regulation. Figure 10 illustrates the measured waveform on the VS pin with a different VS capacitor. If a higher-value VS capacitor is used, the charging time becomes longer and the sampled voltage is higher than the actual value. [STEP-5] Calculate the Voltage and Current of the Switching Devices Primary-Side MOSFET The voltage stress of the MOSFET was discussed when determining the turns ratio in STEP-3. Assuming that drainvoltage overshoot is the same as the reflected output voltage, maximum drain voltage is given as: max = VDL max + VRO + VOS (37) Select 1% tolerance resistor for better output regulation. The non-conduction time should be larger than 3µs (10% of the switching period), considering the tolerance of the switching frequency. VDS (36) The voltage divider R1 and R2 should be determined such that VS is 2.5V at the end of diode current conduction time, as shown in Figure 8. Then, the non-conduction time at minimum output voltage is given as: VDL @ C N 1 = − tON @ C (1 + P × min ) f SR N S VO + VF NP N N S × I O × 8.5 (32) The RMS current though the MOSFET is given as: I DS rms = I DS PK × tON × f S 3 (33) Secondary-Side diode The maximum reverse voltage and the RMS current of the rectifier diode are obtained, respectively, as: N VF = VO + NS max × VDL NP (34) Figure 10. Sampling Voltage with Different VS Capacitors min IF rms = I DS rms × VDL N × P VRO NS FL103 is able to control brownout voltage by VS resistors. When the current through VS (IVS) is typically 175µA, the FL103 triggers brownout protection. At that time, VS is 1.13V. The brownout voltage is obtained, respectively, as: (35) N V A = VDL × − A NP (38) VS VS − V A + R2 R1 (39) I VS = When input voltage is low line & output load is heavy, IVS should be larger than 227µA. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/27/11 www.fairchildsemi.com 6 AN-9741 APPLICATION NOTE [STEP-7] Determine the Output Filter Stage voltage does not change significantly during one switching cycle. The snubber capacitor should be ceramic or a material that offers low ESR. Electrolytic or tantalum capacitors are unacceptable for these reasons. The peak to peak ripple of capacitor current is given as: ∆I CO = NP PK × I DS NS (40) The snubber capacitor voltage at full-load condition (VSN) is given as: The voltage ripple on the output is given by: ∆I − I O N ∆I × t ∆VO = CO DIS × CO 2 × CO ∆I CO VSN = VRO + VOS 2 + ∆I CO × RC (41) The power dissipated in the snubber network is obtained as: 2 Sometimes it is impossible to meet the ripple specification with a single output capacitor (CO) due to the high ESR (RC) of the electrolytic capacitor. Additional LC filter stages (post filter) can be used. When using post filters, do not to place the corner frequency too low as this may make the system unstable or limit the control bandwidth. It is typical to set the corner frequency of the post filter at around 1/10 ~ 1/5 of the switching frequency. PSN = VSN VSN 1 PK = × Llk × ( I DS ) 2 × × fS RSN 2 VSN − VOS (43) where IDSPK is peak-drain current at full load, Llk is the leakage inductance, VSN is the snubber capacitor voltage at full load, and RSN is the snubber resistor. The leakage inductance is measured at the switching frequency on the primary winding with all other windings shorted. Then, the snubber resistor with proper rated wattage should be chosen based on the power loss. The maximum ripple of the snubber capacitor voltage is obtained as: [STEP-8] Design the RCD Snubber in the Primary Side When the power MOSFET is turned off, there is a highvoltage spike on the drain due to the transformer leakage inductance. This excessive voltage on the MOSFET may lead to an avalanche breakdown and, eventually, failure of the device. Therefore, it is necessary to use an additional network to clamp the voltage. The RCD snubber circuit and MOSFET drain-voltage waveform are shown in Figure 6. The RCD snubber network absorbs the current in the leakage inductance by turning on the snubber diode (DSN) once the MOSFET drain voltage exceeds the voltage of cathode of DSN. In the analysis of snubber network, it is assumed that the snubber capacitor is large enough that its © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/27/11 (42) ∆VSN = VSN CSN × RSN × f S (44) In general, 5~20% ripple of the selected capacitor voltage is reasonable. In the snubber design in this section, neither the lossy discharge of the inductor nor stray capacitance is considered. In the actual converter, the loss in the snubber network is less than the designed value due to this effect. www.fairchildsemi.com 7 AN-9741 APPLICATION NOTE Design Example Using FL103M Table 1. Cable Compensation Application Device Input Output LED Bulb FL103M 85VAC ~ 265VAC (50Hz/60Hz) 8.4W (24V/0.36A) Description Symbol Value Unit min 85 VAC max 265 VAC System Specifications Minimum Line Input Voltage VLINE Maximum Line Input Voltage VLINE Line Frequency fL Setting Output Voltage Input 60 Hz 24 V VO@B 12 V min 10 V N VO Output Voltage at Point B Minimum Output Voltage VO N Normal Output Current IO 0.35 A Second Diode Voltage Drop VF 1.1 V Normal Switching Frequency fS 50 kHz Switching Frequency between Point B and Point C fSR 33 kHz Efficiency η 0.80 Secondary-Side Efficiency ηS 0.93 Estimated Efficiency Input Input Power Output PIN 10.50 Input Power of Transformer PIN_T 9.05 Overall Efficiency at Point B η@B 0.77 Secondary-Side Efficiency at Point B ηS@B 0.89 Input Power at Point B PIN@B 5.48 PIN_T@B 4.72 η@C 0.75 Input Power of Transformer at Point B Overall Efficiency at Point C Secondary Side Efficiency at Point C ηS@C 0.87 Input Power at Point C PIN@C 4.64 PIN_T@C 4.00 CDL 20 Input Power of Transformer at Point C W Determine DC Link Capacitor & DC Link Voltage Range Input DC Link Capacitor Minimum DC Link Voltage Output min 86 max 375 VDL Maximum DC Link Voltage VDL min 104 min 107 Minimum DC Link Voltage at Point B VDL@B Minimum DC Link Voltage at Point C VDL@C µF V Determine the Transformer Turn Ratio Input max 24.0 min 8.0 ripple 3.8 VP-P V Maximum VDD VDD Minimum VDD VDD VDD Ripple in Burst Mode VDD VDD Diode Drop Voltage VFA 0.7 Determine NP/NS Ratio NP/NS 3.20 Determine NA/NS Ratio NA/Ns 0.68 V Continued on the following page… © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/27/11 www.fairchildsemi.com 8 AN-9741 APPLICATION NOTE Description Symbol Value Unit VRO 80 V NA/NS Ratio 1 1 NA/NS 0.50 NA/NS Ratio 2 2 NA/NS 0.24 NA/NS Ratio 3 NA/NS 3 0.49 Maximum Rectifier Output Voltage Output Transformer Design Non-Conduction Time at Point B Input Output tOFF@B 4.00 us Transformer Core Cross-Sectional Area Ae 31.0 mm Maximum Flux Density Bsat 0.30 T Determine Secondary Side Turns NS 23 Turns MOSFET Conduction Time at Point A tON 7.66 us Inductor Discharge Time at Point A tDIS 8.24 us Non-Conduction Time at Point A tOFF 4.10 us 2 MOSFET Conduction Time at Point B tON@B 4.60 us Inductor Discharge Time at Point B tDIS@B 11.40 us MOSFET Conduction Time at Point C tON@C 5.08 us Inductor Discharge Time at Point C tDIS@C 15.25 us Non-Conduction Time at Point C tOFF@C 9.98 us Lm 1.21 mH PK 0.55 A min Transformer Primary-Side Inductance Peak Drain Current IDS Minimum Primary-Side Turns 71.13 Turns Primary-Side Turns Np Np 74 Turns Auxiliary Winding Turns NA 16 Turns Final NP/NS Ratio NP/NS 3.22 Final NA/NS Ratio NA/Ns 0.70 VOS Selection Switching Device Input Output MOSFET Overshoot Voltage 40 V max 495 V rms 0.20 A 140 V 0.65 A MOSFET Maximum Drain-Source Voltage VDS MOSFET RMS Current IDS Maximum Second Diode Voltage VF Second Diode RMS Current IF rms Setting Output Voltage and Current Input Determine VS High-Side Resistor R1 91 KΩ Determine VS Low-Side Resistor R2 16 KΩ Determine Current-Sensing Resistor 1 Rsense1 2.4 Ω Determine Current-Sensing Resistor 2 Rsense2 2.2 Ω Calculate VS High-Side Resistor R1 90.85 KΩ 1 VA -27.52 V Auxiliary Current at 90VAC low IVS 379.59 uA DC Link Voltage at Brownout VDL 38.83 V Calculate Current-Sensing Resistor Rsense 1.08 Ω Auxiliary Voltage at Low Line Output cal © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/27/11 BO www.fairchildsemi.com 9 © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/27/11 N L 250V/1A F1 D2 1N4007 D1 1N4007 D3 1N4007 D4 1N4007 + 10 1.5uH L102 C101 C102 10uF/400V 10uF/400V 1mH L101 + 6 7 8 3 FL103 GND NC HV VDD NC CS GATE VS 4 1 2 5 D102 1N4007 C103 4.7n/1kV C104 10uF/50V U101 + R101 100K/3216 R102 120K/3216 R107 2R2/3216 R104 100R/2012 Q101 R103 2N60 10R/2012 C105 47pF/2012 D101 1N4007 T101 R108 2R4/3216 R105 91K/2012 1 4 2 5 R106 16K/2012 C106 2.2n 9 10 R201 24K/3216 EGP20D D201 + GND C201 100uF/35V OUTPUT AN-9741 APPLICATION NOTE Design Summary Using FL103M Figure 11. Schematic for LED Bulb www.fairchildsemi.com AN-9741 APPLICATION NOTE Transformer for LED Bulb Core: EFD-20 (Material: PC-40) Bobbin: 10-Pin 3mm 3mm Tape 3T 1 2 5 Na Tape 3T Np2 Tape 3T 3 9 10 Ns Tape 3T 3 Np1 4 Primary Secondary Figure 12. Transformer Specifications and Construction Table 2. Winding Specifications No. Winding Pin (S F) Wire Turns Winding Method 1 Np1 43 0.20 Φ * 1 62 Solenoid Winding 2 Insulation: Polyester Tape t = 0.05mm, 3 Layers 3 Ns 10 9 Np2 35 4 0.32 Φ (TEX) * 1 23 Solenoid Winding Insulation: Polyester Tape t = 0.05mm, 3 Layers 5 0.20 Φ * 1 6 12 Center Solenoid Winding Insulation: Polyester Tape t = 0.05mm, 3 Layers 7 Na 21 8 0.20 Φ * 1 16 Center Solenoid Winding Outer Insulation: Polyester Tape t = 0.05mm, 3 Layers Table 3. Electrical Characteristics Pin Specification Remark Inductance 4-5 1.2mH ±7% 1kHz, 1V Leakage 4-5 Maximum 20µH Short all output pins © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/27/11 www.fairchildsemi.com 11 AN-9741 APPLICATION NOTE Related Datasheets FL103 — Primary-Side Regulation PWM Controller Datasheet DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/27/11 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 12