FAIRCHILD AN4107

www.fairchildsemi.com
Application Note AN4107
Design of Power Factor Correction Using FAN7527
1. Introduction
power factor is obtained.
The FAN7527 is an active power factor correction(PFC)
controller for boost PFC application which operates in the
critical conduction mode. It turns on MOSFET when the
inductor current reaches zero and turns off MOSFET when
the inductor current meets the desired input current reference
voltage as shown in Fig. 1. In this way, the input current
waveform follows that of the input voltage, therefore a good
1-1. Internal Block Diagram
It contains following blocks.
• Error amplifier (E/A)
• Zero current detection (Idet)
• Switch current sensing (CS)
• Input voltage sensing (MULT)
• Switch drive (OUT)
.
Inductor Peak Current
Inductor Current
Inductor Average Current
Gating
Signal
Figure 1. Inductor Current Waveform
Vcc
8
2.5V Ref
+
−
12V
Vcc
Internal
Bias
UVLO
9V
7
Drive
Output
OUT
Timer R
Idet
+
−
5
6.5V
2V 1.5V
Q
Zero Current
Detector
Static OVP
40k
CS
S
4
8pF
+
−
+
−
R
Current Sense
Comparator
2.25V
Vref
Veao(L)=2.25V
1.8V
Vmo
MULT 3
Vm1
−
0 ~ 3.8V
Vmo
Vm1 ⋅ (Vm 2 − Vref )
+
−
+
Vm2
Multiplier
K=
0.25V
Vref~Vref+2.5V
OVP
Current
Detector
6
2
GND
EA_OUT
Isovp=30uA
Idovp=40uA
Vref
Vea(-)
1 INV
Error Amp
Figure 2. Block diagram of the FAN7527
Rev. 1.0.2
©2001 Fairchild Semiconductor Corporation
Rev. A, May 2000
AN4107
APPLICATION NOTE
2. Device Block Description
2-1. Error Amplifier and Over Voltage
Protection Block
The sensed and divided output voltage is fedback to the error
amplifier inverting input(INV) to regulate the output
voltage. The non-inverting input is internally biased at 2.5V.
The error amp output(EA_OUT) is internally connected to
the multiplier and is pinned out for the loop compensation.
Generally, the control loop bandwidth of PFC converter is
set below 20Hz to get a good power factor. In this
application, a capacitor is connected between INV and
EA_OUT. However, in case of over voltage condition, the
E/A must be saturated low as soon as possible, but the
narrow E/A bandwidth slows down the response. To make
the over voltage protection fast, the soft OVP and dynamic
OVP is added. The FAN7527 monitors the current flowing
into the EA_OUT pin. If the monitored current reaches about
30uA, the output of multiplier is forced to be decreased, thus
reducing the input current drawn from the mains(soft OVP).
If the monitored current exceeds 40uA, the OVP protection
is triggered(dynamic OVP), then the external power
transistor is switched off until the current falls below about
10uA. In this case, it disables some internal blocks reducing
the quiescent current of the chip to 2mA. However, if the
over voltage lasts so long that the output of E/A goes below
2.25V, then the protection is activated(static OVP) keeping
the output stage and the external power switch turned off.
The operation of the device is re-enabled as the E/A output
goes back into its linear region.
Static OVP
+
−
Output
Stage
2.25V
Vref
VO
Multiplier
−
+
−
+
Vm2 Vref~Vref+2.5V
OVP
Current
Detector
Isovp=30uA
Idovp=40uA
Vref
Vea(-)
1
INV
R1
R2
Error Amp
2
Figure 3. Error Amplifier and OVP Block
2-2. Multiplier
A single quadrant, two input multiplier is the critical element
that enables this device to get power factor correction. One
input of multiplier(Pin 3) is connected to an external resistor
divider which monitors the rectified ac line voltage. The
other input is internally driven by a DC voltage which is the
difference between error amplifier output (Pin 2) and
reference voltage, Vref. The multiplier is designed to have an
extremely linear transfer curve over a wide dynamic range,
0V to 3.8V for Pin 3, and 2.25V to 6V for error amplifier
output under all line and load conditions.
The multiplier output controls the current sense comparator
threshold voltage as the ac voltage traverses sinusoidally
from zero to peak line. This allows the inductor peak current
to follow the ac line thus forcing the average input current to
be sinusoidal. In other words, this has the effect of forcing
the MOSFET on-time to track the input line voltage,
resulting in a fixed drive output on-time, thus making the
pre-converter load appear to be resistive to the ac line.
2
The equation below describes the relationship between
multiplier output and its inputs.
Vmo = K × Vm1 × (Vm2 - Vref)
K : Multiplier gain
Vm1: Voltage at Pin 3
Vm2: Error amp output voltage
Vmo: Multiplier output voltage
©2001 Fairchild Semiconductor Corporation
APPLICATION NOTE
AN4107
Current Sense
Comparator
OVP
Vref
Veao(L)=2.25V
1.8V
Vmo
−
Vm1
MULT 3
0.25V
+
−
+
Vm2
0 ~ 3.8V
Multiplier
Vref~Vref+2.5V
OVP
Current
Detector
Vmo
K=
Vm1 ⋅ (Vm 2 − Vref )
Isovp=30uA
Vref
Vea(-)
1 INV
Error Amp
Idovp=40uA
2
EA_OUT
Figure 4. Multiplier block
2-3. Current Sense Comparator
The current sense comparator adopts the RS latch
configuration to ensure that only a single pulse appears at the
drive output during a given cycle. MOSFET drain current is
sensed using an external sense resistor in series with the
external MOSFET. When the sensed voltage exceeds the
threshold set by the multiplier output, the current sense
comparator turns off the MOSFET and resets the PWM
latch. The latch insures that the output remains in a low state
after the MOSFET drain current falls back to zero.
The peak inductor current under the normal operating
condition is controlled by the multiplier output, Vmo. The
abnormal operating condition occurs during pre-converter
start-up at extremely high line or as output voltage sensing is
lost. Under these conditions, the multiplier output and
current sense threshold will be internally clamped to 1.8V.
Therefore, the maximum peak switch current is limited to:
Ipk(max) = 1.8V / Rsense
In the FAN7527, an internal R/C filter has been included to
attenuate any high frequency noise that may be present on
the current waveform. This circuit block eliminates the need
for an external R/C filter otherwise required for proper
operation of the circuit.
CS
40k
4
8pF
Rsense
+
−
Current Sense
Comparator
1.8V
Vmo
Figure 5. Current Sense Circuit
©2001 Fairchild Semiconductor Corporation
3
AN4107
APPLICATION NOTE
2-4. Zero Current Detector
FAN7527 operates as a critical conduction current mode
controller. The zero current detector switches on the external
MOSFET as the voltage across the boost inductor reverses,
just after the current through the boost inductor has gone to
zero. The slope of the inductor current is indirectly detected
by monitoring the voltage across an auxiliary winding and
connecting it to the zero current detector Pin 5.
Once the inductor current reaches ground level, the polarity
of the voltage across the winding is reversed. When the Idet
input falls below 1.5V, the comparator output is triggered to
the low state. To prevent false tripping, 0.5V hysteresis is
provided. The zero current detector input is protected
internally by two clamps. The upper 6.5V clamp prevents
input over voltage breakdown while the lower 0.75V clamp
prevents substrate injection. An internal current limit resistor
protects the lower clamp transistor in case the Idet pin is
shorted to ground accidentally. A watchdog timer function is
added to the IC to eliminate the need for an external
oscillator when used in stand-alone applications. The timer
provides a means to start or restart the pre-converter
automatically if the drive output has been off for more than
500us after the inductor current reached zero.
Vin
Idet
+
−
5
6.5V
2V 1.5V
To F/F
Zero Current
Detector
Figure 6. Zero Current Detector Block
2-5. Output Drive
The FAN7527 contains a single totem-pole output stage
designed specifically for a direct drive of power MOSFET.
The drive output is capable of up to 500mA peak current
with a typical rise and fall time of 130ns, 50ns respectively
with a 1.0nF load. Additional circuitry has been added to
keep the drive output in a sinking mode whenever the UVLO
is active. This characteristic eliminates the need for an
external gate pull-down resistor. Internal voltage clamping
ensures that the output driver is always lower than 14V when
supply voltage exceeds the rated Vgs of the external
MOSFET. This eliminates an external zener diode and extra
power dissipation associated with it that otherwise is
required for the reliable circuit operation.
3. Circuit Components Design
switching frequency limitation. The minimum switching
frequency has to be above the audio frequency.
The switching period is maximum when the input voltage is
highest at maximum load condition. TS(max) is a function of
Vin(peak) and VO. It can have maximum value at highest line
or at lowest line according to VO. Check TS(max)
at
Vin(peak_min) and Vin(peak_max) , then take the higher value
for the maximum switching period. The boost inductor value
can be obtained by (5)
t
on
(t )
2I
sin ( ωt )
I
in ( peak )
L ( peak )
= L ---------------------------------------------- = L ----------------------------------------------V
sin ( ωt )
V
sin ( ωt )
in ( peak )
in ( peak )
(1)
2I
in ( peak )
= L ---------------------------V
in ( peak )
3-1. Power stage design
1) Boost inductor design
The boost inductor value is determined by the minimum
4
©2001 Fairchild Semiconductor Corporation
APPLICATION NOTE
AN4107
2) Auxiliary winding design
I L ( peak ) ( t )
2I in ( peak ) sin ( ωt )
t off = L -------------------------------- = L ------------------------------------------------------V O – sin ( ωt )
V O – V in ( peak ) sin ( ωt )
2V O I O
I in ( peak ) = -----------------------------η ⋅ V in ( peak )
T
S
= t
The auxiliary winding voltage is lowest at the highest line.
So the number of auxiliary winding can be obtained by (7).
A small resistor is connected to the auxiliary winding to
suppress the high frequency ringing voltage.
(2)
(3)
on
+t
V CC ⋅ N P
N aux = ------------------------------------------------2
V – 2
----------- V in ( HL )
 O

π
off


1
sin ( ωt )
= 2LI in ( peak )  ----------------------------- + ----------------------------------------------------------------
 V in ( peak ) V O – V in ( peak ) sin ( ωt )
(4)
4LV I

1
O O ( max ) 
1
= -----------------------------------------  -------------------------------- + ------------------------------------------------------------------------------
V
(V – V
)
η
 V2
in ( peak ) O
in ( peak )
in ( peak )
4LV I

O O ( max ) 
1
1
TS ( max ) = -----------------------------------------  -------------------------------- + ------------------------------------------------------------------------------ (5)
η
V
(V – V
)
 V2
in ( peak ) O
in ( peak )
in ( peak )
(7)
3) Input capacitor design
The voltage ripple of the input capacitor is maximum when
the line is lowest and the load is heaviest. If fsw(min) >> fac ,
the input current can be assumed to be constant during a
switching period.
η
L = ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- (6)


1
1
-------------------------------- + ------------------------------------------------------------------------------
4f
V I

sw ( min ) O O ( max )  2
V in ( peak ) ( V O – V in ( peak ) )
V in ( peak )
Inductor
Current
2 ⋅ I in ( peak _ max)
Input
Current
I in( peak _ max)
t on / 2
t on
Figure 7. Input Current and Inductor Current Waveform during a Switching Cycle
2
C in ≥ ------------------------- ⋅
∆V in ( max )
∫
ton
-------2
V a = V A = V in ( peak ) cos ( ωt )
2 ⋅ I in ( peak_max )
I
– -------------------------------------- t dt
 in ( peak_max )

t on
t on ⋅ I in ( peak_max )
≥ -----------------------------------------2 ⋅ ∆V in ( max )
2
(8)
2
L ⋅ I O ( max ) ⋅ V O
≥ ----------------------------------------------------------------3
∆V in ( max ) ⋅ V in ( peak_max )
(9)
i a = I a cos ( ωt )
0
i A = i a + i c = I a cos ( ωt ) – ωC in V in ( peak ) sin ( ωt )
θ = tan
– 1 ωC in V in ( peak )
( 11 )
----------------------------------Ia
Ia
C in ( max ) = --------------------------- tan ( cos
ωV in ( peak )
2V O I O
- tan ( cos
= --------------------------------------2
ωV in ( peak_max )
–1
( 10 )
–1
( IDF ) )
( IDF ) )
( 12 )
The input capacitor must be larger than the value calculated
by (8). And the maximum input capacitance is limited by the
input displacement factor(IDF), defined as IDF≡cosθ .
Therefore the input capacitor must be smaller than Cin(max)
calculated by (12).
©2001 Fairchild Semiconductor Corporation
5
AN4107
APPLICATION NOTE
Lin
iA
iC
+
C in
VA
Im
ia
−
iA
+
iC
PFC
Circuit
Va
−
ia
θ
Re
VA
Input Filter
Figure 8. Input voltage and current displacement due to input filter capacitance
4) Output capacitor design
The output capacitor is determined by the relation between
the input power and the output power. As shown in Fig. 10,
the minimum output capacitance is determined by (14).
ID
I in
IO
PFC
+
LOAD
CO
Vin
−
+
VO
−
Figure 9. PFC configuration
P in = I in ( rms ) V in ( rms ) ( 1 – cos ( 2ωt ) ) = I D V O
I in ( rms ) V in ( rms )
I D = -------------------------------------- ( 1 – cos ( 2ωt ) )
VO
= I O ( 1 – cos ( 2ωt ) )
I O ( max )
C O ( min ) ≥ ------------------------------------------2πf ac ⋅ ∆V O ( max )
( 14 )
5) MOSFET and diode selection
Maximum MOSFET rms current is obtained by (15) and the
conduction loss of the MOSFET is calculated by (16). When
MOSFET turns on the MOSFET current rises slowly so the
turn on loss is negligible. MOSFET turn off loss and
MOSFET discharge loss are obtained by (17) and (18)
respectively. The switching frequency of the critical
conduction mode boost PFC converter varies according to
the line condition and load condition. Therefore the
switching frequency is the average value during a line
period. The total MOSFET loss can be calculate by (19) and
then a MOSFET can be selected considering MOSFET
thermal characteristic.
1 4 2Vin ( LL )
I Qrms = I L ( peak_max ) --- – ---------------------------6
9πV O
( 13 )
2 2 ⋅ VO I O ( max ) 1 4 2V in ( LL )
= ----------------------------------------- --- – ---------------------------ηV in ( LL )
9πV O
6
I D ( avg ) = I O (1 − cos( 2ω t ))
P on = I
IO
2
Qrms
⋅ R DSon
( 15 )
( 16 )
1
P turn – off = --- V O I L ( peak_max ) ⋅ t f ⋅ f sw
6
2
2 V O ⋅ I O ( max )
= ------- --------------------------------- ⋅ t f ⋅ f sw
3 ηV in ( LL )
( 17 )
4
2
P disch arg e = --- C oss.Vo ⋅ V O ⋅ f sw
3
∆VO =
IO
ωC O
VO
( 18 )
P MOSFET = P on + P turn-off + P disch arg e
( 19 )
And the MOSFET gate drive resistor is determined by (20).
V Omax
16V
R g > ---------------- = ------------------ = 32Ω
I Omax 500mA
( 20 )
Figure 10. Diode current and output voltage waveform
6
©2001 Fairchild Semiconductor Corporation
APPLICATION NOTE
AN4107
Diode average current can be calculated by (21). The total
diode loss can be calculated by (22) and then a diode can be
selected considering diode thermal characteristic.
R in2
V PIN3 = V in ( peak_max ) ⋅ ---------------------------R in1 + R in2
= V in ( peak_max ) ⋅ G in ( max ) < 3.8V
( 21 )
I Davg = I O ( max )
( 22 )
P Diode = V f I Davg
3-2. Control circuit design
1) Output voltage sensing resistor and feedback loop design
R1 is determined by the maximum output over voltage,
∆Vovp and R2 is determined by (23).
Calculate the pin 3 voltage at the lowest line using Gin(max)
by (30). Then the current sense resistor is determined by
(31), (32) and (34). Once the current sense resistor is
determined, then the minimum line voltage sensing gain,
Gin(max) is determined by (31).
R in2
V O ( m ) = K ⋅ V in ( peak_min ) ⋅ -------------------------------- ∆Vm2 ( max )
R in1 + R in2
V O – 2.5
R1
∆V OVP
------ = --------------------- ,R 1 = ----------------2.5
R2
40µA
2.5R1
,R 2 = -------------------V O – 2.5
ηV
in ( peak_min )
4 ⋅ V O I O ( max )
⋅ 2.5 V ⋅ --------------------------------------------
The feedback loop bandwidth must be narrower than 20Hz
for the PFC application. Therefore a capacitor is connected
between INV and EA_OUT to eliminate the 120Hz ripple
voltage by 40dB. The error amp compensation capacitor can
be calculated by (24). To improve the power factor, Ccomp
must be increased than the calculated value. And to improve
the system response, Ccomp must be lowered than the
calculated value.
1
C comp = ----------------------------------------------------0.01 ⋅ 2π ⋅ 120Hz ⋅ R 1
( 24 )
2) Zero current detection resistor design
Idet current should be less than 3mA, therefore zero current
detection resistor is determined by (25).
N aux ⋅ V O
R idet > ------------------------N P ⋅ 3mA
3) Start-up circuit design
To start up the FAN7527, the start-up current must be
supplied through a start-up resistor. The resistor value is
calculated by (26) and (27). The start-up capacitor must
supply IC operating current before the auxiliary winding
supplies IC operating current maintaining Vcc voltage
higher than the UVLO voltage. Therefore the start up
capacitor is designed by (28).
2
P Rst
V in ( rms_max )
= -------------------------------- ≤ 0.5W
R ST
I dcc
C ST ≥ ------------------------------------------------2π ⋅ f ac ⋅ HY ( ST )min
( 26 )
( 27 )
( 28 )
4) Line voltage sense resistor and current sense resistor
design
The maximum line voltage sensing gain is determined by
(29) at the highest line.
©2001 Fairchild Semiconductor Corporation
(30)
R in2
VO( m)
R semse < ------------------------------------- = K ⋅ Vin ( peak_min ) ⋅ -------------------------------R in1 + R in2
I L ( peak_max )
( 23 )
V in ( peak_min ) – V th ( st )max
R ST ≤ --------------------------------------------------------------I STmax
( 29 )
(31)
ηV
in ( peak_min )
1.8V
R sense < ------------------------------------- = 1.8V -------------------------------------------4 ⋅ V O I O ( max )
I
L ( peak_max )
( 32 )
 V O I O ( max )  2
P Rsense = 2 ⋅  -------------------------------------------- ⋅ R sense < 1W
 ηV in ( peak_min )
( 33 )
2
ηV
in ( peak_min )
1W 
R sense < --------- ⋅  --------------------------------------------
2  V O I O ( max ) 
( 34 )
And attach 1nF capacitor in parallel with R2 to reduce the
switching ripple voltage.
4. Design Example
A 100W converter is designed to illustrate the design procedure. The system parameters are as follows.
•
•
•
•
•
•
•
•
•
•
Maximum output power : 100W
Input voltage range : 85Vrms~265Vrms
Output voltage
: 400V
AC line frequency : 60Hz
PFC efficiency
: 90%
Minimum switching frequency : 34kHz
Input displacement factor(IDF) : 0.98
Input capacitor ripple voltage : 24V
Output voltage ripple : 8V
OVP set voltage : 450V
4-1. Inductor design
The boost inductor is determined by (6). Calculate it at both
the lowest line and the highest line and choose the lower
value. The calculated value is 586uH. To get the calculate
inductor value, EI3026 core is used and the primary winding
is 62 turns. The air gap is 0.586mm at both legs of the EI
core. The auxiliary winding is determined by (7) and the
auxiliary winding is 5 turns.
4-2. Input capacitor design
The minimum input capacitance is determined by the input
voltage ripple specification. The calculated minimum input
7
AN4107
APPLICATION NOTE
capacitor value is 0.56uF. And the maximum input
capacitance is restricted by IDF. The calculated value is
0.76uF. The selected value is 0.67uF for the input
capacitor(sum of all capacitors connected to the input).
4-6. Zero current detection resistor design
4-3. Output capacitor design
The maximum start-up resistor is 1 MΩ and the minimum is
140kΩ by (26)~(27). Our selection is 150kΩ. And the
start-up capacitance must be larger than 10.6uF by (28). The
selected value is 47uF.
The calculate value is 430Ω and the selected value is 22kΩ.
4-7. Start-up circuit design
The minimum output capacitor is determined by (14) and the
calculated value is 83uF. The selected value is 100uF
capacitor.
4-8. Line voltage sense resistor and current
sense resistor design
4-4. MOSFET and diode selection
By (15)~(19), 500V/6A MOSFET FQP6N50 is selected and
by (21)~(23), and 1000V/1A diode BYV26E is selected by
(21)~(22).
The maximum input voltage sensing gain is determined by
(29). Using the calculated value, the current sense resistance
is determined by (31), (32) and (34). The maximum current
sense resistance is 0.48Ω and the selected value is 0.2Ω.
Then the minimum input voltage sensing gain is determined
by (30). If we choose the input voltage sense bottom resistor
to be 18kΩ then the maximum input voltage sense upper
resistance and the minimum input voltage sense upper
resistance can be obtained from Gin(min) and Gin(max) .
The selected value is 2.7MΩ.
Fig. 11 shows the designed application circuit diagram and
table 1 shows the 100W demo board components list.
4-5. Output voltage sense resistor and
feedback loop design
The upper output voltage sense resistor is 1.2MΩ and the
bottom output voltage sense resistor is 7kΩ plus 10kΩ
variable resistor. A variable resistor is used to adjust the
output voltage. The error amp compensation capacitance
must be larger than 0.11uF by (24). Therefore 0.33uF
capacitor is used.
T1
D2
BD1
C5
R3
R4
R5
R8
R6
D6
NTC
Q1
R9
Idet
4
CS
MULT
3
1
C1
2
INV
EA_OUT
FAN7527
LF1
R10
C2
C8
5
6
OUT
C6
GND
8
C4
Vcc
C3
7
R1
V1
F1
R2
C9
C7
R7
VR1
AC INPUT
Figure 11. Application circuit diagram
8
©2001 Fairchild Semiconductor Corporation
APPLICATION NOTE
AN4107
Table 1: 100W demo board part list
Part#
Value
Note
Part#
Fuse
F1
250V/3A
471
-
-
NTC
RT1
10D-9
Note
Capacitor
Varistor
V1
Value
-
Resistor
C1
47nF
275Vac
C2
150nF
275Vac
C3,C4
2200pF
3000V
C5
0.47nF
630V
C6
47nF
35V
C7
0.33nF
MLCC
R1
2.7MΩ
1/4W
C8
100nF
450V
R2
18kΩ
1/4W
C9
102
Ceramic
R3
150kΩ
1W
R4
100Ω
1/4W
BD1
660(600V/6A)
Bridge Diode
R5
22kΩ
1/4W
D1
1N4148
-
R6
47Ω
1/4W
D2
BYV26E
1000V/1A
R7
0.2Ω
1W
R8
1.2MΩ
1/4W
R9
7kΩ
1/4W
R10
500kΩ
1/4W
VR1
103
-
IC
IC1
©2001 Fairchild Semiconductor Corporation
FAN7527
-
Diode
Line Filter
LF1
45mH
-
Inductor
T1
590uH(62T : 5T)
EI3026
MOSFET
Q1
FQPF6N50
500V/6A
-
-
-
9
AN4107
APPLICATION NOTE
Table 2: 150W demo board part list
Part#
Value
Note
Part#
Fuse
F1
250V/3A
471
-
-
NTC
RT1
10D-9
-
Resistor
C1
330nF
275Vac
C2
330nF
275Vac
C3,C4
2200pF
3000V
C5
0.68nF
630V
C6
47nF
35V
C7
1nF
MLCC
R1
2.2MΩ
1/4W
C8
150nF
450V
R2
20kΩ
1/4W
C9
102
Ceramic
R3
150kΩ
1W
R4
100Ω
1/4W
BD1
660(600V/6A)
Bridge Diode
R5
22kΩ
1/4W
D1
1N4148
-
R6
47Ω
1/4W
D2
SUF15J
600V/1.5A
R7
0.2Ω
1W
R8
1.2MΩ
1/4W
R9
7kΩ
1/4W
R10
500kΩ
1/4W
VR1
103
-
IC
IC1
10
Note
Capacitor
Varistor
V1
Value
FAN7527
-
Diode
Line Filter
LF1
45mH
-
Inductor
T1
500uH(83T:5T)
MPP Core
MOSFET
Q1
FQA9N50
500V/9A
-
-
-
©2001 Fairchild Semiconductor Corporation
APPLICATION NOTE
AN4107
Table 3: 200W demo board part list
Part#
Value
Note
Part#
Fuse
F1
250V/3A
471
-
-
NTC
RT1
10D-9
Note
Capacitor
Varistor
V1
Value
-
Resistor
C1
330nF
275Vac
C2
330nF
275Vac
C3,C4
2200pF
3000V
C5
0.68nF
630V
C6
47nF
35V
C7
1nF
MLCC
R1
2.2MΩ
1/4W
C8
220nF
450V
R2
22kΩ
1/4W
C9
102
Ceramic
R3
150kΩ
1W
R4
100Ω
1/4W
BD1
660(600V/6A)
Bridge Diode
R5
22kΩ
1/4W
D1
1N4148
-
R6
47Ω
1/4W
D2
SUF15J
600V/1.5A
R7
0.1Ω
1W
R8
1.2MΩ
1/4W
R9
7kΩ
1/4W
R10
500kΩ
1/4W
VR1
103
-
IC
IC1
©2001 Fairchild Semiconductor Corporation
FAN7527
-
Diode
Line Filter
LF1
45mH
-
Inductor
T1
400uH(74T:5T)
MPP Core
MOSFET
Q1
FQA13N50
500V/13A
-
-
-
11
AN4107
APPLICATION NOTE
Nomenclature
IL(peak) (t) : inductor current peak value during one switching
cycle
fSW : switching frequency
IL(peak) : inductor current peak value during one AC line
cycle
fSW(min) : minimum switching frequency
IL(peak_max) : maximum inductor current peak value
IL (t) : inductor current
ID : boost diode current
Iin (t) : input current
Iin (peak) : input current peak value
Iin (peak_max) : maximum of the input current peak value
Iin (rms) : input current RMS value
IQrms : MOSFET rms current
IDrms : diode rms current
IDavg : diode average current
IO : output current
IO (max) : maximum output current
Vin (t) : input voltage
∆Vin (max) : maximum input voltage ripple
Vin (peak) : input voltage peak value
Vin (peak_max) : maximum input voltage peak value
Vin (peak_min) : minimum input voltage peak value
Vin (rms) : input voltage RMS value
Vin (rms_max) : maximum input voltage RMS value
Vin (rms_min) : minimum input voltage RMS value
fSW(max) : maximum switching frequency
L : boost inductance
CO : output capacitance
Cin : input capacitance
η : converter efficiency
Naux : auxiliary winding turn number
NP : boost inductor turn number
Ccomp : compensation capacitance
Ridet : zero current detection resistance
RST : start up resistance
R1 : output voltage divider top resistance
R2 : output voltage divider bottom resistance
Rin1 : input voltage divider top resistance
Rin2 : input voltage divider bottom resistance
Rsense : current sense resistance
ISTmax : maximum start up supply current
CST : start up capacitance
HY(ST)min : minimum UVLO hysteresis
K : multiplier gain
Gin (min) : minimum input voltage sense gain
Gin (max) : maximum input voltage sense gain
Vin (LL) : low line rms input voltage
Vin (HL) : high line rms input voltage
VO : output voltage
∆VO (max) : maximum output voltage ripple
∆VOVP : maximum output over voltage
PO : output power
PO(max) : maximum output power
Pin : input power
η : converter efficiency
ton : switch on time
toff : switch off time
tf : MOSFET current falling time
TS : switching period
fac : AC line frequency
ω : AC line angular frequency
12
©2001 Fairchild Semiconductor Corporation
APPLICATION NOTE
AN4107
©2001 Fairchild Semiconductor Corporation
13
AN4107
APPLICATION NOTE
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPROATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
10/11/01 0.0m 002
Stock#ANxxxxxxxxx
 2001 Fairchild Semiconductor Corporation