ESDA14V2-4BF1 ® QUAD BIDIRECTIONAL TRANSIL™ ARRAY FOR ESD PROTECTION ASD™ APPLICATION Where transient overvoltage protection in ESD sensitive equipment is required, such as : ■ Computers Printers ■ Communication systems and cellular phones ■ Video equipment This device is particularly adapted to the protection of symmetrical signals. ■ Flip-Chip (5 bumps) DESCRIPTION The ESDA14V2-4BF1 is a monolithic array designed to protect up to 4 lines in a bidirectional way against ESD transients. FUNCTIONAL DIAGRAM The device is ideal for situations where board A3 A1 C1 C3 space saving is requested. FEATURES 4 Bidirectional Transil™ functions ■ ESD Protection: IEC61000-4-2 level 4 ■ Stand off voltage: 12 V MIN. ■ Low leakage current < 1 µA ■ 50W Peak pulse power (8/20µs) ■ BENEFITS High ESD protection level ■ High integration ■ Suitable for high density boards ■ GND PIN CONFIGURATION (Ball Side) 3 2 1 COMPLIES WITH THE FOLLOWING STANDARDS: A - IEC61000-4-2: 15kV (air discharge) 8kV (contact discharge) - MIL STD 883E- Method 3015-7: class3 25kV (human body model) Order Codes Part Number ESDA14V2-4BF1 May 2004 B C Marking EA REV. 2 1/9 ESDA14V2-4BF1 ABSOLUTE MAXIMUM RATING (Tamb = 25°C) Symbol VPP PPP Tj Tstg Parameter Value Unit ± 25 ± 15 ±8 kV Peak pulse power (8/20µs) 50 W Junction temperature 125 °C -55 to +150 °C 260 °C -40 to +125 °C ESD discharge MIL STD 883E - Method 3015-7 IEC61000-4-2 air discharge IEC61000-4-2 contact discharge Storage temperature range TL Lead solder temperature (10 seconds duration) Top Operating temperature range ELECTRICAL CHARACTERISTICS (Tamb = 25°C) Symbol Parameter VRM Stand-off voltage VBR Breakdown voltage VCL Clamping voltage IRM Leakage current IPP Peak pulse current VBR VCL Slope = 1/Rd Capacitance Rd Dynamic resistance @ IR VBR ESDA14V2-4BF1 V RM min. V I RM C Part Number I max. IRM @ VRM max. V V mA 14.2 18 1 µA V 1 12 0.1 3 I PP Rd αT C typ. max. max. note 1 note 2 0V bias Ω -4 10 /°C pF 3.2 10 15 Note 1: Square pulse, IPP = 3A, tp = 2.5µs. Note 2: ∆VBR = αT (Tamb -25°C) x VBR (25°C) 2/9 ® ESDA14V2-4BF1 Fig. 1: Clamping voltage versus peak pulse current (Tj initial = 25°C) (Rectangular waveform). Fig. 2: Capacitance versus reverse applied voltage (typical values). C(pF) IPP(A) 10.0 14 tp = 2.5µs F=1MHz VOSC=30mVRMS Tj=25°C 12 10 8 1.0 6 4 2 VCL(V) VR(V) 0.1 0 0 10 20 30 40 50 60 0 2 4 6 8 10 12 14 Fig. 3: Relative variation of leakage current versus junction temperature (typical values). IR[Tj] / IR[Tj=25°C] 1000 100 10 Tj(°C) 1 25 50 75 100 125 APPLICATION EXAMPLE Connector A1 A3 C1 C3 IC to be protected B2 ® 3/9 ESDA14V2-4BF1 TECHNICAL INFORMATION 1. ESD protection by ESDA14V2-4BF1 With the focus of lowering the operation levels, the problem of malfunction caused by the environment is critical. Electrostatic discharge (ESD) is a major cause of failure in electronic systems. As a transient voltage suppressor, ESDA14V2-4BF1 is an ideal choice for ESD protection by suppressing ESD events. It is capable of clamping the incoming transient to a low enough level such that any damage is prevented on the device protected by ESDA14V2-4BF1. ESDA14V2-4BF1 serves as a parallel protection elements, connected between the signal line and ground. As the transient rises above the operating voltage of the device, the ESDA14V2-4BF1 becomes a low impedance path diverting the transient current to ground. The clamping voltage is given by the following formula: VCL = VBR + Rd.IPP As shown in figure A1, the ESD strikes are clamped by the transient voltage suppressor. Fig. A1: ESD clamping behavior. Rg Ip Rd V(i/o) Vg R load VBR ESD Surge ESDA14V2-4BF1 Device to be protected To have a good approximation of the remaining voltages at both Vi/o side, we provide the typical dynamical resistance value Rd. By taking into account the following hypothesis: R G > R d ""and""R load > R d we have: VG V ( i ⁄ o ) = V BR + R d × -------RG The results of the calculation done VG = 8kV, RG = 330Ω (IEC61000-4-2 standard), VBR = 14.2V (typ.) and Rd = 3.2Ω (typ.) give: V ( i ⁄ o ) = 91.8 Volts This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be a few tenths of volts during a few ns at the Vi/o side. 4/9 ® ESDA14V2-4BF1 Fig. A2: ESD test board. Fig. A3: ESD test condition. TEST BOARD A1, C1, A3 or C3 V(i/o) ® EB14 15 ± 15kV ESD Air discharge V(i/o) B2 The measurements done here after show very clearly (figure A4) the high efficiency of the ESD protection: the clamping voltage V(i/o) becomes very close to VBR (positive way, figure A4a) and -VBR (negative way, figure A4b). Fig. A4: Remaining voltage during ESD surge. V(i/o) V(i/o) a: Response in the positive way ® b: Response in the negative way 5/9 ESDA14V2-4BF1 2. Crosstalk behavior Fig. A5: Crosstalk phenomenon. RG1 Line 1 VG1 α1VG1 + β12VG2 RL1 RG2 Line 2 VG2 RL2 DRIVERS α2VG2 + β21VG1 RECEIVERS The crosstalk phenomena are due to the coupling between 2 lines. Coupling factors ( β12 or β21 ) increase when the gap across lines decreases, particularly in silicon dice. In the example above, the expected signal on load R L2 is α2VG2, in fact the real voltage at this point has got an extra value β21VG2. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few kΩ). Fig. A6: Analog crosstalk test configuration. Fig. A7: Typical analog crosstalk response. Typical crosstalk response of ESDA14V2-4BF1 (A1/A3 line) 0.00 -10.00 -20.00 TEST BOARD Connected to the port1 of the Network Analyser -30.00 A1 -40.00 EB14 15 C3 -50.00 Connected to the port2 of the Network Analyser -60.00 -70.00 -80.00 -90.00 -100.0 100.0k 1.0M 10.0M f/Hz 100.0M 1.0G Figure A6 gives the measurement circuit for the analog crosstalk application. In figure A7, the curve shows the effect of the line A1on the line A3. In usual frequency range of analog signals (up to 100 MHz) the effect on disturbed line is less than -30dB. 6/9 ® ESDA14V2-4BF1 Fig. A8: Digital crosstalk test configuration. Fig. A9: Typical digital crosstalk response. A1 0 - 3V Pulse generator f = 5MHz risetime = 3ns unloaded VG1 VG1 rise time: t10-90% = 3ns B2 = GND β21VG1 β21VG1 crosstalk unloaded C3 Figure A8 shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. Figure A9 shows that in such a condition, the impact on the disturbed line is less than 5 mV peak to peak. No data disturbance was noted on the concerned line. The measurements performed with falling edges give an impact within the same range. Fig. A10: Aplac model. 1.2pF 1.2pF 100m 100m D02_r BV = 16 IBV = 1m CJO = 200p M = 0.3333 RS = 1 VJ = 0.6 TT = 100n ® C3 C1 A3 A1 1.2pF 100m 1.2pF 100m D02_r D02_f BV = 16 IBV = 1m CJO = 10.4p M = 0.3333 RS = 2 VJ = 0.6 TT = 100n B2 B2 50pH 50m 160pH 1.8 7/9 ESDA14V2-4BF1 ORDER CODE ESDA 14V2 - 4 B F 1 Pitch & bump ESD ARRAY VBR min Nb of lines Flip-Chip Bidirectional PACKAGE MECHANICAL DATA 315 ± 50 650 ± 65 49 5 ± 50 1150 ± 50 700 ± 50 1150 ± 50 FOOT PRINT RECOMMENDATIONS MARKING Copper pad Diameter : 250µm recommended , 300µm max Solder mask opening recommendation : 340µm min for 315µm copper pad diameter All dimensions in µm 8/9 ® diam 230 1150 Solder stencil opening : 330µm 200 275 265 Dot, ST logo xx = marking z = back-end plant yww = datecode (y = year ww = week) XXZ YWW 220 40 1150 ® ESDA14V2-4BF1 FLIP-CHIP TAPE AND REEL SPECIFICATION Dot identifying Pin A1 location 1.75 +/- 0.1 Ø 1.5 +/- 0.1 4 +/- 0.1 3.5 +/- 0.1 ST xxz yww ST xxz yww ST xxz yww 8 +/- 0.3 0.73 +/- 0.05 4 +/- 0.1 User direction of unreeling All dimensions in mm ORDERING INFORMATION Part Number ESDA14V2-4VF1 Marking Package Weight Base qty Delivery mode EA Flip Chip 2.1 mg 5000 Tape & reel Note: More packing informations are available in the application notes - AN1235: ''Flip-Chip: Package description and recommandations for use'' - AN1751: "EMI Filters: Recommendations and measurements" REVISION HISTORY Table 1: Revision history Date Revision Description of Changes July-2002 1 First issue 27-May-2004 2 Die clearance optimization Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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