TEA1024/ TEA1124 Zero Voltage Switch with Fixed Ramp Description The monolithic integrated bipolar circuit, TEA1024/ TEA1124 is a zero voltage switch for triac control in domestic equipments. It offers not only the control of a triac in zero crossing mode but also the possibility of power control. This is why the IC contains a mains synchronized ramp generator with 640 ms (1280 ms) duration (50 Hz). It is suitable for a typical load of 750 W (1000 W) meeting the Flicker Standard. (values in brackets relate to TEA1124.) Features D D D D D D D D D D Direct supply from the mains Definite IC switching characteristics Very few external components Full wave drive – no dc component in the load circuit Simple power control Integrated ramp generator Reference voltage variable by external resistance Pulse position optimization Current consumption ≤ 1.5 mA Package: DIP8 Output short circuit protected Block Diagram 95 10871 D1 R2 (Rsync) 390 kW 7 Ramp generator TEA 1024 – 640 ms TEA 1124 – 1280 ms 1 56 kW R1 22 kW/ 2W max. C1 Supply TIC 236N 5 Pulse amplifier – 2 3 43 kW NC 100 mF 16 V V M= 230 V ~ 6 Sync. logic + min. 100 kW Load 1000 W 4 Comparator Protection L 1N4007 RG MT2 MT1 68 W 8 NC N Figure 1. Typical block diagram – open loop power control TELEFUNKEN Semiconductors Rev. A1, 24-May-96 1 (8) TEA1024/ TEA1124 Power Supply and its Limitations Full-Wave Logic The voltage limitation contained in the IC allows it to be powered from mains via series resistance R1 and recti– fying diode D1 between Pin 6 (+ Pol/ ) and Pin 4 (–VS). The capacitor C1 smooths the supply voltage (see figure 1). The full-wave logic ensures that only pairs of pulses can be released, and that these always begin with the positive dv/dt. The load is thus switched on for a minimum of one complete mains cycle. This means that the triac receives a minimum of two driving pulses, so that the unwanted d.c. component in the load circuit is definitely eliminated. An internal temperature-compensated limiting circuit protects the module from random peaks of voltage on the mains, and delivers a defined reference voltage during the negative half-cycle. Pulse Amplifier ă Synchronization The pulse amplifier connected to the output of the fullwave logic circuit, is proof against continuos short-circuits, and delivers negative output pulses of typ. 75 mA, via an integrated limiting resistance, to Pin 5. Ramp Generator (Figures 3, 4) Ramp voltage which is generated in the IC is available not only at reference Pin 1, but also at the non-inverted input of the comparator. The current sink which is controlled by D/A converter influences the internal reference voltage at Pin 1 specified by voltage divider. The current sink is turned-off in the reset state of the D/A converter so that the voltage at Pin 1 is primarily specified via the internal voltage divider (ramp starting voltage). Figure 2. Pulse position optimization The logic function is synchronized by means of a separate resistance R2 connected between Pin 7 and phase (voltage-synchronization). The width of the pulse can be varied between wide limits by choice of Rsync. The larger the value chosen, the wider the output pulse is on Pin 5. Automatic optimization of the phase of the pulse is necessary, since the latching current of the triac exceeds the steady current by a factor of 3. The phase of the pulse is chosen so that ca. 1/3 of the pulse width appears before the transition through null and 2/3 after it (see electrical characteristics and figure 2). In order to avoid phase-clipping after the switch-on the first third of the first pulse is automatically suppressed. 2 (8) In the maximum state of the 4 stage (5 stage – TEA1124) D/A converter, the current sink overtakes the maximum current, whereby the ramp’s final (end) voltage has reached. External resistance Rx, Ry shown in figure 4 are in position to influence the initial ramp voltage as well as the ramp amplitude. If the external resistances ratio Rx, Ry is the same as that of the internal ratio, the ramp voltage at the beginning remains maintained (constant), only the amplitude is compressed. t V 1 –1.3 V 2.2 V –3.8 V T= 640 ms (T= 1280 ms) 16 stage ramp 95 11410 Figure 3. Ramp diagram without external circuit TELEFUNKEN Semiconductors Rev. A1, 24-May-96 TEA1024/ TEA1124 2 – Protection GND + 6 50 kW Rx 4 stage ripple counter 1 D/A converter Ry 150 kW A D 4 –VS 23 22 21 20 Period 20 ms (40 ms) 7 Divider 1:2 (1:4) Sync (50 Hz) Current sink 95 11411 Figure 4. Principle diagram – Generation and evaluation of ramp Period Firing Pulse Width (Figures 6, 7) 1. The time required for one complete cycle of a regular. repeating signal, function, or series of emends. 2. The tune between two consecutive transients of the pointer or indicating means of an electrical indicating instrument in the same disdain the rest position. Something called periodic fine. It depends on the latching current as well as on the load current of the used triacs. Comparator The comparison of set value and measured value is carried out via the two comparator inputs Pin 1 and Pin 2. Here Pin 2 is the inverting input and has a circuit protecting it against interference spikes. Figure 5 shows the protective circuit of the comparator. Pin 1 is the noninverting input. 1 Ramp generator 6 t p [s] + 4 3p f arcsin Ǹ2 IL VM P whereas IL[A] = Latching current of the triac VM[V]= Mains voltage, effective P[W] = Power load f[1/s] = Mains frequency Firing pulse width is specified through the zero cross over identification which can be influenced by the sync. resistance. R sync [W] +V M Ǹ2 sin ǒ 2 3 2.5 Ǔ w 10 t p – 0.6 –5 –1.4 10 3 where tp [s] = required ignition pulse width GND R Z T 2 + – 95 11412 Figure 5. Protective circuit of the comparator TELEFUNKEN Semiconductors Rev. A1, 24-May-96 3 (8) TEA1024/ TEA1124 Supply Voltage 10.00 Vmains = 230 V∼ Due to higher trigger sensitivity of the triac it is supplied with negative signal. It can be supplied via diode and series resistance from the negative half wave of the mains. An internal parallel controller limits the voltage between Pin 5 and 7 to a typical value of 6.55 V. t p ( ms ) 1.00 Dimensioning of the Series Resistance R1 (Figures 8, 9) IL ( mA) 0.10 200 100 0.01 10 100 1000 10000 I tot VMains=230V S P VM VS Itot Ix Figure 6. 2.5 Mmin Smax –65 tot P(W) 96 11939 + 0.85 V 2 –I V +I )I )I R 1max 50 X P(R 1) X W + (V 2–RV ) M S 2 1 = Mains supply = Limiting voltage of the IC = Total current requirement = Current requirement for external circuit 50 2 VMains=230V 1.5 R 1 ( kW ) R 2 ( MW ) 40 1 X 30 20 0.5 10 0 0 200 95 11 400 600 tp ( ms ) 800 1000 0 0 3 6 Figure 7. 6 I p [A] I Gmax T + W 4 (8) 12 15 X 4 3 2 tp whereas VG[V]= Gate voltage of the triac IG[A]= Max. gate current IP[A] = Average gate current requirement tP[s] = Ignition pulse width T[s] = Duration (of mains frequency) VMains=230V 5 PR1 ( W ) The necessary ignition current depends on the specified triac. With the help of a resistance, it is possible to limit its value: [ 15 Figure 8. Ignition (Firing) Current R Gmax [W] 12 Itot ( mA ) 95 10114 5.7 V – V Gmax –25 I Gmax 9 1 0 0 95 10116 3 6 9 Itot ( mA ) Figure 9. TELEFUNKEN Semiconductors Rev. A1, 24-May-96 TEA1024/ TEA1124 Absolute Maximum Ratings Reference point Pin 6 Parameters Current consumption t ≤ 10 ms Pin 4 Sync. current t ≤ 10 ms Pin 7 Comparator input current Input voltages Pin 2 Pin 1,4,5 Pin 5 Symbol –IS is ISync iSync II –VI +VI Value 30 150 5 40 1 ≤ VS ≤ 0.5 Unit mA Ptot mW Tj Tamb Tstg 400 125 125 0 to 100 –40 to + 125 Symbol RthJA Maximum 200 Unit K/W " mA mA V Power dissipation Tamb = 45°C Tamb = 100°C Junction temperature Ambient temperature range Storage temperature range °C °C °C Thermal Resistance Parameters Junction ambient Electrical Characteristics Supply voltage –VS = 5.6 V, Tamb = 25°C, f = 50 Hz, reference point Pin 6, unless otherwise specified Parameters Supply voltage limitation Current consumption Synchronization Voltage limitation Synchronization current Zero cross detection Comparator, figure 5 Input zero voltage Input quiescent current Common mode input range Test Conditions / Pins –I4 = 1 mA Pin 4 Pos. half, cycle Pin 4 Zero cross over (Pin 5 open) Pin 4 neg. half cycle Pin 4 Pin 7 ±I7 = 1 mA TELEFUNKEN Semiconductors Rev. A1, 24-May-96 Symbol –VS –IS Min 5.7 Max 7.4 1 Unit V mA 1 1.8 –IS –IS "V "I "I I Sync 1.0 0.15 V10 IB –VIC 1.8 10 mV 1 1 (VS–1.6) V mA mA 25 Sync Pin 1, 2 Pin 2 Pin 1, 2 Typ mA V 5 (8) TEA1024/ TEA1124 Parameters Test Conditions / Pins Ramp generator, figures 3, 4 Pin 1 TEA1024 Period TEA1124 Step number Initial voltage Final voltage Internal reference Temperature coefficient of internal reference Pulse amplifier Output pulse current Output pulse width Symbol Min Typ 1.2 3.3 640 1280 16 1.4 3.6 T n –V1 –V1 Max Unit ms 1.6 3.9 V V V ǒ) Ǔ V S 2.5% 4–7.5% "TC 1.2 Ref mV/K Pin 5 VG ≤ 1.5 V VSync = 230 V , R2 = 220 kW –IO t0 t1 t2 X 50 100 mA ms 33 65 110 Applications 95 11416 D1 390 kW/ 0.5 W R2 (Rsync) 7 1 Ramp generator TEA 1024 – 640 ms TEA 1124 –1280 ms R1 22 kW/ 2W R(30) = 8 kW R(10) = 20 kW Protection 100 mF 16 V Supply TIC 236N 5 Pulse amplifier 3 NC C1 VM = 230 V ~ 6 Sync. logic + – 2 Load 0.7...1.5 kW 4 Comparator NTC / M87 B value = 3474 R(25) = 10 kW L 1N4007 MT2 MT1 RG 68 W 8 NC N Figure 10. Simple temperature regulation with maximum proportional range 6 (8) TELEFUNKEN Semiconductors Rev. A1, 24-May-96 TEA1024/ TEA1124 95 11417 D1 R2 (Rsync) 390 kW/ 0.5 W R4 33 kW R6 7 R1 22 kW/ 2W Ramp generator TEA1024 – 640 ms TEA1124 –1280 ms Rp Sync. logic Supply Load 0.7...1.5 kW C1 4 10 kW 1 L 1N4007 100 mF 16 V 6 TIC 236N V M= 230 V ~ MT2 50 kW Comparator NTC / M87 B value = 3474 R(25) = 10 kW R(30) = 8 kW 5 + Protection Pulse amplifier – R12 2 2.2 kW 3 NC RG MT1 68 W 8 NC R(10) = 20 kW N Figure 11. Temperature regulation with proportional range, 10 to 30 °C/ 640 ms ramp cycle Dimensions in mm Package: DIP8 TELEFUNKEN Semiconductors Rev. A1, 24-May-96 7 (8) TEA1024/ TEA1124 Ozone Depleting Substances Policy Statement It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2831, Fax number: 49 ( 0 ) 7131 67 2423 8 (8) TELEFUNKEN Semiconductors Rev. A1, 24-May-96