UAA145 Phase Control Circuit for Industrial Applications Description circuits to be drastically reduced. The versatility of the device is further enhanced by the provision of a large number of pins giving access to internal circuit points. Features Applications D Separate pulse output synchronized by mains D Industrial power control D Silicon controlled rectifier Gm bH The UAA145 is a bipolar integrated circuit, designed to provide phase control for industrial applications. It permits the number of components in thyristor drive half wave D Output pulse-width is freely adjustable nt s D Phase angle variable from >0° to <180° D High-impedance phase shift input Package: DIP16 (special case) D Less than 3° pulse symmetry between two half-cycles or phase of different integrated circuits om po ne D Output pulse blocking Block Diagram 9 6 Ad ro nic C Voltage synchronisation Ramp generator Comparator 7 S Pulse inhibit R Memory 16 PHW Channel selection Puls generator 10 Pos. / Neg. half wave 14 NHW Supply –V Ref 15 +15 –15 13 3 1 8 11 2 PHW = Positive half wave NHW = Negative half wave 95 11298 Figure 1. Block diagram TELEFUNKEN Semiconductors Rev. A1, 29-May-96 1 (11) UAA145 Ramp Generator The operation of the circuit is best explained with the help of the block diagram shown in figure 1. It comprises a synchronizing stage, ramp generator, voltage com-parator, pulse generator, channel selecting stage and two output amplifiers. The circuit diagram in figure 2 also shows the external components and terminal connections necessary for operation of the circuit. As can be seen from figure 2, the circuit requires two supply rails i.e. a +15 V and a –15 V. The positive voltage is applied directly to Pin 1, while an external series resistor in each line is used to connect the negative voltage Pin 13 and Pin 15. In the following circuit description each section of the block diagrams is discussed separately. Transistor T7 amplifies the zero-crossover switching pulses. During the sync process capacitor CS at Pin 7 is charged to the operating voltage of reference diode Z4, i.e., to approximately 8.5 V, the charging time being always less than the duration of the sync pulse. The capacitor discharges via resistor RS during each half-cycle. The discharge voltage is of the same magnitude as the charge voltage, and is determined by Z3. To ensure an approximately linear ramp waveform, the voltage is allowed to decay up to ca. 0.7 CsRs. Because Z-diodes Z3 and Z4 have the same temperature characteristics, the timing of the ramp zero crossover point in relation to that of the sync. pulse is constant, and consequently the pulse phasing rear limit is also very stable. W Ad ro nic C m om po ne Pin 9 is connected, via a voltage divider (22 k and Rp), to the ac line (sync. signal source). A pulse is generated during each zero crossover of the sync. input. The pulse duration depends on the resistance Rp and has a value of 50 to 100 s. (figure 2). In addition to providing zero voltage switching pulses this section of the circuit generates blocking signals for use in the channel selecting stage. nt s Synchronization Stage Gm bH General Description Figure 2. Block diagram and basic circuit 2 (11) TELEFUNKEN Semiconductors Rev. A1, 29-May-96 UAA145 Gm bH om po ne In the (voltage) comparator stage, the ramp voltage is compared with the shift voltage Vö applied to Pin 8. The comparator switches whenever the instantaneous ramp voltage is the same as the shift voltage (corresponding to the desired phase angle), thereby causing the memory to be set, i.e. the integrated thyristor in memory is to be turned on. The time delay between the signal input and the comparator output signal is proportional to the required phase angle. Design of the circuit is such that the memory content is reset only during the instant of zero crossover, the reset signal always overriding the set signal. This effectively prevents the generation of additional output pulses and causes any pulse already started to be immediately inhibited on application of an inhibit signal to Pin 6. The memory content can also be reset via Pin 6. Thus the memory ensures that any noise (negative voltage transients) superimposed on the shift signal at Pin 8 cannot give rise to the generation of multiple pulses during the half-cycle. pulse can be monitored by means of an oscilloscope applied to Pin 6. The Pin 11 pulse waveform is that at Ct, and the waveforms at Pin 10 and Pin 11 are those of the output pulses. nt s Comparator (Differential Amplifier) and Memory Pulse Generator (Monostable Multivibrator) The memory setting pulse also triggers a monostable stage. The duration of the pulse produced by the monostable is determined by Ct and Rt, connected to Pin 2 and Pin 11. Channel Selection and Output Amplifier Ad ro nic C A pulse is produced at either output Pin 10 or Pin 14 if transistor T20 or T19 respectively is cut-off. The pulses derived from the pulse generator are applied to the output transistors via OR gates controlled by the half-cycle signals derived from the sync stage. During the positive half-cycle no signal is applied from the sync stage to T19 so that an output pulse is produced at Pin 14. The same is valid for Pin 10 during the negative half-cycle. Pulse Diagram Figure 3 shows the pulse voltage waveforms measured at various points of the circuit, all signals being time referenced to the sync signal shown at the top. The input circuit limits any signal applied to 0.8 V at Pin 9. The sync pulse can be measured at Pin 16, whereas the ramp waveform and the pulse phasing rear limit (öh) are at Pin 7. The time relationship between the shift voltage applied to Pin 8 and the ramp waveform is indicated by dotted lines. A pulse trigger signal is produced whenever the ramp crosses the shift level. The memory control " TELEFUNKEN Semiconductors Rev. A1, 29-May-96 Figure 3. Pulse diagram Influence of External Components, Syncronization Time An ideal 0 to 180_ shift range and perfect half-cycle pulse timing symmetry are attained, if the sync pulse duration is kept short. However, there is a lower pulse duration limit, which is governed by the time required to charge capacitor Cs (figure 5). As can be seen, it takes about 35 ms to charge Cs. The sync time can be altered by adjustment of Rp, the relationship between Rp and the sync time being shown in figure 6. The ratio of R and Rp determines the width of internal sync pulse, tsync, at Pin 16. The pulse shape is valid only for sync pulse of 230 V∼. The lower the sync voltage, longer is the sync pulse. A minimum of 50 ms (max. 200 ms) input sync pulse is required for a pulse symmetry of Dö 3°. x" 3 (11) UAA145 95 11299 600 vsync X Sync. Time VSync.=230V R=22kW v14 v10 400 2 300 Pin16 200 v10,14 öv ö öh t 100 a ö 0 0.1 95 10106 Figure 4. Pulse phasing tSync. Gm bH t tSync. ( ms ) 500 1 10 100 1000 RP ( kW ) Figure 6. P7 20mA/div. –0mA –0V 95 10105 Figure 5. Charging time 10 ms/div. Pulse Phasing Limits Ad ro nic C The pulse phasing front limit is determined by limiting the maximum shift voltage applied to Pin 8 which is thus adjustable by external circuitry. This can be done by connecting a Z-diode between Pin 8 and Pin 3. The pulse phasing rear limit, öh, is the residual phase angle of the output pulses when the shift voltage Vö is zero. Since öh coincides with the zero crossover point of the ramp, it can be adjusted by variation of the time constant CsRs (figure 14). Figure 10 shows the pulse phasing rear limit plotted as a function of Rs. Pulse Blocking The output pulses can be blocked via Pin 6, the memory content being erased whenever Pin 6 is connected to +VS (Pin 1). This effectively de-activates the pulse generator; any output pulse in the process of generation is interrupted. Pulse blocking can be accomplished either via relay contacts or a PNP switching transistor (figure 14). 4 (11) The output pulse width can be varied by adjustment of Rt and Ct. In figure 11 pulse width is shown plotted as a function of Rt for Ct = 50 nF. The output pulse always finishes at zero crossover. This means that if there is a minimum pulse width requirement (for example, when the load is inductive) provision must be made for a corresponding pulse phasing rear limit. The output stages are arranged so that the transistors are cut off when a pulse is produced. Consequently, the thyristor trigger pulse current flows via the external load resistors, this current being passed by the transistors during the period when no output pulse is produced. During this period the output voltage drops to the transistor saturation level and is therefore load dependent. Figure 12 shows the relationship between saturation voltage and load current. om po ne P7 2V/div. nt s Output Pulse Width Shift Characteristic In figure 13 the angle of phase shift is shown plotted as a function of the voltage applied to Pin 8 for a pulse phasing rear limit of approximately 0_. Because the ramp waveform is a part of the exponential function, the shift curve is also exponential. The limitation of the shift voltage to approximately 8.5 V is due to the internal Z-diode Z4, which has a voltage spread of 7 to 9 V. The waveforms in figures 7 to 9 show the output pulse phase shift as a function of Vö. It can be seen from the oscillograms, the instants at which pulses are released coincide with the intersections of the ramp and the shift voltage. TELEFUNKEN Semiconductors Rev. A1, 29-May-96 UAA145 P7Ramp 2V/div. 200 Pulse Phasing Rear Limit VB=0, Cs=100nF 120 80 40 95 10107 0 Figure 7. Output pulses phase shift 2 ms/div 0 Gm bH P8 Ref. Voltage 2V/div. 0V V14 20V/div. 0V V10 20V/div. –0V ö h (°) 160 –0mA 40 80 120 W) 160 200 Rs ( k 95 10295 Figure 10. nt s 10 P8 Ref. Voltage 2V/div. P7Ramp 2V/div. Output Pulse Width Ct=50nF 6 om po ne 0V V14 20V/div. t p ( ms ) 8 0V V10 20V/div. 0V 95 10108 4 2 Figure 8. Output pulses phase shift 2 ms/div 0 0 95 10296 40 80 120 W) 160 200 Rt ( k Figure 11. Ad ro nic C P8 Ref. Voltage 2V/div. P7Ramp 2V/div. 0V V14 20V/div. 0V V10 20V/div. 0V 95 10294 Figure 9. Output pulses phase shift 2 ms/div TELEFUNKEN Semiconductors Rev. A1, 29-May-96 5 (11) UAA145 200 0.6 0.5 ö (°) 0.3 120 80 0.2 40 0.1 Shift Characteristics ö h=0, ö =f (V8 ) 0 0 0 10 20 I10, I14 ( mA ) 95 10298 0 40 30 95 10297 om po ne Reference point Pin 3, Tamb = 25°C, unless otherwise specified Pin 1 Pin 8 Reverse voltage, control input Negative supply current Control input pulse current Output currents 6 8 10 V8 ( V ) Pin 11 Pin 13 Pin 15 Pin 9 Symbol VS Vö -Vö –VIR –IS "I sync Value 18 VS1 5 15 25 5 20 Unit V V V V mA mA mA mW mA Pin 11 Pin 10 Pin14 II IO Ad ro nic C Synchronization current 4 Figure 13. Absolute Maximum Ratings Parameters 2 nt s Figure 12. Positive supply voltage Shift voltage Gm bH 0.4 V10 , V14 ( V ) 160 Saturation Output Voltages Ptot 3 20 20 550 Tj Tamb Tstg 125 –25 to +70 –25 to +125 °C °C °C Symbol Value 100 35 Unit K/W Total power dissipation Tamb 70°C Junction temperature Ambient temperature range Storage temperature range x Thermal Resistance Parameters Junction ambient Junction case 6 (11) RthJA RthJC TELEFUNKEN Semiconductors Rev. A1, 29-May-96 UAA145 DC Characteristics VS1 = 13 to 16 V, –IS13 = 15 mA, reference point Pin 3, figure 2, Tamb = 25_C, unless otherwise specified Ct-potential shift current Ct-charging current x CS-charging current VS = VI2 =Vö8 = 13 V VI7 = x VS = VI2 =16 V, VI7 = Vö8 = 0 V, II11 = 50 mA I10 = 2 = 0.3 I14 = 2 = 0.3 AC Characteristics Ad ro nic C Tamb= 25_C, figures 2, 4 and 14 Parameters Rise time Pulse width Pulse phasing difference for two half-waves Inter lC phasing difference Pulse phasing front limit Pulse phasing rear limit II –II Min. 12 7.0 7.0 7.0 Typ. –II Max. 30 9.0 9.0 9.0 10 4.5 10 20 om po ne Output saturation voltage Symbol IS –VZ2 –VZ3 VZ4 Iö Gm bH Input current Test Conditions / Pin VS = 16 V Pin 1 –IS13 = 15 mA Pin 13 Pin 15 –IS15 = 3.5 mA VS = 13 V, V9 = 0V Pin 16 VS = 16 V, Pin 8 Vö8 = 13 V, V7 = 0V, I9 = 0.3 mA VS = VI2 =13 V, VI7 = 3 V, Iö8 = 5 mA, I VS = 13 V, VI2 =VI7 = 0 V Vö8 = nt s Parameters Positive supply current Voltage limitation 62 mA V 0.3 1.0 VOsat 0.3 1.0 Type. Max. 0.5 0.5 4 4 Min. tp tp 0.1 0.1 Dö f = 50 Hz Dö f = 50 Hz, figure 4 f = 50 Hz, figures 4 and 10 ö ö mA mA VOsat Symbol tr mA 30 Test Conditions / Pin Pin 10 Pin 14 Pin 10 Pin 14 f = 50 Hz Unit mA V "3 "3 177 Unit m ms ° ° ° ° Angle of current flow ö = 0 to 177° at Vö8 = 0.2 to 7.5 V, öh = 0°, figures 4 and 13 TELEFUNKEN Semiconductors Rev. A1, 29-May-96 7 (11) nt s Gm bH UAA145 Figure 14. Test circuit for ac characteristics Applications Ad ro nic C om po ne Parallel connection for three-phase current applications Figure 15. Parallel connection for three-phase current applications. For polyphase operation connect all Pins 15 and Pins 16. To ensure good pulse phasing symmetry as well as identical shift characteristics in three-phase applications, when three devices are employed, two parallel connection pins (figure 15) are provided on each device. Besides the supply pins, the input pins 15 and 16 are to be paralleled. If this is done, then all the Z4 and Z3 diodes are connected in parallel so that the reference voltage 8 (11) effective for all three devices becomes that of the Z-diode with the lowest operating voltage. In this way all the CS capacitors are charged and discharged to the same voltage levels. By symmetrical adjustment of the time constants with resistors RS, good pulse phasing symmetry and identical shift characteristics are attained. TELEFUNKEN Semiconductors Rev. A1, 29-May-96 Ad ro nic C om po ne nt s Gm bH UAA145 Figure 16. Speed control with tacho-generator TELEFUNKEN Semiconductors Rev. A1, 29-May-96 9 (11) UAA145 Case: DIP 16 (Special case) Ad ro nic C om po ne nt s Gm bH Dimensions in mm 10 (11) TELEFUNKEN Semiconductors Rev. A1, 29-May-96 UAA145 Ozone Depleting Substances Policy Statement It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to Gm bH 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). nt s The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. om po ne 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. Ad ro nic C TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2831, Fax number: 49 ( 0 ) 7131 67 2423 TELEFUNKEN Semiconductors Rev. A1, 29-May-96 11 (11)