STMICROELECTRONICS TEA7063DP

TEA7063
SPEECH CIRCUIT WITH POWER MANAGEMENT
PRELIMINARY DATA
2/4 WIRES INTERFACE WITH
- double antisidetone network
- AC impedance externally programmable
- Rx output dynamic programmable
- AGC attack-disconnect points programmable
ANTI-CLIPPING/ANTI DISTORTION CIRCUIT
PROGRAMMABLE
DTMF INTERFACE
3.3 VOLTS SUPPLY FOR MICROPROCESSOR OR DIALER
EXTRA CURRENT SUPPLY PROGRAMMABLE FOR LOUD SPEAKER
DC CHARACTERISTIC PROGRAMMABLE
FOR ALL SPECIFICATION
LOW CURRENT OPERATION
DESCRIPTION
The TEA7063 is designed to meet the different
DIP20
SO20
ORDERING NUMBERS:
TEA7063FP
TEA7063DP
worldwide specifications for telephone set in medium and high range equipments.
BLOCK DIAGRAM
January 1994
1/15
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
TEA7063
PIN CONNECTION (Top view)
LONG LINE SIDETONE
1
20
EARPHONE
SHORT LINE SIDETONE
2
19
MICROCONTROLLER POWER SUPPLY
IMPEDANCE
3
18
NOISE FILTER
BUFFER OUTPUT
4
17
V-CAPA
V-REF
5
16
V-LINE
DTMF INPUT
6
15
I SLOPE
MICROPHONE INPUT
7
14
MIC/MIC-EARPHONE MUTE
I-REF
8
13
GND
I START
9
12
CURRENT SUPPLY FOR L.S. AMP
10
11
SOFT-CLIPPING FILTER
SQUEEZING THRESHOLD
D93TL021
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Max. Current DC (steady)
Parameter
150
mA
Max. Voltage AC (steady)
7.5
V
9
V
Max. Current (20ms) ONE SHOT
1
A
Max. Voltage (20ms) ONE SHOT current < 1A
12
V
Max. Voltage AC + DC (steady)
Ptot
Total Power Dissipation
TJ
Junction Temperature
1
W
130
°C
Value
Unit
MAXIMUM OPERATING CONDITION
Symbol
2/15
Parameter
VDC
DC Voltage
7
V
VAC
AC Voltage
2.2
Vp
IDC
DC Current
110
mA
TOP
Temperature Range
-20 to 70
°C
TEA7063
TEST CIRCUIT
R4 = 75
R5 = 5.1K
R6 = 22K
R9 = 100K
R11 = 140K
R12 = 0
R13
R14
R15
R16
R17
R18
= 2.7K
=0
= 140K
= 2.7K
= 1.8K
= 560K
C1
C2
C3
C4
C5
C6
= 47µF
= 4.7µF
= 47µF
= 470nF
= 100µF
= 47pF
C7 = 47pF
C8 = 2.2nF
C9 = 2.2nF
C10 = 150nF
RLL = 150K
RLS = 100K
RST = 330K
3/15
TEA7063
ELECTRICAL CHARACTERISTICS (Tamb = 25°C; f = 1KHz; R9 = 100KΩ; unless otherwise specified)
Symbol
Test Condition
Min.
Typ.
Max.
Unit
VC
Stabilized Voltage (pin 17)
Parameter
IL = 25mA; R9 = 100KΩ
2.25
2.5
2.75
V
Iint
Internal Bias Current (pin 17)
IL = 25mA
IL = 25mA; R9 = 180K
(V16 - R6*Iint +VC)
120
140
105
160
µA
µA
Vref
Reference Voltage
IL = 25mA
1.05
1.2
1.35
V
Iref
Current at Vref
+10
µA
-100
Vmp
Stabilized Supply at pin 19
Icmp
Charging Current at Pin 19
Pin 17 = GND
3.1
Ispm
Static Current at Pin 19
IL = 25mA; R9 = 100KΩ
3.3
3.5
0.6 X
Iline
1.1
IL = 25mA; R9 = 180KΩ
V
mA
1.5
mA
0.85
mA
Internal Consumption
Iea
Supply Current for Parallel
Circuits (pin 12)
IL = 25mA
IL = 75mA
Vmh
Vmb
Mute Microphone (pin 14)
ON
OFF
1.6
0.25
0.8
V
V
Vmh
Vmb
Mute Earphone (pin 14)
ON
OFF
2.7
0.25
2.1
V
V
Imleak
Mute Leakage Current (pin 14)
V14 = 5V
20
µA
GS
AGCS
Tx Gain Long Line
IL = 25mA
41.5
-7
42.5
-6
43.5
-5
dB
dB
41.5
42.5
43.5
dB
3
10
%
%
Gmf
DTMF Gain
Pin 14 > 1.6V
THDS
Tx Distortion
IL = 25mA
Vmic = -3dBm -GS
Vmic = -3dBm -GS + 15dB
80
110
10
50
12
57
Ze
Microphone Impedance
NTx
Tx Noise (psometric)
IL = 25mA
2KΩ at Pins 5-7
RS
Tx Attenuation in Mute Mode
IL = 25mA
Pin 14 > 1.6V
60
Gr
AGCr
Rx Gain Long Line
Line Lenght
IL = 25mA
29
-7
THD r
Rx Distortion
IL = 25mA
Vro = 500mV
Vro = 630mV
4/15
150
µA
Iimp
mA
mA
20
KΩ
-74
dBm
psoph
dB
30
-6
31
-5
dB
dB
3
10
%
%
NRx
Rx Noise
IL = 25mA
Rr
Rx Attenuation in Mute Mode
IL = 25mA
Pin = 14 > 2.7V
Gas
Antisidetone
IL = 25mA
22
Zac
AC Impedance
IL = 25mA
500
650
800
Ω
Grs
Confidence Level = VLINE/VREC
(in DTMF)
Pin 14 > 2.7V
35.5
38.5
41.5
dB
IST
Soft Clipping Current Level
Control (pin 10)
IL = 25mA; R9 = 100KΩ
IL = 25mA; R9 = 180KΩ
2.30
2.55
1.4
2.80
mA
µA
VST
Control Voltage Range (Pin 10)
VST = RST x IST
1
V
-74
dBmp
50
0
dB
dB
TEA7063
CIRCUIT DESCRIPTION
1. DC CHARACTERISTICS
1.1 VC (pin 17)
The stabilized voltage VC is connected to Vline
(pin 16) through an internal shunt regulator T1,
T2, which presents to the line a high AC impedance at frequecncies higher than 200Hz. At this
purpose the value of C1 (at pin 17) must be not
lower than 47µF (suggested value is 100µF).
The shunt regulator, T1 and T2, also controls the
extra current source, or power management, at
pin 12 (see also paragraph 6).
1.2 VLINE (pin 16)
The line voltage (pin 16) is determined by the
value of the external resistor R6 and by the internal current, Iint, flowing between VC (pin 17) and
Ground (see also paragr.: 1.1):
VLINE = VC + R 6 x Iint
VC is fixed by design at about 2.5V.
Iint is reversely related to R9:
Iint = 8 Volt/R9 + 60µA at IL > 25mA
Iint = 4 Volt/R9 + 60µA at IL = 6mA
where IL depends on ILB (see supply management)
VLINE must be externally adjusted (with R6) to
guarantee both DC and AC characteristic in accordance to the specific standard of the different
adminastrations.
Another adjustment of the DC characteristic is
possible with R9. Increasing the value of R9
causes a decrease of Iint and consequently a reduction of the product Iint x R9. (see also Paragraph 7)
Figure 1
Figure 2
5/15
TEA7063
2. TRANSMISSION CHAIN
2.1 A.G.C. In Transmission
The transmission gain between Microphone Input
(pin 7) and Vline (pin 16) is internally decreased
of 6dB when the line current varies from ILL to
ILS with a constant AC load of 600Ω.
The values of ILL (long line current) and ILS (short
line current) are programmable through I-start (pin
9) and I-slope (pin 15) (see also paragr. 4).
2.2 Sending Impedance
The impedance of the Output Stage Amplifier, Zout,
is determined by the impedance Z4 (at pin 3).
Zout = 10.65 xZ4
The total AC impedance shown to the line is the
parallel
Zpar = Z out//Zint//Zext
where:
Figure 3
6/15
- Zint = 10KΩ//8.5 nF (internal)
- Zext = R6//C4 (at pin 16)
2.3 Sending Mute
In normal speech operation (Vmute at pin 14 <
0.8V), the signal at Microphone Input (pin 7) is
amplified to Vline (pin 16) with the gain Gs (long
line) or 6dB lower (shorter lines) depending on
AGC control (see paragr. 4).
In sending mute condition (V 14 > 1.6V) these
gains are reduced of at least 60dB. In the same
condition, DTMF input (pin 6) is activated, with
gain Gmf to the line independent from Iline lenght.
2.4 Antisidetone Buffer
The signal coming from the sending preamplifier
is internally presented at pin 4 and than buffered
to pins 1 and 2 for sidetone cancellation (see
paragraph 3.2).
TEA7063
2.5 Soft Clipping
To avoid distortion on line, the TEA7063 has a
”soft clipping” on transmit channel.
The resistor (Rsoft) on pin 10 fixes the maximum
AC peak dynamic on the line: VSTL
VSTL(Vp) = Vpin16(DC) -1.44 •
Rsoft ( pin 10 )
R9 ( pin 8 )
where Rsoft ≤
470mV
1V
IST =
2 ⋅ R9 (pin8)
IST
The capacitor (C10) and the resistor (R10) connected on pin 11 fixe the constant time of the soft
clipping.
Recommended values: C10 = 150nF;
R10 = 560KΩ
Figure 4
Figure 5: Transmit Curves
7/15
TEA7063
3. RECEIVE CHAIN
3.1 A.G.C. In Receive
As described for the transmission chain, also the
receiving gains Gr, from pins 1 and 2 to pin 20,
have a reduction of 6dB when Iline moves from
ILL to ILS (see also paragr. 4).
3.2 Sidetone Compensation
The circuit is provided with a double anti-sidetone
network to optimize both at long and short lines.
In case double antisidetone network is not requested by the application needs, pins 1 and 2
can be connected to each other and 5 external
passive components can be saved (ZALL and
ZRL).
Before entering pins 1 and 2, the received signal
is areduced by the two attenating networks:
- ZALL/ZRL to pin 1 for long lines sidetone compensation,
- ZALS/ZRS to pin 2 for short lines sidetone compensation.
ZRL and ZRS define the total receive gains:
a)
V20
ZRL
= Gr •
for long lines
V16
ZRL + ZALL
b)
V20
ZRS
= ( Gr − 6dB ) •
for short lines
V16
ZRS + ZALS
ZALL and ZALS define the sidetone compensation of the circuit.
Figure 6
8/15
The equivalent balancing impedance is given by
the formula:
ZAL = K • ZALS + (1 - K) • ZALL
where:
-K = 0 at ILINE = ILL or lower (long line)
-K varies linearly from 0 to 1 with Iline between
ILL and ILS
-K = 1 at ILINE = ILS or higher (short line)..
Calculations to define ZALL and ZALS are:
a)
Zline ( long ) ⁄ ⁄ Zext ⁄ ⁄ Zint ⁄ ⁄ Zout
ZALL = 70 • R5 •
Zout
b)
Zline ( short ) ⁄ ⁄ Zext ⁄ ⁄ Zint ⁄ ⁄ Zout
ZALL =70• R5 •
Zout
where:
- Zext = R6//C4//(Zelectret) (at pin 13)
- Zint = 10KΩ//8.5nF (internal impedance)
- Zout = 10.65 • Z4 (at pin 3; see paragr. 2.2)
- Zline (short) and (long) are the impedances of
the line at minimum and naximum line lenght
- R5 = 5.1KΩ ±1% (typically)
3.3 AC Impedance
The total AC impedance of the circuit to the line
is:
ZAC = Zout//Zint//Zext (ZALS, ZALL >>ZAC)
3.4 Receive Mute (and confidence level)
When the receive channel is muted (Vpin 14 >
2.7V) the receive gain is reduced of 60dB minimum.
TEA7063
In this condition an internal connection is activated from line DTMF output (pin 16) to Receive
Output (pin 20) with an attenuation GRS = 38.5dB
to provide acoustic feedback of the DTMF emission.
4. A.G.C AND SIDETONE PROGRAMMING
4.1 Programmable Controls
AGC and sidetone attack and disonnect points (or
currents) are programmable externally through
two independents pins, I-start (pin 9) and I-slope
(pin 15).
4.2 I-Start (pin 9)
An external resistor RLL connected between Istart (pin 9) and Microprocessor Supply (pin 19)
controls the attack point of AGC and ZAL (antisidetone Z).
ILL is the line current at which the control starts.
Formulas for ILL and RLL with R9 = 100K are:
2880
ILL =
+ 11mA
RLL
2880
RLL =
( ILL − 11mA )
4.3 I-Slope (pin 15)
An external resistor RLS connected between
I-slope (pin 15) and Microprocessor Supply (pin
19) controls the disconnected point of AGC and
ZAS (antisidetone Z). ILS is the line current at
which the control stops. Formulas for ILS and
RLS with R9 = 100K are:
4680
+ ILL;
RLS
4680
RLS =
( ILS − ILL )
ILS =
4.4 A.G.C. OFF (pin 9 and 15)
Programming ILL and ILS respectively higher
than 70mA and 450mA is forcing the IC in AGC
OFF Condition.
Suggested external components are:
RLL = 51KΩ and RLS = 10KΩ
In this case sending, receiving gain and sidetone
compensation are independent of the line lenght.
Pins 1 and 2 can be connected to each other saving 5 passive external components at pin 2.
4.5 Secret Function for Private (pin 14)
The two separate thresholds for sending and Receiving Mute (pin 14) allow ”Secret Function”
(only microphone muted).
Pin 14 can be set:
a) between 0.25V and 0.8V for speech mode,
b) between 1.6V and 2.1V for ”secret” mode (microphone muted),
c) between 2.7V and 3.3V for ”all muted” mode
Figure 7
9/15
TEA7063
5. MICROPROCESSOR INTERFACE
5.1 Microprocessor Supply (pin 19)
At ”off-hook” the first priority of the circuit is to
make some current available at the Microprocessor Supply (pin 19) to charge quickly the external
capacitor C2.
This charging current is Icpm = 0.6 • ILINE
T-charge of about 10ms is necessary, with C2 =
47/µF. to charge pin 19 at the specified value of
3.3V typical at ILINE = 25mA:
T-charge =
3.3V • C2
typically
0.6 • ILINE
Vmp = 3.3V in normal operation and current increases linearly from 0.5mA min, at ILINE = 6mA,
to1.5mA, at ILINE = 25mA, remaining stable for
higher values of ILINE. (with R9 = 100K)
In general:
Imp =
130Volt
+ 0.3mA at IL > 25mA
R9
Imp =
11Volt
+ 0.3mA at IL > 6mA
R9
A zener of 3.9V typical is generally suggested to
Figure 8
6. CURRENT SOURCE FOR SPEAKERPHONE
6.1 Current Source (pin 12)
Most of the DC current available from the line is
delivered by the speech circuit at the output Isource
(pin 12) through an internal current generator.
Typical values of this current, lLS with R9 = 100K,
are:
ILS = (0.3 • ILINE)
for I LINE < 16.5mA
ILS = (0.9 • ILINE -10mA) for ILINE > 16.5mA
(ex: ILINE = 16mA then ILS = 5mA
Figure 9
10/15
ILINE = 30mA then ILS = 17mA
ILINE = 60mA then ILS = 44mA).
The voltage level at pin 12 must be defined by an
external regulator (i.e.: zener) and, if necessary,
filtered with a capacitor (47 to 220µF).
In case VLINE (at pin 16) approaches voltage at
pin 12, then the internal current source switches
off and its DC current is shunt to ground through
and internal complementary generator, thus
avoiding any negative effect on the AC and DC
impedances of the telephone set application.
TEA7063
7. INTERNAL DESCRIPTION OF CURRENT
MANAGEMENT
7.1 Internal Power Supply Management
R9 fixes the line power supply management.
R9 fixes the values of: Iear, Iup, Iref and ILS.
A current line information is used to modifie the
values of Iear, Iup, Iref and ILS between a minimum
and a maximum values.
On Fig 10:
The transmit output stage is represented by a current source (Itr). The I tr value depends of the DC
voltage on VLINE (pin 16) and RZAC value.
The other internal stages connected to VLINE (pin
16) are represented by a constant 1.3mA current
source.
7.2 DC Characteristics (internal)
The DC characteristic is equals to:
VLINE (pin 16) = VC (pin 17) + R6 • Iint
Iint is the sum of all the current sources connected on VC (pin 17):
[Ip + Iref + Vpin17 / (r7 + r8)]
- Ip is the bias internal operational amplifiers
power supply.
- Iref = 1 / 3 • (Vrefi / R9); with Vrefi = 470mV
- Iref = 156 / R9 mA
The current line information changes Iint value;
at low line current (6mA): Iint = 4V / R9 + 60µA
at low line current (IL = ILb): Iint =8V / R9 + 60µA
7.3 Microcontroller Supply (internal)
Iup = [(p2 / r2) • Iref + 0.3] mA = [(p2 / r2) • 156 /
R9) + 0.3] mA
The current line information changes p2/r2 value;
at low line current (6mA): p2 / r2 = 70
at a line current (IL = ILb): p2 / r2 = 820
7.4 Earphone Current Supply (internal)
Iear = (p1 / r1) • Iref mA = (p1 / r1) • (156 / R9) mA
The current line information changes p1/r1 value;
at low line current (6mA): (p1 / r1) = 200
at a line current (IL = ILb): p1 / r1 = 2700
The maximum peak dynamic on the earphone is:
Vpear = Zear • Iear
7.5 Transmit Output Stage (internal)
The output stage bias current depends of the DC
voltage on pin 16 and on RZAC impedance.
0.1425 • VLINE − 0.517
(RZ is the resistor
Itr =
RZ
connected betwee pin3 and the ground)
7.6 Loudspeaker Current Source (internal)
The current source for external peripherals has
two slopes:
- First slope; before Iear, Iup, Itr and Iint are stabilized at their maximum values: (IL = ILb)
ILS = 0.285 • IL
- Second slope; after Iear, Iup, Itr and Iint are stabilized at their maximum values: (for IL > ILb)
∆ (ILS) = 0.91 • ∆(ILINE
Iear, Iup, Itr and Iint are stabilized at their maximum
values between 16 and 26mA, the absolute IL
value depends of R9 value. The line current (ILb)
where Iear, Iup, Itr, Iint are stabilized at their maximum values and where the slope of ILS change
is:
Iear + Iup + Itr + Iint + 1.3
ILb =
0.715
7.7 Numerical Example
1) R9 = 100KΩ; R6 = 25KΩ
♦ DC characteristic = 6V for Iint max:
= 5V for Iint min:
Iint min (IL = 6mA) = 4 /100K + 60 = 100µA
Iint min (IL = ILb) = 8 /100K + 60 = 140µA
Vpin17 = 2.5V ⇒ R6 = 25KΩ ⇒
Vpin16 min (IL = 6mA) = 2.5 + 25 • 100E - 3 = 5V
Vpin16 max (IL = ILb) = 2.5 + 25 • 140E - 3 = 6V
♦ Current Sources
Iup min (IL = 6mA) = 0.4mA
Iup max (IL = ILb) = 1.6mA
Iear min (IL = 6mA) = 0.3mA
Iear max (IL = ILb) = 4.2mA
with RZ = 75Ω
Itr min (IL = 6mA) = 2.6mA
Itr max (IL = ILb) = 4.5mA
ILS min (IL = 6mA) = 1.3mA
♦ ILb 1.6 + 4.2 + 4.5 + 0.14 + 1.3
ILb =
mA
0.715
ILb = 16.5mA
ILS (for IL = ILb) = 0.285 • ILb = 4.7mA
♦ at IL = 100mA:
∆(ILS) = 0.91 • ∆(IL) = 0.91 • (100 - 16.5) = 76mA
ILS = 4.7 + 76 = 80.7mA
2) R9 = 56KΩ; R6 = 18KΩ
♦ DC characteristic = 6.1V for Iint max:
♦ ∆Χ χηαραχτε
= 4.8V for Iint min:
11/15
TEA7063
Iint min (IL = 6mA) = 4 /56K + 60 = 130µA
Iint min (IL = ILb) = 8 /56K + 60 = 200µA
Vpin17 = 2.5V ⇒ R6 = 18KΩ ⇒
Vpin16 min (IL = 6mA) = 2.5 + 18 • 130E - 3 = 4.85V
Vpin16 max (IL = ILb) = 2.5 + 18 • 200E - 3 = 6.1V
♦ Current Sources
Iup min (IL = 6mA) = 0.5mA
Iup max (IL = ILb) = 2.5mA
Iear min (IL = 6mA) = 0.55mA
Iear max (IL = ILb) = 7.5mA
with RZ = 75Ω
Figure 10: Line Power Supply Management
12/15
Itr min (IL = 6mA) = 2.35mA
Itr max (IL = ILb) = 4.5mA
ILS min (IL = 6mA) = 1.17mA
♦ ILb
2.5 + 7.5 + 4.5 + 0.2 + 1.3
ILb =
mA
0.715
ILb = 22.4mA
ILS (for IL = ILb) = 0.285 • ILb = 6.4mA
♦ at IL = 100mA:
∆(ILS) = 0.91 • ∆(IL) = 0.91 • (100 - 22.6) = 64mA
ILS = 6.4 + 64 = 70.4mA
TEA7063
SO20 PACKAGE MECHANICAL DATA
mm
DIM.
Min.
Typ.
A
a1
inch
Max.
Min.
Typ.
2.65
0.1
0.104
0.2
a2
Max.
0.004
0.008
2.45
0.096
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.013
C
0.5
0.020
45o (typ.)
c1
D
12.6
13.0
0.496
0.510
E
10
10.65
0.394
0.419
e
1.27
0.050
e3
11.43
0.450
F
7.4
7.6
0.291
0.300
L
0.5
1.27
0.020
0.050
M
S
0.75
0.030
o
8 (max.)
13/15
TEA7063
DIP20 PACKAGE MECHANICAL DATA
mm
DIM
Min.
a1
0.254
B
1.39
Typ.
Max.
Min.
Typ.
Max.
0.010
1.65
0.055
0.065
b
0.45
0.018
b1
0.25
0.010
D
25.4
1.000
E
8.5
0.335
e
2.54
0.100
e3
22.86
0.900
F
7.1
0.280
i
3.93
0.155
L
Z
14/15
inch
3.3
0.130
1.34
0.053
TEA7063
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics.
 1994 SGS-THOMSON Microelectronics - All Rights Reserved
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15/15