TCD2561D TOSHIBA CCD Linear Image Sensor CCD (charge coupled device) TCD2561D The TCD2561D is a high sensitive and low dark current 5340 elements × 4 line CCD color image sensor which includes CCD drive circuit, clamp circuit. The sensor is designed for scanner. The device contains a row of 5340 elements × 4 line photodiodes which provide a 24 lines/mm across a A4 size paper. The device is operated by 5 V pulse and 12 V power supply. Features · Number of image sensing elements: 5340 elements × 4 line · Image sensing element size: 7 µm × 7 µm on 7 µm centers · Photo sensing region: High sensitive PN photodiode · Distanced between photodiode array: Color (28 µm, 4 lines), B/W-color (56 µm, 8 lines) · Clock: 2 phase (5 V) · Power supply: 12 V power supply voltage · Internal circuit: Clamp circuit · Package: 22 Pin CERDIP package · Color filter: Red, green, blue Weight: 5.2 g (typ.) Pin Connections (top view) OS3 1 SS Unit 22 OS2 2 21 OS1 RS 3 20 OD CP 4 19 SS SW 2 5 18 SW 1 17 f2A3 16 NC Characteristic 1 1 1 1 Maximum Ratings (Note1) Symbol Rating VB V Shift pulse voltage VSH V Reset pulse voltage V RS Clamp pulse voltage V CP V f1A3 6 Changeover switch voltage V SW V SS 7 Power supply voltage VOD -0.3~15 V f2A2 8 15 f2A1 Operating temperature Topr 0~60 °C °C f1A2 14 Tstg -25~85 9 Storage temperature f1A1 SH3 10 13 SH0 12 SH1 V Note 1: All voltage are with respect to SS terminals (ground). SH2 11 1 5340 5340 5340 5340 -0.3~8.0 Red Green Blue Black & White Clock pulse voltage 2001-12-06 TCD2561D Circuit Diagram OD SS SW 1 20 19 18 f1A3 f2A3 6 Clamp 17 CCD ANALOG SHIFT REGISTER (EVEN) SW1 13 SH0 Ｄ148 D149 PHOTO DIODE (Black & White) S5338 S5339 S5340 D128 D125 D126 D127 S1 S2 D26 D27 D28 SHIFT GATE SH0 SHIFT GATE SH0 Clamp CCD ANALOG SHIFT REGISTER (ODD) Ｄ148 D149 PHOTO DIODE (blue) S5338 S5339 S5340 D128 D125 D126 D127 S1 S2 D26 D27 D28 SW1 12 SH1 SHIFT GATE SH1 SW2 14 f1A1 15 f2A1 Ｄ148 D149 PHOTO DIODE (green) S5338 S5339 S5340 D128 CCD ANALOG SHIFT REGISTER D26 D27 D28 Clamp D125 D126 D127 S1 S2 OS1 21 11 SH2 SHIFT GATE SH2 SW2 Ｄ148 D149 PHOTO DIODE (red) S5338 S5339 S5340 D128 CCD ANALOG SHIFT REGISTER D26 D27 D28 Clamp D125 D126 D127 S1 S2 OS2 22 10 SH3 SHIFT GATE SH3 OS3 1 Clamp CCD ANALOG SHIFT REGISTER 5 4 3 7 SW 2 CP RS SS 9 8 f1A2 f2A2 Pin Names OS3 Signal Output 3 (red) OS2 Signal Output 2 (green) SS Ground OS1 Signal Output 1 (blue) RS Reset Gate OD Power CP Clamp Gate SS Ground SW 2 Changeover Switch 2 (color and B/W) SW 1 Changeover Switch 1 (color and B/W) f1A3 Clock 3 (phase 1) f2A3 Clock 3 (phase 2) SS Ground NC Non Connection f2A2 Clock 2 (phase 2) f2A1 Clock 1 (phase 2) f1A2 Clock 2 (phase 1) f1A1 Clock 1 (phase 1) SH3 Shift Gate 3 SH0 Shift Gate 0 SH2 Shift Gate 2 SH1 Shift Gate 1 2 2001-12-06 TCD2561D Optical/Electrical Characteristics (Ta = 25°C, VOD = 12 V, VB = VRS = VSH = VCP = 5 V (pulse), fB = 1.0 MHz, fRS = 1.0 MHz, LOAD RESISTANCE = 100 kW W, tINT (INTEGRATION TIME) = 10 ms, LIGHT SOURCE = A LIGHT SOURCE + CM500S FILTER (t = 1.0 mm)) Characteristics Sensitivity Symbol Min Typ. Max RB/W 16.8 21.0 25.2 RR 6.3 9.0 11.7 RG 7.3 10.5 13.7 Unit Note V/(lx･s) (Note 2) RB 3.8 5.5 7.2 PRNU (1) ¾ 10 20 % (Note 3) PRNU (3) ¾ 3 12 mV (Note 4) IL ¾ 1 ¾ % (Note 5) Saturation output voltage (B/W) VSAT (B/W) 1.5 2.0 ¾ V (Note 6) Saturation output voltage (color) VSAT (color) 3.2 3.5 ¾ V (Note 6) Saturation exposure SE ¾ 0.1 ¾ lx･s (Note 7) Dark signal voltage VDRK ¾ 0.4 2.0 mV (Note 8) Dark signal non uniformity DSNU ¾ 7 12 mV (Note 8) DC power dissipation PD ¾ 480 690 mW ¾ Total transfer efficiency TTE 92 ¾ ¾ % ¾ Output impedance ZO ¾ 0.3 1.0 kW ¾ DC signal output voltage VOS 5.0 6.0 7.0 V (Note 9) Random noise NDI ¾ 1.0 ¾ mV (Note 10) VRSN ¾ 0.5 1.0 V (Note 9) Photo response non uniformity Image lag Reset noise Note 2: Sensitivity is defined for each color of signal outputs average when the photosensitive surface is applied with the light of uniform illumination and uniform color temperature. Note 3: PRNU (1) is defined for each color on a single chip by the expressions below when the photosensitive surface is applied with the light of uniform illumination and uniform color temperature. DX PRNU (1) = ´ 100 (%) X When X is average of total signal output and DX is the maximum deviation from X . The amount of incident light is shown below. 1 1 1 Red = SE, Green = SE, Blue = SE 2 2 4 Note 4: PRNU (3) is defined as maximum voltage with next pixel, where measured 5% of SE (typ.) 3 2001-12-06 TCD2561D Note 5: Image Lag is defined as follows. SH ON OFF LED OS Image Lag Signal (500 mV) Note 6: VSAT is defined as minimum saturation output of all effective pixels. V Note 7: Definition of SE: SE = SAT (lx･s) RB/W Note 8: VDRK is defined as average dark signal voltage of all effective pixels. DSNU is defined as different voltage between VDRK and VMDK when VMDK is maximum dark signal voltage. VDRK VMDK DSNU Note 9: DC signal Output Voltage and Reset Noise is defined as follows, but Reset Noise is a fixed pattern noise. VRSN OS VOS SS 4 2001-12-06 TCD2561D Note 10: Random noise is defined as the standard deviation (sigma) of the output level difference between two adjacent effective pixels under no illumination (i.e. dark conditions) calculated by the following procedure. video output video output 200 ns 200 ns pixel (n) DV pixel (n + 1) Output waveform (effective pixels under dark condition) (1) (2) (3) (4) Two adjacent pixels (pixel n and n + 1) in one reading are fixed as measurement points. Each of the output level at video output periods averaged over 200 ns period to get V (n) and V (n + 1). V (n + 1) is subtracted from V (n) to get DV. DV = V (n) - V (n + 1) The standard deviation of DV is calculated after procedure (2) and (3) are repeated 30 times (30 readings) DV = (5) (6) 30 1 30 å DVi 30 i =1 s= 2 1 (| DVi | －DV ) 30 iå =1 Procedure (2), (3) and (4) are repeated 10 times to get sigma value. 10 sigma values are averaged. 10 s = 1 åsj 10 j=1 (7) I value calculated using the above procedure is observed 2 times larger than that measured relative to the ground level. So we specify random noise as follows. N DI = 1 s 2 5 2001-12-06 TCD2561D Operating Condition Characteristics Clock pulse voltage Symbol “H” Level “L” Level Min Typ. Max 4.5 5.0 5.5 0 ¾ 0.5 4.5 5.0 5.5 0 ¾ 0.5 4.5 5.0 5.5 0 ¾ 0.5 4.5 5.0 5.5 0 ¾ 0.5 4.5 5.0 5.5 0 ¾ 0.5 11.4 12.0 13.0 VBA “H” Level Shift pulse voltage “L” Level VSH “H” Level Reset pulse voltage “L” Level V RS “H” Level Clamp pulse voltage “L” Level V CP “H” Level Switch pulse voltage “L” Level Power supply voltage V SW VOD Unit Note V V V V V V Clock Characteristics (Ta = 25°C) Characteristics Symbol Min Typ. Max Unit Clock pulse frequency fB 0.3 1.0 10 MHz Reset pulse frequency f RS 0.3 1.0 10 MHz Clamp pulse frequency f CP 0.3 1.0 10 MHz Clock1 capacitance (Note 11) CB1 ¾ 160 240 pF Clock2 capacitance (Note 11) CB2 ¾ 130 195 pF Shift gate capacitance CSH ¾ 30 60 pF Reset gate capacitance CRS ¾ 10 40 pF Clamp gate capacitance CCP ¾ 10 40 pF Switch gate capacitance CSW ¾ 10 40 pF Note 11: VOD = 12 V 6 2001-12-06 TCD2561D Timing Chart 1: Bit Clamp Mode (color or B/W mode) tINT (integration time) SH f1A f2A RS CP D149 D148 D147 D146 D145 D134 D133 D132 D131 D130 D129 D128 S5340 S2618 S2617 S2616 S2610 S2609 S2608 S2607 S2606 S1 D127 D126 D125 D124 D123 D122 D121 D64 D63 D62 D61 D60 D26 D25 D13 D12 D1 D0 OS1, 2, 3 (color) DUMMY OUTPUTS (26 elements) DUMMY OUTPUTS LIGHT SHIELD OUTPUTS (96 elements) (6 elements) (6 elements) DUMMY OUTPUTS (128 elements) SIGNAL OUTPUTS (5340 elements) (12 elements) TEST OUTPUTS (1 elements) DUMMY OUTPUTS (3 elements) DUMMY OUTPUTS (22 elements) 1 LINE READOUT PERIOD (5490 elements) D52 D120 D122 D124 D126 S1 S115 S117 S119 S121 S123 S125 S127 S129 S5339 D128 D130 D132 D134 D146 D148 D53 D121 D123 D125 D127 S2 S116 S118 S120 S122 S124 S126 S128 S130 S5340 D129 D131 D133 D135 D147 D149 D25 D51 D24 D3 D50 D2 D1 D26 D0 OS2 (B/W) D27 OS1 (B/W) DUMMY OUTPUTS (13 elements) LIGHT SHIELD OUTPUTS (3 elements) (48 elements) DUMMY OUTPUTS (64 elements) (3 elements) DUMMY OUTPUTS (6 elements) TEST OUTPUT (1 element) DUMMY OUTPUT (1 element) DUMMY OUTPUTS (11 elements) SIGNAL OUTPUTS (2670 elements) 1 LINE READOUT PERIOD (2745 elements) 7 2001-12-06 TCD2561D Timing Chart 2: Line Clamp Mode (color or B/W mode) tINT (integration time) SH f1A f2A RS CP = SH CP = “H” D149 D148 D147 D146 D145 D134 D133 D132 D131 D130 D129 D128 S5340 S2618 S2617 S2616 S2610 S2609 S2608 S2607 S2606 S1 D127 D126 D125 D124 D123 D122 D121 D64 D63 D62 D61 D60 D26 D25 D13 D12 D1 D0 OS1, 2, 3 (color) DUMMY OUTPUTS (26 elements) DUMMY OUTPUTS LIGHT SHIELD OUTPUTS (96 elements) (6 elements) (6 elements) DUMMY OUTPUTS (128 elements) SIGNAL OUTPUTS (5340 elements) (12 elements) TEST OUTPUTS (1 elements) DUMMY OUTPUTS (3 elements) DUMMY OUTPUTS (22 elements) 1 LINE READOUT PERIOD (5490 elements) D52 D120 D122 D124 D126 S1 S115 S117 S119 S121 S123 S125 S127 S129 S5339 D128 D130 D132 D134 D146 D148 D53 D121 D123 D125 D127 S2 S116 S118 S120 S122 S124 S126 S128 S130 S5340 D129 D131 D133 D135 D147 D149 D25 D51 D24 D3 D50 D2 D1 D26 D0 OS2 (B/W) D27 OS1 (B/W) DUMMY OUTPUTS (13 elements) LIGHT SHIELD OUTPUTS (3 elements) (48 elements) DUMMY OUTPUTS (64 elements) (3 elements) DUMMY OUTPUTS (6 elements) TEST OUTPUT (1 element) DUMMY OUTPUT (1 element) DUMMY OUTPUTS (11 elements) SIGNAL OUTPUTS (2670 elements) 1 LINE READOUT PERIOD (2745 elements) 8 2001-12-06 D147 D134 D135 D132 D133 D130 D131 D128 D129 S5399 S5340 S1 S2 D126 D127 D124 D125 D122 D123 D120 D121 D26 D27 D24 D25 D2 D1 D148 D148 D147 D147 D146 D146 D145 D145 D134 D134 D133 D133 D132 D132 D128 D128 S5340 S5340 S1 S1 D127 D127 D123 D123 D122 D122 D121 D121 D26 D26 D25 D25 D1 D1 D0 D0 1 LINE READOUT PERIOD (5490 elements) D149 OS2 (green) D149 OS1 (blue) SW 2 SW 1 CP RS f2A f1A SH Timing Chart 3 (color ® B/W mode) tINT (integration time) 9 D0 D3 OS2 (B/W) D146 OS1 (B/W) D149 1 LINE READOUT PERIOD (2745 elements) 2001-12-06 TCD2561D D148 TCD2561D Timing Requirements t2 t3 t4 SH f1 t1 t5 f2 f1A GND 3.5 V (max) 1.5 V (min) RS t6 CP t7 CP = SH (line clamp mode) t8 B/W ® Color mode: SW 1 (“L” ® “H”) Color ® B/W mode: SW 2 (“L” ® “H”) B/W ® Color mode: SW 2 (“H” ® “L”) Color ® B/W mode: SW 1 (“H” ® “L”) f1 10% t10 t9 f2 10% t11 t12 90% RS t13 t14 t16 t15 t17 90% CP t18 t20 t19 10% to the peak OS (bit clamp mode) Peak 10% Video signal 10% to the peak OS (line clamp mode) t21 10 2001-12-06 TCD2561D Timing Requirements (cont.) Symbol Min Typ. (Note 12) Max t1 120 1000 ¾ t5 800 1000 ¾ t2, t4 0 50 ¾ ns SH pulse width t3 3000 5000 ¾ ns Pulse timing of SH and CP t6 200 500 ¾ ns Pulse timing of SH and CP (line clamp mode) t7 10 100 ¾ ns Pulse timing of SH and SW t8 100 500 t3 - 100 ns Characteristics Pulse timing of SH and f1 SH pulse rise time, fall time Unit ns f1, f2 pulse rise time, fall time t9, t10 0 50 ¾ ns RS pulse rise time, fall time t11, t12 0 20 ¾ ns RS pulse width t13 10 (20) 80 ¾ ns Pulse timing of RS and CP t14 0 40 ¾ ns Pulse timing of f1A, f2A and CP t15 0 20 ¾ ns t16, t17 0 20 ¾ ns t18 30 (3000) 80 (5000) ¾ ns t19 ¾ 20 40 (Note 16) ns t20 ¾ 20 40 (Note 15) ns t21 ¾ 30 50 (Note 16) ns CP pulse rise time, fall time CP pulse width (Note 13) Reference level settle time (bit clamp mode) Video data delay time (Note 14) Reference level settle time (line clamp mode) Note 12: Typ. is the case of f RS = 1.0 MHz. Note 13: Line clamp Mode inside ( ). Note 14: Load Resistance is 100 kW. Note 15: Typical settle time to about 1% of final value. Note 16: Typical settle time to about 1% of the peak. Clamp Mode Clamp Means CP Input Pulse Bit Clamp CP Pulse Line Clamp “H” or SH Changeover Switch Mode Output Type SW1 Input Pulse SW 2 Input Pulse Color “H” “L” B/W “L” “H” 11 2001-12-06 TCD2561D Typical Spectral Response Spectral response 1.0 Ta = 25°C Red Relative response 0.8 0.6 Blue Green 0.4 0.2 0 400 450 500 550 Wavelength l 12 600 650 700 (nm) 2001-12-06 TCD2561D Typical Drive Circuit +5 V 47 mF/25 V SW 1 12 V 1 mF/25 V SW 2 IC5 1 mF/25 V +5 V 47 mF/25 V f1A1 1 mF/25 V 47 mF/25 V f2A1 22 21 20 19 OS2 OS1 OD SS 18 17 SW 1 f2A3 16 15 14 13 12 NC f2A1 f1A1 SH0 SH1 IC1 +5 V TCD2561D OS3 SS 1 2 RS CP 3 4 SW 2 f1A3 5 6 SS 7 f2A2 f1A2 SH3 SH2 8 9 10 11 f1A2 1 mF/25 V 47 mF/25 V f2A2 IC2 +5 V f1A3 1 mF/25 V 47 mF/25 V f2A3 12 V 1 mF/25 V IC3 +5 V 47 mF/25 V 1 mF/25 V 47 mF/25 V OS1 SH0 OS2 SH1 OS3 SH2 SH3 CP IC1, 2, 3 : TC74AC04 IC4, 5 : TC74HC04 RS IC4 13 2001-12-06 TCD2561D Caution 1. Window Glass The dust and stain on the glass window of the package degrade optical performance of CCD sensor. Keep the glass window clean by saturating a cotton swab in alcohol and lightly wiping the surface, and allow the glass to dry, by blowing with filtered dry N2. Care should be taken to avoid mechanical or thermal shock because the glass window is easily to damage. 2. Electrostatic Breakdown Store in shorting clip or in conductive foam to avoid electrostatic breakdown. CCD Image Sensor is protected against static electricity, but interior puncture mode device due to static electricity is sometimes detected. In handing the device, it is necessary to execute the following static electricity preventive measures, in order to prevent the trouble rate increase of the manufacturing system due to static electricity. a. Prevent the generation of static electricity due to friction by making the work with bare hands or by putting on cotton gloves and non-charging working clothes. b. Discharge the static electricity by providing earth plate or earth wire on the floor, door or stand of the work room. c. Ground the tools such as soldering iron, radio cutting pliers of or pincer. It is not necessarily required to execute all precaution items for static electricity. It is all right to mitigate the precautions by confirming that the trouble rate within the prescribed range. 3. Incident Light CCD sensor is sensitive to infrared light. Note that infrared light component degrades resolution and PRNU of CCD sensor. 4. Lead Frame Forming Since this package is not strong against mechanical stress, you should not reform the lead frame. We recommend to use a IC-inserter when you assemble to PCB. 5. Soldering Soldering by the solder flow method cannot be guaranteed because this method may have deleterious effects on prevention of window glass soiling and heat resistance. Using a soldering iron, complete soldering within ten seconds for lead temperatures of up to 260°C, or within three seconds for lead temperatures of up to 350°C. 14 2001-12-06 TCD2561D Package Dimensions Weight: 5.2 g (typ.) 15 2001-12-06 TCD2561D RESTRICTIONS ON PRODUCT USE 000707EBA · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 16 2001-12-06